Lecture 3 - Design Challenges
Lecture 3 - Design Challenges
Lecture 3
Design Challenges
2
Design Evolution
3
Challenges in VLSI Design
4
Power Dissipation
105 103
18KW
104 5KW 102 Switching
1.5KW
101
Power (W)
Power (Watts)
103 500W
Pentium® proc 100
102
10-1
486
10 8086 386
10-2
8080
1 4004 10-3
Leakage
0.1 10-4
1971 1974 1978 1985 1992 2000 2004 2008 10m 1m 100nm 10nm
Year Technology node
5
Even Worse: Power Density
10000
Rocket
Power Density (W/cm2)
1000 Nozzle
Nuclear
100 Reactor
Hot Plate
8086
10 P6
4004
8008 8085 386 Pentium
286 486
8080
1
1970 1980 1990 2000 2010
Source: Intel
Year
Power per (transistor switching) does go down with
technology scaling
6
Design Innovation Demanded
14
8 Fujitsu VP2000
IBM 3090S IBM RY5
NTT
6 IBM RY7
Fujitsu M-780
Pulsar
4 IBM3090
CDC Cyber 205 IBM RY6
IBM4381
IBM3084 IBM RY4
2 IBM370 Fujitsu
Apache
IBM360 IBM3033 M380 Pentium II
0
1950 1960 1970 1980 1990 2000 2010
Year of Announcement
Process variations
Dynamic uncertainties:
‒ Temperature
‒ Power supply (Ldi/dt noise)
‒ Crosstalk
‒ Soft error
8
Cost of Integrated Circuits
9
NRE Cost
10
Recurrent Cost
Cost per M Gates
(IBS, 2014)
11
Design Trend I: Integration
Small Power
Signal RF RF
Power
Management
Analog
Baseband
Digital Baseband
(DSP + MCU)
12
Design Trend II: Parallelism
Concurrency for
better reliability,
programmability, and
cost factor
Examples:
‒ Multiple cores
‒ Array structure
13
Summary
14
Quiz 3
Answer
(d) All of the above
15