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Lecture 18

The document discusses cache memory in computer organization and architecture, focusing on mapping functions for main memory blocks to cache lines. It covers three techniques: Direct, Associative, and Set Associative mapping, detailing their structures, advantages, and disadvantages. The document also highlights performance differences between direct and set associative caches as cache size increases.

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Amaresh Swain
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31 views21 pages

Lecture 18

The document discusses cache memory in computer organization and architecture, focusing on mapping functions for main memory blocks to cache lines. It covers three techniques: Direct, Associative, and Set Associative mapping, detailing their structures, advantages, and disadvantages. The document also highlights performance differences between direct and set associative caches as cache size increases.

Uploaded by

Amaresh Swain
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Computer Organization

and Architecture
(EET 2211)

1 Computer Organization and Architecture


Chapter 4
CACHE MEMORY

2 Computer Organization and Architecture


Mapping Function
Ø Algorithm needed for mapping main memory blocks to
cache lines
Ø A means is needed to determining which main memory
block currently occupies a cache line
Ø Three Techniques:
1. Direct
2. Associative
3. Set Associative

3 Computer Organization and Architecture


Associative Mapping

 A main memory block can load into any line of cache


 Memory address is interpreted as tag and word
 Tag uniquely identifies block of memory
 Every line’s tag is examined for a match
 Cache searching gets expensive

4 Computer Organization and Architecture


Associative Mapping from
Cache to Main Memory

5 Computer Organization and Architecture


Fully Associative Cache Organization

6 Computer Organization and Architecture


Associative
Mapping
Example

7 Computer Organization and Architecture


8 Computer Organization and Architecture
Addressing Structure

Word
Tag 22 bit 2 bit
 22 bit tag stored with each 32 bit block of data
 Compare tag field with tag entry in cache to check for hit
 Least significant 2 bits of address identify which 16 bit word is
required from 32 bit data block
 e.g.
 Address Tag Data Cache line
 FFFFFC FFFFFC 24682468 3FFF

9 Computer Organization and Architecture


Associative Mapping Summary
 Address length = (s + w) bits
 Number of addressable units = 2^(s+w) words or bytes
 Block size = line size = 2^w words or bytes
 Number of blocks in main memory = 2^(s+ w)/2^(w)= 2^s
 Number of lines in cache = undetermined
 Size of tag = s bits
There is flexibility as which block to replace when a new
block is read into the cache.
Disadvantage- complex circuitry required to examine the
tags of all cache lines in parallel.

10 Computer Organization and Architecture


Set Associative Mapping
 Cache is divided into a number of sets
 Each set contains a number of lines
 A given block maps to any line in a given set
 e.g. Block B can be in any line of set i
 e.g. 2 lines per set
 2 way associative mapping
 A given block can be in one of 2 lines in only one set

11 Computer Organization and Architecture


Set Associative Mapping Example
 In this case the cache consists of number of sets, each of which
consists of a number of lines. The relationships are
m =v * k
i = j modulo v
where
i = cache set number
j = main memory block number
m = number of lines in the cache
v = number of sets
k = number of lines in each set

12 Computer Organization and Architecture


Mapping From Main Memory to Cache : v Associative

13 Computer Organization and Architecture


Mapping From Main Memory to Cache : k-way
Associative

14 Computer Organization and Architecture


K-Way Set Associative Cache Organization

15 Computer Organization and Architecture


Set Associative Mapping Summary

 Address length = (s + w) bits


 Number of addressable units = 2^(s + w) words or bytes
 Block size = line size = 2^w words or bytes
 Number of blocks in main memory = 2^s
 Number of lines in set = k
 Number of sets = v = 2^d
 Number of lines in cache =m= kv = k * 2^(d)
 Size of cache =k * 2^(d + w)
 Size of tag = (s – d) bits

16 Computer Organization and Architecture


Set Associative Mapping Address Structure

Word
Tag 9 bit Set 13 bit 2 bit

 Use set field to determine cache set to look in


 Compare tag field to see if we have a hit
 e.g
 Address Tag Data Set number
 1FF 7FFC 1FF 12345678 1FFF
 001 7FFC 001 11223344 1FFF

17 Computer Organization and Architecture


Two Way Set Associative Mapping Example

18 Computer Organization and Architecture


Varying Associativity over Cache Size

19 Computer Organization and Architecture


Direct and Set Associative Cache Performance
Differences
 Significant up to at least 64kB for 2-way
 Difference between 2-way and 4-way at 4kB much less than
4kB to 8kB in cache size
 Cache complexity increases with associativity
 Not justified against increasing cache to 8kB or 16kB
 Beyond about 32kB gives no improvement in performance

20 Computer Organization and Architecture


Thank You !

21 Computer Organization and Architecture

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