8086 Interfacing

I/O Interfacing
Memory Interfacing

Dr. Dipti Mishra, Mahindra University Ecole Centrale School of

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Engineering, Hyderabad
Interfacing

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 •A15 - A8 (Higher Address Bus)
•AD7 - AD0(Lower Address/Data Bus)
•ALE
•RD
•WR
•READY

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 Dr. Dipti Mishra, Mahindra University Ecole Centrale School of
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I/O Mapped I/O
• 8086 has special instructions IN and OUT to transfer data through the
input/output ports in I/O mapped I/O system.
• The IN instruction copies data from a port to the Accumulator. If an 8-
bit port is read data will go to AL and if 16-bit port is read the data will
go to AX.
• The OUT instruction copies a byte from AL or a word from AX to the
specified port. The M/IO signal is always low when 8086 is executing
these instructions.
• In this address of I/O device is 8-bit or 16-bit. It is 8-bit for Direct
addressing and 16-bit for Indirect addressing.
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Memory Mapped I/O
• In this type of I/O interfacing, the 8086 uses 20 address lines to
identify an I/O device.
• The I/O device is connected as if it is a memory device.
• The 8086 uses the same control signals and instructions to access I/O
as those of memory, here RD and WR signals are activated indicating
the memory bus cycle.

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 Dr. Dipti Mishra, Mahindra University Ecole Centrale School of
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Engineering, Hyderabad
• To read or write 8 bits of data, it would require only 1 CPU cycle, no matter the data is stored in any of
the memory banks, but to read or write 16 bits of data, the BIU of the 8086 may require either 1 or 2
memory cycles depending upon whether the lower byte of word is located at even or odd memory
address.
• If the lower byte of the word is stored at even memory bank and the upper byte is stored at odd
memory bank then the CPU will require only 1 memory cycle. So, it is better to store data in this way.

• If the lower byte of the word is located at an odd memory address, then the CPU will require 2 memory
cycles. The first memory cycle is required for accessing the lower byte of the word through the higher
data bus, i.e. D15 to D8, and the second memory cycle is required for accessing the upper byte of the
word through the lower data bus, i.e. D7 to D0.
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 Memory Devices
• Simple or complex, every microprocessor-based system has a memory
system.
• Introduction: Memory is simply a device that can store information.
• The semiconductor memories are extensively used because of their small
size, low cost, high speed, high reliability & ease of memory size expansion.
• It consists of mainly flip-flops & some additional circuitry such as buffers, one
flip-flop can hold one bit of data.
• Memory fundamentals: Memory capacity. The no. of bits that a
semiconductor memory chip can store is called its chip capacity.
Almost all systems contain four common types of memory:
♦ Read-only memory (ROM)
♦ Flash memory (EEPROM)
♦ Static Random access memory (SARAM)
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Dynamic Random access
♦10/10/2024 memory (DRAM).
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Static Random Access Memory (SRAM)
• A Static RAM is a volatile memory device which means that the
contents of the memory array will be lost if power is removed.
• Unlike a dynamic memory device, static memory does not require a
periodical refresh cycle and generally runs much faster than a
dynamic memory device.
• Static RAM is used when the size of the read/write memory is
relatively small, today, a small memory is less than 1M byte.
• The main difference between ROM and RAM is that RAM is written
under normal operation, whereas ROM is programmed outside the
computer and normally is only read.
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 Dynamic Random Access Memory (DRAM)
• Available up to 256M X 8 (2G bits).
• DRAM is essentially the same as SRAM, except that it retains data for only 2
or 4 ms on an integrated capacitor.
• After 2 or 4 ms, the contents of the DRAM must be completely rewritten
(refreshed), because the capacitors, which store a logic 1 or logic 0, lose their
charges.

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 Read Only Memory (ROM)
• Read-only memory (ROM) permanently stores programs/data resident to the system, and must not
change when power disconnected
• Often called nonvolatile memory, because its contents do not change even if power is disconnected.
• The EPROM (erasable programmable read-only memory) is programmed on an EPROM programmer in
the field.
• Also erasable if exposed to high-intensity ultraviolet light, depending on the type of EPROM.
• The PROM (programmable read-only memory) is also programmed in the field by burning open tiny
NIchrome or silicon oxide fuses. Once it is programmed, it cannot be erased.
• A newer type of read-mostly memory (RMM) is called flash memory.
• Flash memory is also often called an EEPROM (electrically erasable programmable ROM), EAROM
(electrically alterable ROM) or a NOVRAM (nonvolatile RAM)
• Electrically erasable in the system, but they require more time to erase than normal RAM.
• The flash memory device is used to store setup information for systems such as the video card in the
computer.

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Engineering, Hyderabad
 8086 Memory Interface
• The memory address space of the 8086-based microcomputers has different logical and physical
organizations.
• Logically, memory is implemented as a single 1M × 8 memory chunk.
• The byte-wide storage locations are assigned consecutive addresses over the range from 00000H
through FFFFFH
• Physically, memory is implemented as two independent 512 Kbyte banks: the low (even) bank and the
high (odd) bank. Data bytes associated with an even address (00000H, 00002H, etc.) reside in the low
bank, and those with odd addresses (00001H, 00003H, etc.) reside in the high bank.
• Address bits A1 through A19 select the storage location that is to be accessed. They are applied to both
banks in parallel. A0 and bank high enable (BHE) are used as bank-select signals.
• The memory locations 00000-FFFFF are designed as odd and even bytes. To distinguish between odd
and even bytes, the CPU provides a signal called BHE (bus high enable).
• BHE and A0 are used to select the odd and even byte, as shown in the table below.
BHE A0 Function
0 0 Choose both odd and even memory bank
0 1 Choose only odd memory bank
1 0 Choose only even memory bank
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Minimum mode Memory Interface
• The control signals provided to support the interface to
the memory subsystem are ALE, M/IO , DT/R, RD, WR,
DEN and BHE
• When Address latch enable (ALE) is logic 1 it signals that a
valid address is on the bus.
• This address can be latched in external circuitry on the 1-
to-0 edge of the pulse at ALE.
• M IO (memory/IO) and DT/R tell external circuitry
whether a memory or I/O transfer is taking place over the
bus and whether the 8086 will transmit or receive data
over the bus.
• The bank high enable (BHE) signal is used as a memory
enable signal for the most significant byte half of the data
bus, D8 through D15.
• The WR (write) and RD (read) signals indicate that a write
or read bus cycle is in progress.
• DEN (data enable), is also supplied. It enables external
devices to supply data to the microprocessor.
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Engineering, Hyderabad
 • In maximum mode, the 8086 not
directly provides all control signal
to support the memory interface.
• Instead, an external Bus Controller
(8288) provides memory
commands and control signals as
shown in figure.

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Engineering, Hyderabad
 Memory expansion

• In many applications, the microcomputer system requirement for memory

is greater than what is available in a single device. There are two basic
reasons for expanding memory capacity:

❖ The byte-wide length is not large enough

❖ The total storage capacity is not enough bytes.
❖Both of these expansion needs can be satisfied by interconnecting some
ICs.

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Engineering, Hyderabad
 Dr. Dipti Mishra, Mahindra University Ecole Centrale School of
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Engineering, Hyderabad
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Engineering, Hyderabad
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Engineering, Hyderabad
 Dr. Dipti Mishra, Mahindra University Ecole Centrale School of
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Engineering, Hyderabad