Sindhi college

BCA

Second Semester

Computer Architecture
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Chapter-1
Digital logic circuits
―It is concerned with the structure and behavior of the computer as seen by the user .it
includes the information, formats, instruction set, addressing modes.‖

The architectural design of a computer system is concerned with the specifications of the
various functional modules, such as processors and memories and structuring them together into
a computer system

Types of Computer architecture

Von Neumann architecture
Harvard architecture

Von Neumann architecture

The von Neumann architecture is a design model for a stored-program digital computer that uses
a processing unit and a single separate storage structure to hold both instruction and data The
structure of computer system is composed of the following components:
The arithmetic logic unit(ALU) performs the computer‘s computational and logical
functions
Main memory or fast memory is called the random access memory(RAM)
Control unit (CU) that directs other components of the computer to perform certain
actions such as fetching data or instructions from memory to be processed by ALU.
Interface between the user and the computer such as input output devices such as
keyboard or monitor
Instructions are carried out sequentially, one instruction at a time

Harvard architecture
It uses separate store and signal pathways for their instructions and data.
The term originate from the Harvard mark-relay based computer, which stored
instructions on punched tape(24 bits wide) and data in relay latches(23 digits wide)
The CPU can read both an instruction and data from memory at same time ,even without
a cache, leading to double the memory bandwidth

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Different program and data bus widths are possible ,allowing program and data memory to be
better optimized to the architectural requirements

Comparison between von Neumann and Harvard architecture

Von Neumann Architecture Harvard Architecture

Program and data are stored in

the same memory and
Managed by The same Program and data are stored and
information handling subsystem handled by different subsystem

There is increased efficiency in Program handling task and data

designing ,implementing and handlingtaskaredifferent,
operating one memory resulting in not so efficient system
It can be slower It can be much faster
ex:Desktop personal computer ex:Microcontroller based systems

Boolean algebra
Introduction
In 1854 George Boole introduced a systematic treatment of logic and developed for this
purpose an algebraic system known as symbolic logic, or Boolean algebra.
Boolean algebra is a branch of mathematics and it can be used to describe the
manipulation and processing of binary information or used in the design ,maintenance
and analysis of logical circuits in digital computers
Boolean algebra
Boolean algebra uses Boolean variables and Boolean operators.
Boolean variables are binary variables or symbol used to represent a logical quantity.
Some examples of Boolean variables are A, B, C, a, b, c, X, Y, and Z.
Boolean operators are logical operators There are three basic logical operators: AND,
OR, and NOT.
A Boolean expression is a combination of Boolean variables and Boolean operators.

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There are many Boolean expressions that are logically equivalent to one another. There
are called equivalent expressions.
A Boolean function typically has one or more input variables and produces a result that
is based on these input values. The result can have a value of 0 or 1.

Truth Tables
A truth table is a useful visual tool for defining the input-output relationship of binary
variables in a Boolean function.
n
A function of n variables has 2 rows of possible input combinations, each row
specifying the value of the function for a different combination.
A truth table can be used to represent one or more functions.
Complement
It is the inverse of a variable and is indicated by a bar over the variable ex: A=>A‘
Literal:
It is a variable or the complement of a variable

The Duality Principle

Given a Boolean expression, the dual is formed by replacing AND with OR, OR with
AND, 0 with 1, 1 with 0.
The duality principle states that if two Boolean expressions are equal, then their duals are
also equal.
 Ex:ab+ab‘=a Dual is (a+b).(a+b‘)=a

Basic Postulates, Laws, and Theorems

Laws of Boolean Addition

x + 0 = x (Identity law in OR form)
x + 1 = 1 (Null law in OR form)
Laws of Boolean Multiplication
x  0 = 0 (Null law in AND form)
x  1 = x (Identity law in AND form)
Idempotent Laws
x+x=x xx=x
Involution Law
(x‘)‘ = x

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Laws of Complementarities
x + x‘ = 1 (Inverse law in OR form)
x  x‘ = 0 (Inverse law in AND form)

Commutative Laws
x+y=y+x xy=yx
Associative Laws
(x + y) + z = x + (y + z) = x + y + z
(x  y)  z = x  (y z) = x y z = xyz
Distributive Law
x  (y+z) = x  y +x or x(y+z) = xy + xz
z
x+(y.z)=(x+y)(x+z)
Absorption Laws
x  (x+y) = x x + xy = x

De Morgan’s Laws
(x+y)‘ = x‘ y‘
The complement of a sum of variables is equal to the product of the complements of the
individual variables
LHS RHS
X Y X' Y' X+Y (X+Y)' ( X'.Y')
0 0 1 1 0 1 1
0 1 1 0 1 0 0
1 0 0 1 1 0 0
1 1 0 0 1 0 0

(x  y)‘ = x‘ + y‘
The complement of a product of variables is equal to the sum of the complements of the
individual variables
LHS RHS
X Y X' Y' X.Y (X.Y)' ( X'+Y')
0 0 1 1 0 1 1
0 1 1 0 0 1 1
1 0 0 1 0 1 1
1 1 0 0 1 0 0

Representations of Boolean Functions

A Boolean function can be described or represented by any one of the following:

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A Boolean expression (one of many equivalent Boolean expressions)

A truth table
A circuit diagram (one of many equivalent circuit diagrams)

Logic gates
A gate is simply an electronic circuit which operates on one or more input signals to
perform a particular logical function
The basic gates are AND gate, OR gate & NOT gate
NAND,NOR,EX-OR & EX-NOR gates are the other most widely used gates

AND gate:

Logic symbol AND gate :

Function:
The AND gate is a logic element having two or more input terminals and only one output
terminal
Its output is at logical 1(high) only when all of its inputs are at logical 1(high)
If any one or more of the inputs are low then output of the gates will be low
Logical expression: Y=AB

Truth table
INPUTS OUTPUT
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

OR gate:

Logic symbol: OR gate

Function:

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The OR gate is a logic element having two or more input terminals and only one output
terminal
The output of an OR-gate is high(1) if any one or more of its inputs are high(1),the output
is low(0) only when all of its inputs are low
Logical expression: Y=A+B

Truth table
INPUTS OUTPUT
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

NOT gate (inverter)

Logic symbol:NOT gate

Function:
The NOT gate is having one input and one output terminal.
It is also called as an inverter as it inverts its input.
It performs the operation called inversion or complementation or negation
When a high is applied to an inverter, a low will appear on its output.
When a low is applied to its input, a high will appear on its output
Boolean expression: Y=A‘
Truth table:
INPUTS OUTPUT
A Y Y=A'
0 1 ON
1 0 OFF

NAND gate:

Logic symbol:NAND gate

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Function:
The NAND logical function is equivalent to AND followed by an inversion
The output of a NAND gate is low only when all of its inputs are high.othrewise its
output is high

Boolean expression: Y= (A.B)‘

Truth table:
INPUTS OUTPUT
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

NOR gate

Logic symbol: NOR gate

Function:
The NOR logical function is equivalent to OR followed by an inversion
The output of a NOR gate is high only when all of its inputs are low.othrewise its output
is low
Boolean expression: Y= (A+B)‘
Truth table:
INPUTS OUTPUT
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

EX-OR gate

Logic symbol:EX-OR gate

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Function:
The exclusive-OR gate is a combinational circuit with two or more inputs and one output
The output of the EX-OR is high if one and only one input is high
When both the inputs are equal, then the output is also low

Boolean expression: Y=A + B i.e., A‘B+AB‘

Truth table:
INPUTS OUTPUT
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

EX-NOR gate

Logic symbol:EX-NOR gate

Function:
The exclusive-NOR gate is a combinational circuit with two or more inputs and one output
The EX-NOR function is the complement of an EX-OR function, and hence its output is
high only when its inputs are equal

Boolean expression: Y= (A + B)‘ i.e., A‘B‘+AB

Truth table:
INPUTS OUTPUT
A B Y
0 0 1
0 1 0
1 0 0
1 1 1

UNIVERSAL GATE:

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Logic gates that can be used to realize any of the basic logical operations like AND,OR
NOT,NAND ,NOR,EX-OR & EX-NOR is called universal gate EX:NAND & NOR gates are
universal gates

NAND as universal gate

Desired NOT Gate NAND Construction

Desired AND Gate NAND Construction

Desired OR Gate NAND Construction

Desired NOR Gate NAND Construction

Desired XOR Gate NAND Construction

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Desired XNOR Gate NAND Construction

NOR as universal gate

Desired NOT Gate NOR Construction

Desired OR Gate NOR Construction

Desired AND Gate

NOR Construction

Desired NAND Gate NOR Construction

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Desired X-OR Gate NOR Construction

Desired XNOR Gate

NOR Construction

Logical functions:

Boolean expressions are represented in two forms based on their structure

Sum of products form(SOP)or disjunctive normal form
Product of sums form(POS)or conjunctive normal form

SOP function:
SOP is two or more AND functions ORed together.
A product of two or more variables or their complements is simply the AND function of
those variables
EX: 1.ABC‘+D‘EF‘+FGH+AF‘G
2. AB+BCD

POS function:
It is two or more OR functions ANDed together. It is also known as the dual of the
SOP EX: 1.(A+B+C‘)(D‘+E+F)
2.(A+B)(C+D+E‘)

Standard SOP:
It is also SOP but each product should contain all variables that are in the Boolean expression

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EX:ABC‘+A‘BC+AB‘C
In the above example it has got 3 product terms containing all the 3 variables (i.e.,A,B,C)

Conversion from SOP to standard SOP form

Multiply each of the product term by ‗1‘ which doesn‘t consist of all the variables so that the
value doesn‘t change (A.1=A)
Replace ‗1‘ by sum of complement and uncomplement of the variable which is missing in that
product term (A+A‘=1)
Repeat the above procedure until each product term consists of all the variables

Eg: write the following in the standard SOP form f(A,B,C)=AB’C+AB+A’

Step1:AB‘C+AB.1+A‘.1.1
Step2:AB‘C+AB(C+C‘)+A‘(B+B‘)(C+C‘)
Step3: AB‘C+ABC+ABC‘+A‘(BC+BC‘+B‘C+B‘C‘)
Step4: AB‘C+ABC+ABC‘+A‘BC+A‘BC‘+A‘B‘C+A‘B‘C‘
Standard SOP forms have 7 minterms or product terms

Assigning the value to each minterm

Complement of a variable is taken as ‗0‘ and uncomplement variable as‘1‘
Convert obtained binary form to its decimal equivalent

EX: f(A,B,C)=AB’C+ABC+ABC’+A’BC’+A’BC+A’B’C+A’B’C’
AB‘C=(101)2=(5)10
ABC=(111)2=(7)10
ABC‘=(110)2=(6)10
A‘BC‘=(010)2=(2)10
A‘BC=(011)2=(3)10
A‘B‘C=(001)2=(1)10
A‘B‘C‘=(000)2=(0)10
f(A,B,C)=sum of minterms(0,1,2,3,5,6,7)
Or
f(A,B,C)= (0,1,2,3,5,6,7)
where m indicates minterms(product terms)

Standard POS:

It is also POS but each sum function consists of all the variables that are in the Boolean
expression each such OR function/term is known as Max term
Eg:(A+B+C‘)(A‘+B+C)

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Conversion from POS to standard POS form

ADD each of the sum term by ‗0‘ which doesn‘t consist of all the variables so that the value
doesn‘t change (A+0 =A)
Replace ‗0‘ by product of complement and uncomplement of the variable which is missing in
that sum term (A.A‘=0)
Expand the function by using the theorem A+BC=(A+B)(A+C)
Repeat the above procedure until each sum term consists of all the variables

Eg: write the following in the standard POS form f(X,Y,Z))=(X’+Y’)(Y+Z)

Step1:(X‘+Y‘+0)(0+Y+Z)
Step2:(X‘+Y‘+ZZ‘)(XX‘+Y+Z)
Step3:(X‘+Y‘+Z) (X‘+Y‘+Z‘) (X+Y+Z) (X‘+Y+Z)
Standard POS term have 4 max terms or sum terms

Assigning the value to each minterm

Complement of a variable is taken as ‗1‘ and uncomplement variable as‘0‘
Convert obtained binary form to its decimal equivalent

f(X,Y,Z)=:(X’+Y’+Z) (X’+Y’+Z’) (X+Y+Z) (X’+Y+Z)

X‘+Y‘+Z =(110)2=6
X‘+Y‘+Z‘=(111)2=7
X+Y+Z=(000)2=0
X‘+Y+Z=(100)2=4
f(X,Y,Z)=product of max terms(0,4,6,7)
or
f(X,Y,Z)= (0,4,6,7)
where ‗M‘ indicates Max term(or sum terms)

Karnaugh map

Karnaugh map provides a systematic method for simplifying Boolean expression. The
simplified expression (SOP or POS) is called the minimum expression
K-map can be used to simplify Boolean expressions with two, three or four variables
The number of cells in a k-map is equal to the total number of possible input variable
combinations
n 2
For a 2 variable k-map the number of cells=2 =2 =4 .The variables are A&B

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Each cell value is called a minterm

n 3
For a 3 variable k-map the number of cells=2 =2 =8.The variables are A, B&C

n 4
For a 4 variable k-map the number of cells=2 =2 =16.The variables are A, B, C&D

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Cell adjacency
Cell adjacency is defined by a single variable change .cells that are differ by only one variable
are said to be adjacent so the order used in 00,01,11,10 to maintain “cell adjacency”

Wrap around adjacency

The cells in the left most columns are adjacent to the corresponding cells in the right most
columns this is called “wrap around adjacency”

Karnaugh map minimization of Boolean expressions

Minimization can be defined as the process that is used to obtain an expression containing the
fewest possible terms with the fewest possible variables

Minimization of SOP expressions

The following 3 steps

Mapping a standard SOP expression
Grouping the 1‘s
Summing the resultant product terms

Mapping a standard SOP expression

For each product term in the expression a 1 is placed in the cells corresponding to the value
of the product term
After mapping, the number of 1‘s in the k-map will be equal to the number of product terms
in the standard SOP expression
The remaining cells are filled with 0‘s

Grouping the 1’s

The grouping should be done so as to maximize the size of the groups and to minimize
the number of groups
The 1‘s are grouped to produce minimum product term
The groups must have either 1, 2, 4, 8&16 cells each being some power of 2
Sub-cubes
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m
A sub-cubes or a group is a set of exactly 2 adjacent cells containing 1‘s
Single cell
For m=0 the sub-cubes consists of a single cell. No variables are reduced it is an
isolated 1
Pair
m 1
For m=1 a sub-cube consists of 2 =2 =2 adjacent cells
Since m=1 grouping two adjacent cells containing 1‘s result in elimination of one
variables
Quad
m 2
For m=2 a sub-cube consists of 2 =2 =4 adjacent cells
Since m=2 grouping four adjacent cells containing 1‘s result in elimination of two
variables
Octet
m 3
For m=3 a sub-cube consists of 2 =2 =8 adjacent cells
Since m=3 grouping eight adjacent cells containing 1‘s result in elimination of
three variables
Overlapping groups
The same 1 in a k-map cell may be used in more than one group so as to help in forming largest
group possible

Rolling the map

The k map is visualized as if it is rolled so that the left side touches the right side and the top
edge touches the bottom edge

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Redundant group
A group whose 1‘s are all overlapped by other groups is called a redundant group

Summing the resultant product terms

The product terms corresponding to each of the groups are written
The variable that changes from the complemented to uncomplemented form or vice versa
is eliminated

Example: The SOP expression by using 4 variables is A’BCD+A’BCD’+ABCD+ABCD’

On grouping into a quad, the SOP expression will be BC

Because A changes from 0 to 1 and D changes from 1 to 0,So both variables A & D are
eliminated
Therefore A‘BCD+A‘BCD‘+ABCD+ABCD‘ can be simplified as BC
The final Boolean expression can be obtained by summing the resultant product terms
corresponding to each group this will be the minimum SOP expression

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Example problem
Minimize the following standard SOP expression using k-map
AB‘C+A‘BC+A‘B‘C+A‘B‘C‘+AB‘C‘ or f(A,B,C)= ∑m(0,1,3,4,5) or f(A,B,C)=(m0,m1,m4,m5)

Solution: Step1: Mapping a standard SOP expression

Step 2: Grouping the 1’s

Step 3: Summing the resultant product terms

A‘B‘C‘+A‘B‘C+AB‘C‘+AB‘C=>B‘
A‘B‘C+A‘BC=>A‘C
The term corresponding to these groups are B‘+A‘C

Don’t care condition

The don‘t care condition do not have any effect on the output
For these don‘t care terms ,the output may be assigned either a 0 or a 1
An ‗X‘ or ‗d‘ is placed in the cell for each don‘t care term
These terms need not be covered by the sub-cubes, but can be treated as 1‘s to make
grouping so as to simplify the resulting term

Example: Using k-map simplify the expression A‘BCD+A‘BCD‘+A‘BC‘D+A‘BC‘D‘+A‘B‘CD

Solution:

Without using don‘t care term we can have 2 pairs. The resultant expression will be
A‘BD+A‘BC‘=>here one variable is eliminated
Using the don‘t care term we can have one group i.e. quad .The resultant expression will be A‘B

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=>Here 2 variables are eliminated so it is advantageous to use don‘t care terms in simplifying
expression using k-map

Minimization of POS expressions

The following 3 steps
Mapping a standard POS expression
Grouping the 0‘s
Multiplying the resultant sum terms

Mapping a standard POS expression

Each 0 is placed in a cell of k-map corresponding to the value of a sum term
The number of 0‘s in the k=map is equal to the number of sum terms in the standard POS
expression
The remaining cells are filled with 1‘s

Grouping the 0’s

The 0‘s are grouped to produce minimum sum terms. The rules for grouping are the same
as for the grouping of 1‘s discussed earlier

Multiply the resultant sum terms

The sum terms corresponding to each of the groups are written
The variable that changes from the complemented to uncomplemented form or vice versa
is eliminated
The final Boolean expression can be obtained by multiplying the resultant sum terms
corresponding to each group this will be the minimum POS expression

Example problem
Use k-map to minimize the standard POS expression (X+Y‘+Z)(X+Y‘+Z‘)(X‘+Y‘+Z)(X‘+Y+Z)
or f(X,Y,Z)=∏M(3,4,5,6)OR f(X,Y,Z)=(M3+M4+M5+M6)

Solution:
Step 1: Mapping a standard POS expression

Binary values of the expression

(X+Y‘+Z)=010
(X+Y‘+Z‘)=011
(X‘+Y‘+Z)=110

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(X‘+Y+Z)=100

Step 2: Grouping 0’s

As done in the above k-map

Step 3: Multiplying the resulting sum terms

The terms corresponding to these groups are (X+Y‘) & (X‘+Z)
The final minimum POS expression can be written as the product of these 2 terms
corresponding to the 2 groups (X+Y‘). (X‘+Z)

Combinational logic
Introduction
When gates are connected together to produce a specified output for certain specified
combinations of input variable with no storage involved the resulting circuit is called
combinational logic. In combinational logic the output variable are at all times dependent on the
combination of input variables.

A combinational logic circuit consists of input variables, logic gates and output variables. The
logic gates accept signals from the input variables and generate output signals. This process
transforms binary data information from the given input data to the required output data.
Fig below shows the block diagram of a combinational circuit..

This accepts n input binary variables and generates output variables depending on the logical
combination of gates.
The main function of combinational circuits is
Truth table,
Boolean expression and
logic diagram

Design procedure
The design of combinational circuit starts from the online of the problem statement and ends in a
logic circuit diagram or a set of Boolean functions from which the logic diagram can be easily
obtained.

The design procedure

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The problem definition.

The determination of number of available input variables and required output variables.
Assigning letter symbols to input and output variables.
The derivation of truth table indicating the relationship b/w input and output variables.
Obtain simplified Boolean expression for each output.
Obtain the logic diagram.

Adders

Half adder
The function of a half adder is to add two binary digits producing a sum and a carry according to
binary addition rules.

Truth table
A B Sum carry
0 + 0 0 0
0 + 1 1 0
1 + 0 1 0
1 + 1 0 1
The block diagram truth table and the logic diagram of a half adder are given below.

As shown in the truth table if any one of the input is 1 but not both then the output on the S
(SUM) line will be 1.
If both inputs are 1, then carry line C will be 1 for all other states of input, there will be zero on
the carry line.
As per truth table

Logical expression
S=AB‘ + A‘B
S=A+B
C=AB
Hence sum output is generated by ex-or gate and carry output using AND gate.

Logic diagram of half adder

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Full adder
The arithmetic addition of 3 bits when adding two numbers you may have a carry from one
column to the next.

Eg:
ЀĀȀĀĀ ⸀Ā ᜀ The least significant column, 1+1=0, carry 1
ЀĀȀĀĀ ⸀Ā ᜀ The next column, 1+0+1(carry) therefore sum is 0, carry is 1
ЀĀȀĀĀ ⸀Ā ᜀ In the last column, we must again add 3 digits because of the carry 1+1+1=>S=1
C=1
Logical symbol

Truth table

Inputs Outputs
A B cin Sum carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Logical expression
Sum =A‘B‘C+A‘BC‘+AB‘C‘+ABC
=A‘(B‘C+BC‘)+A(B‘C‘+BC)
=A‘(B C)+A(B C)‘
Sum =A B C
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Carry =A‘BC+AB‘C+ABC‘+ABC
=C(A‘B+AB‘)+AB(C‘+C)
=C(A B)+AB(1)
Carry =C(A B)+AB

Logical diagram

Half adder implementation of full adder

To add binary numbers electronically we need a circuit that can handle 3 digits at a time, by
connecting two half adder and one OR gate we get a full adder a circuit that can add 3 digit at a
time.
FLIP FLOP
Flip flop is the basic memory element in a digital computer.
It is used to store one bit of information with a 0 or a 1.It is also called the binary or
toggle or latch.

Characteristics of flip flop

It is a bistable device. The circuit has only two stable states o & 1. It responds to inputs of
retains its state until some signal causes it to change state.
The flip flop has two outputs. One output is the complement of the other.

Types of flip flop

RS flip flop
D flip flop
JK flip flop
T flip flop
Master slave JK flip flop

RS flip flop (Reset-set flip flop)

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The logic symbol for SR flip flop is shown in fig

It has 3 inputs, S(set), R(reset), C (clock).

It has an output Q & a complement output Q1.The flip flop responds to a positive
transition from 0 to 1 of the input clock signal.

Working or operation of RS flips flop

When the clock signal changes from 0 to 1 the output is affected according to the values in inputs
S & R.
The following cases occur
If both S & R are 0 during the clock transition, the output does not change.
If S=1 & R=0 the output Q is set to 1
If S=0 & R=1 the output is cleared or reset to 0
If both S & R are 1, the output is unpredictable and may be either 0 or 1 depending on
internal timing delays that occur within the circuit. This is said to be the indeterminate
state of forbidden state.
The characteristic table or truth table
Outputs
Inputs Q(t+1)
S R X X' Mode Of Operation Effect On Output X
0 0 X X' Hold No Change
0 1 0 1 Reset Reset To 0
1 0 1 0 Set Set To 0
Prohibited Or
1 1 1 1 Forbidden Should Not Be Used
The two inputs are R & S have binary values 0 & 1.
Q(t) is the binary state of the Q output at a given time called the present state.
Q(t+1) is the binary state of the Q output after the occurrence of a clock transition and is
known as the next state.

D flip flop
The D flip flop is a flip flop with a sing le data input D and a clock input C.therfore it is
called data flip flop.

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The D flip flop is also known as the delays flip flop. The word ―delay‖ describes what
happens. To the data at input 0.The data at D input is delayed by one clock pulse before it
gets to the output Q.

The D flip flop can be formed from a clocked RS flip flop by adding an inventor or NOT gate.
The D input is connected to S input of RS flip flop directly
The D input is connected to R input of RS flip flop through the inventor.

The typical commercial D flip flop contain two extra inputs PRESET (P) AND CLEAR (CLR).

Asyn-Inputs Syn-Inputs Outputs

PRESET CLEAR CLK D X X' Mode Of Operation
0 1 X X 1 0 Asyn SET
1 0 X X 0 1 Asyn RESET
0 0 X X 1 1 Prohibited

1 1 _ 1 1 0 SET
1 1 _ 0 0 1 RESET

The preset and clear inputs are called asynchronous inputs as they act on the flip flop
independent of the clock.
The preset input is used to set the flip flop to 1.
The clear input is used to clear reset the flip flop to 0.
The bubble at these inputs that the active signal is 0.
The D input is called the synchronous input as it activates the flip flop only in
synchronism with the clock pulse.
Always the asynchronous inputs override the synchronous inputs.

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Working or operations of D flip flop

D Q(t+1)
0 0 CLEAR TO 0
1 1 SET TO 1

From the above table

The next state Q(t+1) is determined from the D input.
The relationship can be expressed by a characteristic equation. Q(t+1)=0
Every time that the clock signal goes through a transition from 0 to 1

Applications
D flip flop are widely used as temporary memory devices.
They are wired together to form shift registers and storage registers commonly used in digital
systems.

JK flip flop (JOCK KILBY)

It is a versatile and widely used type of flip flop

The J input is equivalent to the S input of SR flip flop and the K input is equivalent to the
R input of SR flip flop.
JK flip flop can be wired using RS flip flop

J K Q(t+1) mode of operation

0 0 Q(t) Hold
0 1 0 reset
1 0 1 set
1 1 Q(t)' Complement

Working or operations of JK flip flop

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When J & K inputs are both 0, the data inputs have no effect on the outputs. The flip flop is
said to be in the hold state.
when J=0 & K=1, the flip flop is reset or cleared to 0, then it said to be in the reset state.
When J=1 & K=0, the flip flop I s set to 1. Then it is said to be in the set state.
When both J & K are 1, if the state of the flip flop was 0, applying clock pulse causes it to
change to 1 & vice versa called toggling.

Toggling
It is defined as the change of output in a JK flips flop alternatively b/w 0 to 1 for every clock
transition

Racing
It can be defined as toggling (change of 0 to 1 and 1 to 0 alternatively) more than once during
one clock cycle in JK flip flop.

Applications
JK flip flop are used in many digital circuits especially its toggle feature is used in
counters.
JK flip flop are also used as frequency divider.

T flip flop
It is also known as toggle flip flop
Logical symbol

This type of flip flop can be obtained from a JK flip flop when input J & K are connected to
provide a single input designated by T.
So the T flip flop has only two conditions
When T=0 (J=0, K=0) a clock transition does not change the state of the flip flop.
When T=1(J=1, K=1) a clock transition complements the state of the flip flop.
Truth table
T Q(t+1)
0 Q(t) No change
1 Q(t)' Complement

Master slaves JK flip flop

In Master Slave JK flip flop consists of two flip flops.
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The first is the master, which responds to the positive edge of the clock. The second is the
slave, which responds to the negative edge of the clock. The output changes only during
the negative edge transition of the clock.

Logical symbol

This helps in avoiding the racing condition in JK flip flop where it can be triggered only once
within a clock cycle.
Since the output of the second flip flop follows that of the first JK flip flop, the names master and
slave are used.

Characteristics table
It specifies the next state when the inputs and the present state are known.
Excitation table
When we need to know the required transition from present state to next state and the input
conditions that caused the required transition, a table called excitation table.

Q(t) Q(t+1) S R
0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0

Q(t) Q(t+1) D
0 0 0
0 1 1
1 0 0
1 1 1

Q(t) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0

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Q(t) Q(t+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Application of flip flops

Flip flop have an important characteristic of storage capability so they are widely used in
registers.
It can be used to divide frequency of periodic waveform. They are said to be used as
frequency dividers.
They can also be used to count the number of clock pulses in digital counters.

Sequential circuit

A sequential circuit is an interconnection of flipflops and gates

It consists of a combinational circuit and a number of clocked flipflops

The combinational circuit block receives binary signals from external inputs and from the
outputs flipflops
The outputs of the combinational circuit go to external outputs and to inputs of flipflops
The gates in the combinational circuits determine the binary value to be sorted in the
flipflops after each clock transition
The output of flipflops in turn, are applied to the combinational circuit inputs and
determine the circuit‘s behavior
This process shows that the external outputs of a sequential circuit are functions of both
external inputs and the present state of the flipflops
The next state of flipflop is also a function of their present state and external inputs

State table
A sequential circuit is specified by a state table
A state table relates outputs and next states as a function of inputs and present states
The transition from present state to next state is activated by the present state to next state
is activated by the presence of a clock signal
The table consists of four sections
a. Present state-the states of flipflops at any given time t

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Input section gives a value of x for each possible present state

Next state section shows the states of flipflops one clock period later at time t+1
Output section gives the value of y for each present state and input condition

Derivation of state table

It consists of first listing all possible binary combinations of present state and inputs
The next state values are then determined from the logic diagram or from the input
equations
State diagram
The state diagram gives a pictorial view of state transitions and is the form suitable for human
interpretation of the circuit operation
Consider an example of sequential circuit fig.1

It has one input variable X and one output variable Y and Z clocked D flip-flops
The AND gates, OR gates and inverter form the combinational logic part of the
circuit
The relationship between the gates in the combinational circuit can be simplified by a set
of Boolean expression
The set of Boolean expressions called flip flop input equations
DA=AX+BX
A & B->output
o X->input
DB=A‘X
Y=AX‘+BX‘
State table
The state table consists of 4 sections
a. Present state
b. Input
c. Next state
d. Output
Present State Input Next State Output

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A B x A B Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0

State diagram
The information available in a state table can be represented graphically using a state diagram
A state is represented by a circle
The transition between states is indicated by directed lines connecting the circle
The directed lines are labeled with two binary number separated by a slash
The present state is labeled first and the number after the slash gives the output during the
present state
The state diagram for the sequential circuit is shown in fig

If the directed line from state 00 to state 01 is labeled 1/0,it means that when the sequential
circuit is in the present state 00 & the input is 1,the output is 0 & so on

The design procedure of a sequential circuit

The behavior of the circuit is first formulated in a state diagram

From the number of bits listed in a circle of state diagram, the number of flip flops required is
determined
The number of inputs for the circuit is specified
Letters are designated to all flip flops and input and output variables
The state table is obtained
The state table is then extended into an excitation table by including columns for each input of
each flip flop
By means of map simplification, a set of flip flop input equations for the circuit is obtained

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The combinational circuit so obtained together with the flip flops, constitutes the sequential
circuit
Flip flops are drawn and all their inputs and outputs are labeled
The combinational circuit is drawn from the Boolean expressions given by flip flop input
equations
The outputs of flip flops are connected to inputs in combinational circuit and outputs of the
combinational circuit are connected to flip flop inputs

Design of sequential circuit

First the circuit specifications are translated into a state diagram
The state diagram is then converted into a state table
The state table then provides the information for obtaining the logic circuit
diagram

Consider the example of a clocked sequential circuit with binary counter

When an external input X=1,The repeated binary states of 00,01,10 & 11.If X=0 the state of the
circuit remains unchanged, This circuits is called a 2 bit binary counter, The input X is called
external variable
The state diagram for binary counter

The states of the circuit follow the binary count as long as X=1, If X=0,the state of the circuit
remains unchanged

The state table for binary counter

Present State Input Next State

A B X A B
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 1 0
1 0 1 1 1
1 1 0 1 1

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1 1 1 0 0

Excitation table
If JK flip flop is used the columns are J & K inputs of each flip flop A & B.These are
denoted as JA, KA & JB,KB
The excitation table for JK flips flop
Q(t) Q(t+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

The excitation table for the binary counter follows from the excitation table of JK flip
flop

Present state input next state FLIP FLOP INPUTS

A B x A B JA KA JB KB
0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 X 1 X
0 1 0 0 1 0 X X 0
0 1 1 1 0 1 X X 1
1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X
1 1 0 1 1 X 0 X 0
1 1 1 0 0 X 1 X 1

In the circuit diagram shown in the fig.1

The simplified Boolean functions for the combinational circuit can be derived .the inputs are
variables A, B & X. the outputs are the variables JA, KA, JB & KB

The maps for the 4 flip flop inputs are shown below

JA=Bx KA=Bx

JB=X KB=X

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The simplified flip flop input equations are derived as JA=BX KA=BX JB=X KB=X

The logic diagram of 2 bit binary counter

Inputs J&K determine the next state of the counter when a clock signal occurs
If both J & K are equal to 0,a clock signal will have no effect
Answer the following questions:
Define computer organization.(1M,OCT/NOV 2012)
Define computer architecture.(1M,OCT/NOV 2011)
What is stored program concept? .(1M,OCT/NOV 2012)
Explain VON-Neuman architecture. .(5M,OCT/NOV 2011)
Explain Harvard architecture with a neat diagram. .(5M,OCT/NOV 2012)
Prove that(x+y)(x+z)=x+xz. .(1M,OCT/NOV 2011)
Given the function F=xy‘z+x‘y‘z+xyz.(3M,NOV/DEC 2010)
list the truth table of the function.
draw the logic diagram using only NAND gates.
Design half adder and full adder circuit?
Design a combinational logic circuit with 3 input x,y,z and the three output A,B,C.when
the binary input 0,1,2 or 3,the binary input is 4,5,6,or 7 the binary output is one less than
the input? .(3M,NOV/DEC 2010)
Explain the minimum SOP expresion using karnaugh map method using k-map simplify
f=∑(0,5,7,8,11,13,15) .(5M,OCT/NOV 2011)

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Design a Full –Adder circuit. .(5M,OCT/NOV 2011)

Explain JK flip flop. .(5M,OCT/NOV 2011)
Explain working of D flips flop, RS flipflop, JK flipflop and T flip flop
Explain S-R flip flop with logic diagram.(6M,OCT/NOV 2012)
Explain the steps involved in the design of sequential circuits.
Explain the design procedure of a 2 bit binary counter

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Chapter-2
Integrated circuits and digital functions
Using advanced techniques a manufacturer can produce miniature circuits of the surface
of a small piece of semiconductor material called a chip. Such a circuit is called an
Integrated circuit(IC).
There are two basic techniques for manufacturing ICs are
Bipolar technique.
Metal oxide semiconductors (MOS) technique
A digital IC family is a group of compatible devices with the same logic leves and supply
voltages

Scale of integration or Classification of integrated circuits

The number of gats that can be put in a single chip a) Small
scale integration (SSI)
It contains several independent gates in a single package. The inputs and outputs of the
gates are connected directly to the pins in the package. The number of gates is usually less than
10 and is limited by the number of the pins available in the IC.
b) Medium scale integration (MSI)
It has approximately 10 to 200 gates in a single package. They perform specific
elementary digital functions such as decoders, adders and registers.
c) Large scale Integration (LSI)
It contains b/w 200 and a few thousand gates in a single package. They include digital
systems such as processors, memory chips and programmable modules.
d) Very large scale integration (VSIL)
It contains thousands of gates within a single package. They include large memory arrays
and complex microcomputers chips.
e) Super large scale integration (SLSI)
Between 10,000 and 1, 00,000 transistors within a single package and perform
computational operations such as microprocessor chips, micro-contollers, basic PICs and
calculator
f) Ultra large scale integration (ULSI)
More than 1 million transistor and it is used in computers CPUs, GPUs, Video
processors, micro-controllers

Logic families
The IC technology usually depends on the following factors:-
Speed
Power description
Noise immunity
Input/output interface compatibility

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Cost.
Compatibility
It means that we can connect the output of one device to the input of another.
Interfacing
It is defined as the design of the interconnections between circuits that shift the voltage levels
and current levels to make the compatible.

Digital integrated circuits

The advantages if ICs being used in digital system are many
Small size
High reliability
Low cost
Low power consumption

There are two broad categories of digital ICs. They are:-

Fixed function logic.
Programmable logic.
Fixed function logic: - The logic functions of the IC are set by the manufacture and cannot be
altered.
Programmable logic: - The logic functions of the IC can be altered later.

The two basic techniques for manufacturing Ics are

Bipolar technique.
Metal oxide semiconductor (MOS) technique.

Classifications of digital IC families

Digital IC families are broadly classified as
Bipolar families
MOS families

The basic families in the bipolar category are

Resistor transistor logic.
Diode transistor logic.
Transistor transistor logic.
Emitter coupled logic

The basic families in the MOS category are

P channel MOSFET (PMOS)
N channel MOSFET (NMOS)
Complementary MOSFET (CMOS)

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Characteristics of IC family gates

There are five basic characteristics are
Power dissipation
Propagation delay
Fan in
Fan out
Noise margin
Power dissipation
This is the power consumed by the gate
It is the product of dc voltage and current
Power dissipation of a circuit or system defines battery life the greater the power
dissipation the shorter the battery life
Power dissipation is proportional to the heat generated by the chip or system excessive
heat dissipation may increase operating temperature cause gates to generate improper
output values
Propagation delay
The term propagation delay refers to the average time it takes the input signal to propagate to
the output

Fan in is the number of inputs a gate has like a 2 input AND gate has fan in of two ,a 3 input
NAND gate has fan in of three and so on

The number of gates that each gate can drive while providing voltage levels in the
guarantied range is called the standard load or fan out
The fan out really depends on the amount of electric current a gate can source or sink
while driving other gates
Noise margin
Noise margin refers to the maximum noise voltage that can be added to the generated signal
in a digital circuit before an undesirable change is caused in the circuit output

Transistor transistor logic (TTL)

In this technology the diodes were replaced by transistors to improve the circuits
operations and the logic family was called TTL.
It is a class of digital circuits build from bipolar function transistors and resistors. It is
called TTL
Because both the logic gating function AND and the amplifying function are
performed by transistors

Applications

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Computers, industrial control, test equipments and instrumentation, consumer electronics,

synthesizers etc..
TTL ICs are examples of SSI to LSI.

There are several variation of TTL family.

Standard TTL
High speed TTL
Low power TTL
Schottky TTL
Low power schottky TTL
Advanced schottky TTL
Low voltage TTL

Emitter coupled logic (ECL):-

It is a logic family in which current is steered through bipolar transistors to compute
logical function. It is sometimes called current mode logic.

Characteristics
ECL is that the transistors are always in the active region.
It can be change state very rapidly.
It operates at very high speed.
The propagation time can be less than a nanosecond.
The large current requirement is approximately constant and does not depend
significantly on the state of the circuit.

Disadvantages
The circuit require a lot of power.
Most of this power is wasted as heat.

Usage
It is used in high speed application.
Older high and mainframe computers used ECL
It is used in systems such as supercomputers and signal processors where high speed is
essential.

Metal oxide semiconductors (MOS)

The metal oxide semiconductor is a unipolar transistor that depends on the flow of only
one type of carrier, which may be electrons (n channel) or hole (p channel).

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The triple compound ―metal oxide semiconductor‖ is a reference to the nature of the
physical structure of the field effect transistors.

CMOS complementary MOS

CMOS is sometimes explained as complementary symmetry metal oxide semiconductors.
The word ―complementary symmetry‖ refers to the fact that the typical digital design
style with CMOS user complementary and symmetrical pairs of electronic devices p type
and N type MOSFETs for logic functions.

Characteristics
They have a very high input resistance.
They are compatible with one another.
They possess high noise immunity.
They have low static power supply drain.
CMOS allows a high density of logic functions on a chip.
Heat dissipation is low.
It is simple.
Sophisticate protection circuitry.

Usage
It is used in chips such as microprocessors, micro controllers, static RAM and other
digital logic circuits.
CMOS technology is also used for a wide variety of analog circuits such as image sensor,
data converts and highly integrated transrecievers for many types of communication.
Current IBM mainframes use CMOS.
They are also used in battery powered equipment such as pocket calculators, digital wrist
watches and portable computers.

Advantages
These devices dissipate less power.
Their operation speed is high.
Manufacturing costs are low.
Both low to high and high to low output transitions are flat.
Simpler processing techniques during fabrications
More economical operation.
High packaging density of circuit

Disadvantages
Power consumption increases rapidly with clock speed.
CMOS devices have higher noise.
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Comparison of logic families

TTL ECL CMOS
Uses NAND gate User NOR gate Uses NOT gate
Consumes more power at rest Consumes more power than Consumes lesser power at
the two rest
Power consumption Power consumption is the Power consumption does not
increased rapidly with clock highest increases rapidly with clock
speed speed
Less sensitive to damage More sensitive to damage
from electrostatic discharge from electrostatic discharge
Provides more heat power Provides most heat power Provides less heat low power
dissipation is more dissipation is most dissipation

Register
A register is a group of flip flop with each flip flop is capable of storing one bit of
information.
An ‗n‘ bit register has a group of ‗n‘ flip flops and is capable of storing any binary
information of ‗n‘ bits
The flip flops hold the binary information and the gates control when and how new
information is transferred into the register.

The clock input is common to all the 4 D-flipflop.it triggers all flip flops on the rising edge of
each clock pulse, and the binary data available at the four D inputs are latched into the register

Figure shows a 4 bit register constructed with four D-flip flop

When clear input =0,all flip flops are reset asynchronously i.e,which clears the register
content to all 0‘s
Clear input =1 for normal operation

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Register load:
The transfer of new information into a register is called loading a register

Register with parallel load

A 4 bit register with a load control input that is directed through gates and into the D
input is shown in fig

The clock input is common for all flip flop

The load input determines whether the next pulse will accept new information or leave
the information in the register
When the load input=1, the data in the 4 inputs are transferred into the register with the
next positive transition of a clock pulse
When the load input =0, the data inputs are inhibited and the D inputs of the flip flops are
connected to their outputs
The feedback connection from output to input is necessary because the D flip flop does
not have a ―no change ―condition.

Shift register
A register capable of shifting its binary information in one or both directions is called a
shift register
A shift register consists of a series of flip flops cascaded together, with the output of one
flip flop connected to the input of the next flipflop.all flip flops receives common clock
pulses that initiate the shift from one stage to the next

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Shift register can be of two types depending upon the direction of shift
Unidirectional
Bidirectional

Unidirectional shift register

A register is capable of shifting in one direction only is called a unidirectional shift register

Bidirectional shift register

A register than can shift in both directions is called a directional shift register.

Characteristic features of shift register

They provide necessary input and output terminals for parallel data transfer
An input for clock pulses to synchronize all operations
A shift right operation and a serial input line associated with the shift right
A shift left operation and a serial input line associated with the shift left
A parallel load operation and n input lines associated with the parallel transfer
N parallel output lines
A control state that leaves the information in the register unchanged even though clock
pulses are applied continuously.

Bidirectional shift register with parallel load

A 4 bit bidirectional shift register with parallel load is shown in fig

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The selection lines S1 and S0 control the mode of operation of the register according to the
function table

A 3 bit bidirectional shift register with parallel load

When mode control S1S0=00,data input 0 of each multiplexer is selected so there is no

change in the state
When S1S0=01,a shift right operation shifts the contents of the register in the down
direction
When S1S0=10,a shift left operation shifts the contents of the register in the upward
direction
When S1S0=11,the binary information from each inputs D0 through D3 is transferred
into the corresponding flipflop,resulting parallel load operation.

Binary counter
Counter
A counter is a device which stores the number of times a particular event or process
has occurred.

Usage
Counters are found in almost all equipment containing digital logic.

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They are used for counting the number of occurrences of an event.

They are useful for generation timing signals to control the sequence of operations
in digital computers.

Binary counter
A counter that follows the binary number sequence is called a binary counter.
An ‗n‘ bit binary counter is a register of n flip-flops and associated gates that follows a
n
sequence of states according to the binary count of n bits, from 0 to 2 -1
A counter circuit will usually employ flip-flops with complementing capabilities .both T
and JK flip flops have this property.

Synchronous binary counter

JK flip flops have complementing capabilities. So that is used in the 4 bit synchronous
binary counter.
Clock pulses are applied to the input of all flip-flops
Common clock trigger all flip-flops simultaneously
T=0 or J=K=0(flip flop does not change state)
T=1 or J=K=1(flip-flop complements)

Design of 4 bit Synchronous binary counter

JK flip flop truth table
J K Qt+1 State
0 0 Qt No change
0 1 0 Clear
1 0 1 Set
1 1 Qt` Complement

JK flip flop excitation table

Truth table of 4 bit binary counter

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The flip-flop in the least significant position is complemented in every pulse

A flip-flop in any other position is complemented when all the bits in the lower
significant positions are equal
If J and K = 0 (state of the counter does not change), however if it is =1 counter is
enabled.

Binary counter with parallel load

Counters employed in Binary Counter with Parallel Load digital systems often require a
parallel load capability for transferring an initial binary number into the counter prior to
the counter operation
When equal to 1, the input load control disables the count operation. Count operation and
causes a transfer of data from the four data inputs into the four flip-flops
If both inputs are zero, clock pulses do not change the state of the register.

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Increment Or
Clock Clear Load Count Operation
↑ 0 0 0 No Change
↑ 0 0 1 Increment Count By 1
↑ 0 1 x Load Inputs I0 Through I3
↑ 1 x x Clear Outputs To 0

The four control inputs – Clear, Clock, Load, Count determine the next state
Clear input is asynchronous and when equal to 0, causes the counter to be cleared.
X symbolize don‘t care conditions for the other inputs.
With the Load and Count inputs both 0, the output do not change.

Decoder
A decoder is a combination circuit that converts binary information from the ‗n‘
n
coded inputs to a maximum of 2 unique outputs.
The decoder has ‗n‘ inputs and ‗m‘ outputs and is also referred to as n x m decoder.

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2 to 4 line decoder
Logical diagram

2 to 4 line decoder

When E=1 the decoder is enabled.

E=0 the decoder is disabled.
When E=0 and the inputs A and B are anything that can be represented by X (don‘t care
condition). All the outputs are equal to 0
When E=1 i/p X=0 Y=0 the F0 output is high (i.e. selected)
When E=1 i/p X=0 Y=1 the F1 output is high remaining outputs are held low
When E=1 i/p X=1 Y=0 the F2 output is high
When E=1 and i/p X=1Y=1 then F3 output is high remaining output are held low

3 to 8 decoder
Logical diagram

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Truth table

INPUTS OUTPUTS
X2 X1 X0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

These are decoded into 8 outputs, each output representing one of the combinations of
the three binary input variables.
The 3 inverter provide the complement of the inputs.
Each of the eight AND gates generates one of the binary combination.
Enable input is use to control the operation of the circuit.

NAND gate decoder and Truth table of 2 to 4 line NAND gate decoder

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The circuit operates with complemented outputs and enables input E is also complemented
to match the outputs of the NAND gate decoder

In general the following points about decoder can be noted.

Any decoder may operate with complemented or uncomplemented outputs.
The enable input may be activated with a 0 or with a1.
Some decoders have two or more enable inputs that must satisfy a given logic condition
in order to enable the circuit.

Decoder expansion
Decoder of large size may be required while there are only small size decoders are
available.
In order to obtain the required size decoder two or more decoders can be combined.
A 3x8 decoder constructed using 2x4 decoders.

When A2=0 upper decoder is enabled, while the lower is disabled. Thus, the outputs
of the upper decoder correspond to minterms D0 through D3.
When A2=0 upper decoder is disabled, while the lower is enabled. Thus, the outputs
of the upper decoder correspond to minterms D4 through D7

Encoder
An encoder performs the inverse operation of a decoder.
n
It has 2 inputs and n output lines.

Ex octal to binary encoder. The encoder can be implemented with OR gates,

whose inputs are determined directly from the truth table.

INPUTS OUTPUTS

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D0 D1 D2 D3 D4 D5 D6 D7 A2 A3 A1
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

A0=D1+D3+D5+D7----1
A1=D2+D4+D6+D7----2
A2=D4+D5+D6+D7----3
Using the equation 1, 2 and 3
We can construct the encoder using three OR gate with 8 datelines.

Priority encoder output the highest order input first.

For ex:- if input lines D2,D3 and D5 are applied simultaneously the output code would
be for the input D5(101) as this has the highest order out of the 3 inputs. Once input D5
had been removed the next highest output code would be for input. D3(001) and so on.

Multiplexer
A multiplexer is a combinational circuit that receives binary information from one of 2n
input data lines and directs it to a single output line.
n n
A 2 to 1 multiplexer has 2 input data lines and n input selection lines whose bit
combinations determine which input data are selected for the output.
The multiplexer is often abbreviated as MUX or MPX. It is also called as a data selector.
Eg: 4 to 1 line multiplex..

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The 4 to 1 line multiplexer has 6 i/p and 1 output.

A truth table describing the circuit needs 64 rows since six i/p variables can have
26 binary combinations.
The functional table demonstrates the relationship b/w the four data input and the
single output as a function of the selection inputs S1 and S0.

Select output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Quadruple 2 to 1 line multiplexer

Two or more multiplexer are enclosed within a single integrated circuit package.
The selection and enable inputs are common to all multiplexer.
The block diagram of a quadruple 2 To 1 line multiplex.

Output Y0 can be selected to come from either input A0 and B0

Output Y1 can be selected to come from either input A1 or B1 and so on.
One input selection line S selects one of the lines in each of the four multiplexers

Function table

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E S Y
0 X ALL 0'S
1 0 A
1 1 B
When E=0 the outputs have all 0‘s whether s is 0 or 1.
When E=1 the unit is enabled.
If S=0 data present at A will be selected
o If S=1 data present at B will be selected

Application of multiplexer
Data routing
Parallel to serial conversion
Logic function generation
Call routing
Memory unit
The computer memory is defined as one or more sets of chips that store data/program
instructions either temporarily or permanently.

The two major types of memories are used in computer systems.

Random access memory (RAM)
Read only memory (ROM)
Based on access time these semiconductor memories are classified into
Random access memories (RAM)
Sequential access memories (SAM)
Random access memories constitute
Read only memories (ROM)
Read mostly memories (RMM)
Read write memories (RWM)
Sequential access memories constitute
Charge coupled devices (CCD)
Bubble memories
Memories with shift registers

ROMs are of four types

marked programmable ROM‘s
User programmed ROM‘S
Erasable and programmable (EPROM)
Electrically erasable (EEPROM)

RAMs are of two types

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Static RAM-memory cells are flip flops.

Dynamic RAM-memory cells have capacitors which must be refreshed, read
and written periodically to avoid loss of memory.

RAM
RAM is the central storage unit in a computer system.
RAM is said to be volatile. Since its contents are accessible only as long as the computer
is on.
The content of RAM is cleared once the computer is turned off.

Steps to be followed to transfer a new word to be stored into memory are-

The binary address of the desired word is applied into the address lines.
The data bits that must be stored in memory are applied into the data input lines.
The write input is activated.

Steps that must be taken from the purpose of transferring a stored word out of memory are as
follows:
Apply the binary address of the desired word into the address lines.
Activate the read input.

ROM
ROM is special type of memory which can only be read and contents of which are not
lost even when the computer is switched off.
ROM also stores an initial program called the ‗Bootstrap load‘ whose function is to start
the computer system operating, once the power is turned on.
ROM can be manufacturer programmed or user programmed.
Manufacturer programmed-ROMs have data burnt into the circuitry. User programmed
ROMs can have the user load and then store read only programs.

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ROM does not need a read control line since any time. The output lines automatically
provide the n bits of the word selected by the address value.
ROM is internally constructed by using with decoder and a set of OR gates.

Applications
It is widely used in the design of digital systems.
It is also employed in the design of control units for digital computers.
It is used as a memory unit to store fixed programs that are not to be altered and for tables of
constants that are not subject to change.
Types of ROM
Mark programmed ROM
Mark programming is done during the last fabrication process of the unit.
Classic mark programmed ROM chips are integrated circuits that physically encode the
data to be stored and thus it is impossible to change their contents after fabrication.

Programmable ROM (PROM)

They contain all the fuses intact, giving all 1‘s in the bits of the stored words.
The fuses are blown by application of current pulses through the output terminals for
each address.
It is available to achieve the desired relationship b/w input address and stored words.

Erasable PROM (EPROM)

When the EPROM is placed under a special ultraviolet light for a given period of time the
radiation discharges the internal gates that serve as fuses.
After erasing EPROM returns to its initial state and can be programmed to a new set of
words.
EPROM chips exceeds 1000 cycles of erasing and reprogramming.

Electrically erasable PROM (EEPROM)

Flash memory is a form of EEPROM in which a block of bytes can be erased in a very
short duration.
It allows it entire contents to be electrically erased and then rewritten electrically so that
they need not be removed from the computer (or camera,mp3 player etc)..
Writing or flashing an EPROM is much slower (milliseconds per unit).

Applications
It is used in storing current time and date in a machine.
It is also used for storing port status.
They are used for storing messages in a mobile phone.
They are used for storing photographs in a digital camera.
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Electrically alterable read only memory (EAROM)

It is a type of EEPROM that can be modified one bit at a time.
Writing is a very slow process and again requires higher voltage.
It may be used as non volatile storage for critical system setup information.
EAROM has been supplanted by CMOS RAM supplied by mains power and backup with
a lithium battery.

Application
ROM is used in embedded systems. This governs everything from industrial robots to home
appliances and consumer electronics (MP3 player, set-top boxes etc.) all of which are designed
for specific functions.
Answer the following questions:
What is a multipler? Explain with a neat circuit diagram a 4-to-1 multiplexer .
(3M,NOV/DEC 2010)
Explain ROM with a neat block diagram and write a note on different types of ROM.
(3M,NOV/DEC 2010)
What is shift register?(1M,OCT/NOV 2011)
What is flash memory? (1M,OCT/NOV 2011) (1M,OCT/NOV 2012)
Compare TTL,ECL & CMOS logic families. (5M,OCT/NOV 2011) (6M,OCT/NOV 2012)
Explain synchronous binary counters.
Explain 4 bit shift register. (7M,OCT/NOV 2011)
Explain 4 to 1 line multiplexer. (8M,OCT/NOV 2011)
What is decoder? (1M,OCT/NOV 2012)
Explain 3 to 8 line decoder.
What is encoder? Explain the octal to binary encoder, with truth table, logical expressions and
circuit diagram.
Explain SSI,MSI,LSI,VSLI(5M,OCT/NOV 2012)
Compare RAM and ROM. (4M,OCT/NOV 2012)
Explain 4 bit register with parallel load with a neat diagram. (7M,OCT/NOV 2012)
Explain magnetic disk memory. (4M,OCT/NOV 2012)

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Chapter-3

Number system
Number a quantity or value expressed by a word or a symbol is called Number
Number system a set of symbols & rules for representation of numbers is called Number
System
They are classified into two types they are
Positional number system
Non positional number system

a. Positional number system

It is use certain well defined symbol is called ‗digit‖

The value of the digit depends on the position in which they appear in the number
The value of the number depends on 3 factors they are
The digits
The position of digit in the number
o The base of the number
Eg: decimal,binary,octal & hexa decimal number system
Eg : 256 is a number
2 5 6 are digits
H T O
The 2 carries the most weight of the 3 number and referred as ―most significant
digit (MSD)‖
The 6 carries the least weight of three number & is called ―least significant digit (LSD)‖

b. Non positional number system

In this type each symbol represents a definite value irrespective of the position in which they
appear

Eg: Roman number system.

Base or radix

The total number of different digits or symbols available in the number system is called ―base
or radix‖

Positional number system

The positional number system are classified into four types they are

1. Decimal number system

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Binary number system

Octal number system
Hexa decimal number system

Decimal number system

It is also called as Hindu Arabic numerals

The symbols used in this system are 0,1,2,3,4,5,6,7,8,9
The radix or base of this number system is 10
Weight structure of this number system is

4 3 2 1 0 -1 -2 -3
…..10 10 10 10 10 . 10 10 10 ……

Binary number system

The symbols used in this system are 0,1 0 & 1 are called ―bits‖
Bit is an abbreviation for a binary digit
The radix or base of this number system is 2
Weight structure of this number system is
4 3 2 1 0 -1 -2 -3
…..2 2 2 2 2 . 2 2 2 ……….
The weights increases from right to left by a power of two for each bit
The left most bit is the MSB & right most bit is the LSB

1 1 1 1 0 1 1 1 1

MSB LSB

Octal number system

The symbols used in this system are 0,1,2,3,4,5,6,7

The radix or base of this number system is 8
Weight structure of this number system is
3 2 1 0 -1 -2 -3
……..8 8 8 8 . 8 8 8 …………
Hexa decimal number system

The symbols used in this system are 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

The radix or base of this number system is 16
Weight structure of this number system is
3 2 1 0 -1 -2 -3
…..16 16 16 16 . 16 16 16 ……..

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Conversions

Binary number system

Decimal to binary conversion

Binary to decimal conversion

Octal number system

Decimal to octal conversion

Octal to decimal conversion
Octal to binary conversion
Binary to octal conversion

Hexa decimal number system

Decimal to Hexa decimal conversion

Hexa decimal to decimal conversion
Hexa decimal to binary conversion
Binary to Hexa decimal conversion

Binary number system

Decimal to binary conversion

In this conversion the given decimal number is repeatedly divide by 2 for integer part until the
quotient is 0 and for fraction successively multiplying by 2

Eg: Convert 28.3125(10)---- (?)2

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Binary to decimal conversion

Determine the positional value of each digit

Multiply the obtained value by the digit in the corresponding position
Sum the products calculate in the previous step to get the decimal number

26 25 24 23 22 21 20 2-1 2-2 2-3 2-4

64 32 16 8 4 2 1 0.5 0.25 0.125 0.0625


Eg:1110.011(2)-- (?)10
3 2 1 0 -1 -2 -3
=1x2 +1x2 +1x2 +0*2 +0x2 +1x2 +1x2
=1x8+1x4+1x2+0x1+0x0.5+1x0.25+1x0.125
=8+4+2+0+0+0.25+0.125
1110.011(2)=14.375(10)

Octal number system

Decimal to octal conversion

In this conversion the given decimal number is repeatedly divide by 8 for integer part until the
quotient is 0 and for fraction successively multiplying by 8

Eg: Convert 549.1325(10) ----- (?)(8)

Octal to decimal conversion

Determine the positional value of each digit

Multiply the obtained value by the digit in the corresponding position
Sum the products calculate in the previous step to get the decimal number

84 83 82 81 80 8-1 8-2 8-3

4096 512 64 8 1 0.125 0.0156 0.00195

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
Eg: Convert 763.375(8) ---------- (?)(10)
2 1 0 -1 -2 -3
7x8 +6x8 +3x8 +3x8 +7x8 +5x8
7x64+6x8+3x1+3x0125+7x0.0156+5x0.00195

448+48+3+0.375+0.1092+0.00975

763.375(8) = 499.49395(10)

Octal to binary conversion

Convert each digit of the octal number to a 3 digit binary number

Combine all the resulting binary groups into a single binary number

Octal Binary
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111

Eg: 4632.51(8) -------- (?)2
4 6 3 2 . 5 1
100 110 011 010 101 001
4632.51(8) =100110011010101001(2)

Binary to octal conversion

The bits of the binary numbers are grouped into groups of 3 bits starting from LSB for
integer and from MSB for fraction
If the last group contains less than 3 bits then place 0 for those place
Convert each group into a octal equivalent digit

Eg:01111.1101011(2)->(?)8

1.

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2.

3. 1 7 . 6 5 4

4.17.654(8)

01111.1101011(2) = 17.654(8)

Hexa decimal number system

Decimal to Hexa decimal conversion

In this conversion the given decimal number is repeatedly divide by 16 for integer part until the
quotient is 0 and for fraction successively multiplying by 16


Eg:Convert 512.625(16)----- (?)10

Hexa decimal to decimal conversion

1. Determine the positional value of each digit

2. Multiply the obtained value by the digit in the corresponding position
3. Sum the products calculate in the previous step to get the decimal number

164 163 162 161 160 16-1 16-2 16-3

65536 4096 256 16 1 0.0625 0.0039 0.00024

Eg: 36F.ABC(16)------ (?)10
2 1 0 -1 -2 -3
3x16 +6x16 +Fx16 +Ax16 +Bx16 +Cx16
3x256+6x16+15x1+10x0.0625+11x0.0039+12x0.00024
879.67078(10)
36F.ABC(16)= 879.67078(10)

Hexa decimal to binary conversion

1. convert each digit of the Hexa decimal number to a 4 digit binary number

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2. combine all the resulting binary groups into a single binary number

Decimal Hex binary

0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
8 8 1000
9 9 1001
10 A 1010
11 B 1011
12 C 1100
13 D 1101
14 E 1110
15 F 1111

Eg: 10A4.FACE (16) ------ (?)2
1 0 A 4 . F A C E
0001 0000 1010 0100 1111 1010 1100 1110
0001000010100100.1111101011001110(2)
10A4.FACE (16) = 0001000010100100.1111101011001110(2)

Binary to Hexa decimal conversion

The bits of the binary numbers are grouped into groups of 4bits starting from LSB for
integer and from MSB for fraction
If the last group contains less than 4 bits then place 0 for those place
Convert each group into a Hexa decimal equivalent digit

Eg: 11100.01(2)=(?)16

1 C . 4
11100.01(2) = 1 C .4(16)

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Complements

There are two basic types of complements for any number systems they are

True complement
Radix minus one complement

True complement

This is formed by subtracting each digit of the number from the radix minus one of the
number system and then adding 1 to the result of subtraction

Eg: Decimal system->10‘s complement

Binary system->2‘s complement
Radix minus one complement

This is formed by subtracting each digit of the number from the radix minus one of the
number system

Eg: Decimal system->9‘s complement

Binary system->1‘s complement
Complements of binary numbers

They are

1‘s complement
2‘s complement

1’s complement

The 1‘s complement of a binary number is obtained by changing each 0 to 1 and 1 to 0

Eg:101011

010100->1‘s complement

2’s complement

The 2‘s complement of a binary number is formed by taking the 1‘s complement of
the number and then adding 1 to LSB position
Eg: 101011
010100->1‘s complement
1
010101->2‘s complement

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Signed binary numbers

Numbers that contain a sign bit followed by magnitude bits are called ―sign
magnitude number‖
In this MSB always represents the sign whether +ve or –ve
The remaining bits represent magnitude which is the value of the number
The negative numbers are represented as sign magnitude,1‘s complement &
2‘s complement

Bit->0,1

Nibble->4 bits

Byte->8 bits

Word-.2bytes->16 bits

Floating point numbers

Floating point numbers consists of mantissa, exponent and a sign

The Floating point numbers are represented as ‗any number y which is represented as ‗a
p
xr ‘
Where a-

>mantissa r-.radix

p->exponent

Floating point numbers can be expressed in three formats

Single precision (32 bits)

Double precision (64 bits)

Extended precision (80 bits)

S Exponent Mantissa
Normalization

―The number succeeding the floating point is a non-zero number is called normalization‖
9 7
 Eg: 0.0047x10 is represented as 0.49x10
-7 -9
0.00236x10 is the normalized form is 0.236x10
Binary arithmetic

Binary arithmetic consists of the operations such as addition, subtraction, multiplication, division

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Binary addition

The rules of binary addition are

0+0=0

0+1=1

1+0=1

1+1=0 with a carry 1

1+1+1 with a carry 1

Addition of unsigned number

Addition of bits according to the rules of binary addition

Addition of signed numbers

There are 4 cases

Both positive number

Larger positive and smaller negative number
Smaller positive and larger negative number
Both negative numbers

Both positive numbers

Convert decimal to binary

Then add according to the rules

Eg: 128 64 32 16 8 4 2 1
64 0 1 0 0 0 0 0 0
+32 0 0 1 0 0 0 0 0
+96 0 1 1 0 0 0 0 0

Larger positive and smaller negative number

Convert decimal to binary

Then take 2‘s complement for smaller negative number
Add according to the rules
Discard carry bit and represent sign bit

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Eg: Add -16 from 32

step-1 128 64 32 16 8 4 2 1
+32 0 0 1 0 0 0 0 0
-16 0 0 0 1 0 0 0 0
+16

step-2 0 0 0 1 0 0 0 0
1's
1 1 1 0 1 1 1 1 complement
1
2's
1 1 1 1 0 0 0 0 complement

step-3 0 0 1 0 0 0 0 0
1 1 1 1 0 0 0 0
1 0 0 0 1 0 0 0 0

step-4 Ingnored carry bit

Smaller positive and larger negative number

Convert decimal to binary

Then take 2‘s complement for larger negative number
Add according to the rules
Represent sign bit Then take 2‘s complement for obtain the result

Eg: Add -32 from 20

step-1 128 64 32 16 8 4 2 1
20 0 0 0 1 0 1 0 0
-32 0 0 1 0 0 0 0 0
-12

step-2 0 0 1 0 0 0 0 0 =>32
1 1 0 1 1 1 1 1 1's complement
1
1 1 1 0 0 0 0 0 2's complement

step-3 0 0 0 1 0 1 0 0 =>20
1 1 1 0 0 0 0 0 =>2’s com of 32
1 1 1 1 0 1 0 0
sign
step 4 1 1 1 1 0 1 0 0

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0 0 0 0 1 0 1 1 1's complement
1
0 0 0 0 1 1 0 0 2's complement

Both negative numbers

Convert decimal to binary

Then take 2‘s complement for both negative number
Add according to the rules
Discard carry bit and represent sign bit
Then take 2‘s complement for obtain the result

Eg: Add -16 from -32

step-1 128 64 32 16 8 4 2 1
-32 0 0 1 0 0 0 0 0
-16 0 0 0 1 0 0 0 0
-48 Take 2's complement for 32
step-2 0 0 1 0 0 0 0 0
1 1 0 1 1 1 1 1 1's complement
1
1 1 1 0 0 0 0 0 2's complement

Take 2's complement for 16

0 0 0 1 0 0 0 0
1 1 1 0 1 1 1 1 1's complement
1
1 1 1 1 0 0 0 0 2's complement

step-3 add
1 1 1 0 0 0 0 0
1 1 1 1 0 0 0 0
1 1 1 0 1 0 0 0 0
sign
Discard carry bit MSB is 1 i.e sign
step-4 bit=1
step-5 1 1 0 1 0 0 0 0
0 0 1 0 1 1 1 1 1's complement
1
0 0 1 1 0 0 0 0 2's complement

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Binary subtraction

The rules of binary subtraction are

0-0=0

0-1=1 with borrow 1

1-0=1

1-1=0

Subtraction can be performed using 3 methods

Ordinary binary subtraction

Subtraction using 1‘s complement
Subtraction using 2‘s complement

Ordinary binary subtraction

This is the simple method of subtraction of bits according to the rules of binary subtraction

Eg:

1 0 0 1
-0 1 0 1
0 1 0 0

1 1 0 . 1 0 1 1 1 0
-0 1 0 . 0 0 0 1 0 1
1 0 0 . 1 0 1 0 0 1

1 0 1 1 . 0 0 1
-0 1 1 1 . 1 0 1
0 0 1 1 . 1 0 0

Subtraction using 1’s complement

Unsigned numbers

There are two cases

The number of digits of minuend are less than the comprehend

The comprehend is smaller than minuend or the number of digits of comprehend are
lesser than minuend

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The number of digits of minuend are less than the comprehend

Inserting zero‘s to left of the minuend

Take 1‘s complement for minuend
Add both comprehend and minuend
Carry that is generated is added to LSB to obtain result
Eg: Subtract 1100 from 1101001

1 1 0 1 0 0 1 comprehend
1 1 0 0 minuend

step-1 Inserting zero‘s to left of the minuend

0 0 0 1 1 0 0

step-2 Take 1‘s complement for minuend

0 0 0 1 1 0 0
1 1 1 0 0 1 1 1's complement

step-3 Add both comprehend and minuend

1 1 0 1 0 0 1
1 1 1 0 0 1 1
1 1 0 1 1 1 0 0

step-4 Carry that is generated is added to LSB to obtain result

1 0 1 1 1 0 0
1
1 0 1 1 1 0 1

The comprehend is smaller than minuend or the number of digits of comprehend

are lesser than minuend

Inserting zero‘s to left of the comprehend

Take 1‘s complement for minuend
Add both comprehend and minuend
There is no end around Carry so the result is to be again take 1‘s complement

Eg: Subtract 110100101 from 110101

1 1 0 1 0 1 comprehend
1 1 0 1 0 0 1 0 1 minuend

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step-1 Inserting zero‘s to left of the comprehend

0 0 0 1 1 0 1 0 1 comprehend

step-2 Take 1‘s complement for minuend

1 1 0 1 0 0 1 0 1 minuend
0 0 1 0 1 1 0 1 0 1's complement min

step-3 Add both comprehend and minuend

0 0 0 1 1 0 1 0 1 comprehend
0 0 1 0 1 1 0 1 0 1's complement min
0 1 0 0 0 1 1 1 1

There is no end around Carry so the result is to be again take 1‘s

step-4 complement
0 1 0 0 0 1 1 1 1
1 0 1 1 1 0 0 0 0 Final result

Signed numbers

Case 1: subtracting smaller number from a larger number

Convert decimal number to binary number

Take 1‘s complement for minuend
Add both comprehend and minuend
End around carry bit is added to LSB of the result

Eg: Subtract 16 from 25

step-1 Convert decimal number to binary number

25 0 0 0 1 1 0 0 1 comprehend
16 0 0 0 1 0 0 0 0 minuend

step-2 Take 1‘s complement for minuend

0 0 0 1 0 0 0 0 minuend
1 1 1 0 1 1 1 1 1's complement min

step-3 Add both comprehend and minuend

0 0 0 1 1 0 0 1 comprehend
1 1 1 0 1 1 1 1 1's complement min
1 0 0 0 0 1 0 0 0

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step-4 End around carry bit is added to LSB of the result

0 0 0 0 1 0 0 0
1
0 0 0 0 1 0 0 1 Final result

Case 2: subtracting larger number from a smaller number

Convert decimal number to binary number

Take 1‘s complement for minuend
Add both comprehend and minuend
To verify the magnitude the result is converted to its 1‘s complement again

Eg: Subtract 25 from 16

step-1 Convert decimal number to binary number

16 0 0 0 1 0 0 0 0 comprehend
25 0 0 0 1 1 0 0 1 Minuend

step-2 Take 1‘s complement for minuend

0 0 0 1 1 0 0 1 Minuend
1 1 1 0 0 1 1 0 1's complement min

step-3 Add both comprehend and minuend

0 0 0 1 0 0 0 0 comprehend
1 1 1 0 0 1 1 0 1's complement min
1 1 1 1 0 1 1 0
sign
step-4 To verify the magnitude the result is converted to its 1‘s complement again
1 1 1 1 0 1 1 0
0 0 0 1 0 0 1 1's complement & final result

Subtraction using 2’s complement

Unsigned numbers

Case 1: subtracting smaller number from a larger number

Convert decimal number to binary number

Inserting zero‘s to left of the minuend
Take 2‘s complement for minuend

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Add both comprehend and minuend

Carry is ignored

Eg: Subtract 28 from 114

step-1 Convert decimal number to binary number

114 1 1 1 0 0 1 0 Comprehend
28 1 1 1 0 0 Minuend

step-2 Inserting zero‘s to left of the minuend

28 0 0 1 1 1 0 0 Minuend

step-3 Take 2‘s complement for minuend

0 0 1 1 1 0 0 Minuend
1 1 0 0 0 1 1 1's complement
1
1 1 0 0 1 0 0 2's complement min

step-4 Add both comprehend and minuend

1 1 1 0 0 1 0 Comprehend
1 1 0 0 1 0 0 2's complement min
1 1 0 1 0 1 1 0

step-5 Carry is ignored

1 0 1 0 1 1 0 Final result

Case 2: subtracting larger number from a smaller number

Convert decimal number to binary number

Inserting zero‘s to left of the comprehend
Take 2‘s complement for minuend
Add both comprehend and minuend
There is no end around Carry so the result is to be again take 2‘s complement

Eg: Subtract 114 from 28

step-1 Convert decimal number to binary number

28 1 1 1 0 0 comprehend
114 1 1 1 0 0 1 0 minuend

step-2 Inserting zero‘s to left of the comprehend

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28 0 0 1 1 1 0 0 comprehend

step-3 Take 2‘s complement for minuend

1 1 1 0 0 1 0 minuend
0 0 0 1 1 0 1 1's complement
1
0 0 0 1 1 1 0 2's complement min

step-4 Add both comprehend and minuend

0 0 1 1 1 0 0 comprehend
0 0 0 1 1 1 0 2's complement min
0 1 0 1 0 1 0

step-5 There is no end around Carry so the result is to be again take 2‘s complement
0 1 0 1 0 1 0
1 0 1 0 1 0 1 1's complement
1
1 0 1 0 1 1 0 2's complement & final result

Signed numbers

Case 1: subtracting smaller number from a larger number

Convert decimal number to binary number

Take 2‘s complement for minuend
Add both comprehend and minuend
Carry is ignored and represent sign bit

Eg: Subtract 32 from 64

step-1 Convert decimal number to binary number

128 64 32 16 8 4 2 1
64 0 1 0 0 0 0 0 0 comprehend
-32 0 0 1 0 0 0 0 0 minuend
32

step-2 Take 2‘s complement for minuend

0 0 1 0 0 0 0 0 minuend
1 1 0 1 1 1 1 1 1's complement
1
1 1 1 0 0 0 0 0 2's complement min

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step-3 Add both comprehend and minuend

0 1 0 0 0 0 0 0 comprehend
1 1 1 0 0 0 0 0 2's complement min
1 0 0 1 0 0 0 0 0
Carry is ignored and represent sign
step-4 bit
0 0 1 0 0 0 0 0 Final result
sign

Case2: subtracting larger number from a smaller number

Convert decimal number to binary number

Take 2‘s complement for minuend
Add both comprehend and minuend
There is no end around Carry so the result is to be again take 2‘s complement

Eg: Subtract 64 from 32

step-1 Convert decimal number to binary number

128 64 32 16 8 4 2 1
32 0 0 1 0 0 0 0 0 comprehend
-64 0 1 0 0 0 0 0 0 minuend
-32

step-2 Take 2‘s complement for minuend

0 1 0 0 0 0 0 0 minuend
1 0 1 1 1 1 1 1 1's complement
1
1 1 0 0 0 0 0 0 2's complement min

step-3 Add both comprehend and minuend

0 0 1 0 0 0 0 0 comprehend
1 1 0 0 0 0 0 0 2's complement min
1 1 1 0 0 0 0 0
sign

step-4 There is no end around Carry so the result is to be again take 2‘s complement
1 1 1 0 0 0 0 0
0 0 0 1 1 1 1 1 1's complement

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1
0 0 1 0 0 0 0 0 2's complement & final result

Digital codes

Code is a symbolic representation of discrete elements of information which may be in

the form of numbers, letters or any other varying physical quantities
The symbol used is a string of binary digits 0 & 1 & these are arranged according to the
rules of code. The group of bits(0 & 1) is known as a ―binary code or digital code‖
There are two types of digital codes
Numeric codes
Alphanumeric code(character codes)
Numeric codes are broadly divided into 4 classes they are
Weighted codes
Self-complementing codes
Cyclic or reflected codes
Error detecting & correcting codes

Alphanumeric code (character codes)

Alphanumeric code are used to represent numbers, letters, symbols and instructions

Eg: ASCII code

Weighted codes

It obeys the positional weighting principles. In weighted code, the bits are multiplied by the
weights indicated and the sum of the weighted bits gives the decimal digit

Eg: The codes 8421(BCD), 2421 code

Binary coded decimal (BCD) [8421 code]

BCD uses the binary number system to specify the decimal number 0 to 9.it is composed
of four bits
The weights are assigned according to the position occupied by these digits

BCD code
Decimal 8421
0 0000
1 0001
2 0010
3 0011

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4 0100
5 0101
6 0110
7 0111
8 1000
9 1001

Eg: Write BCD code for a decimal number 96.42

=>9 6 . 4 2

=>1001 0110 0100 0010

=>[1001011001000010]BCD

Disadvantages of BCD

Only 10 possible combinations are used to represent decimal numbers. remaining six
combinations of 4 bits are wasted
It is difficult to obtain complements used in subtraction

The 2421 code

A weighted code is the 2421 code. Here the weight 2 is repeated twice

Decimal 2421 code

0 0000
1 0001
2 0010
3 0011
4 0100
5 1011
6 1100
7 1101
8 1110
9 1111
Self complementing codes

The self complementing code may or may not be weighted

If a code is constructed such that when we replace a 1 by a 0 or 0 by a 1 in the 4 bit code.
a code for the 9‘s complement of the digit is obtained then such a code is called self
complementing code

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Example of self complementing weighted code is the 2421 code

code for Digit

2421 complement complement
Decimal code 2421 decimal
0 0000 1111 9
1 0001 1110 8
2 0010 1101 7
3 0011 1100 6
4 0100 1011 5
5 1011 0100 4
6 1100 0011 3
7 1101 0010 2
8 1110 0001 1
9 1111 0000 0
Excess-3 code

It is an important unweighted self complementing code

It is formed by adding 0011(3) to the BD in the normal weighted form so it is called
excess-3 or xs-3 code
Example for self complementing non weighted code is the Excess-3 code

Digit
code for complement
Decimal Excess-3 complement decimal
0 0011 1100 9
1 0100 1011 8
2 0101 1010 7
3 0110 1001 6
4 0111 1000 5
5 1000 0111 4
6 1001 0110 3
7 1010 0101 2
8 1011 0100 1
9 1100 0011 0
Gray code

The gray code is a non weighted code. It differs from the preceding number by a single bit. So it
is called the ―unit distance code‖. It is also called reflected code or cyclic code

Binary to gray code conversion

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The MSB in the gray code is same as the corresponding MSB in the binary number
Going from left to right each adjacent pair of binary code bits are added to get the next
gray bit. The carries generated are ignored

Eg:

Gray to binary conversion

The MSB in the binary is the same as the corresponding MSB in the gray code
Going from left to right each binary code generated is added to the gray code bit in the
next adjacent position .the carries generated are ignored

Eg:

Gray
Decimal Binary code
0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000

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Error detection & correction codes

Parity generators/checkers
In a digital system while codes are being transferred from one point to another, error can
occur. There will be undesired changes in the coded information like a 0 may change to 1
may change to 0.
Error detection can be done using parity bit.
The sum of two bits can be generated by an EX-OR gate. When the number is 1s on the
inputs is even, the output is low and when the number of 1s is odd, the output is high.

It is used to check for odd or even parity on a 9 bit code. (1 bit parity+8 data bits). The
inputs are labelled an A to I.
When number of 1s on the inputs is even, even output is high and odd is low.
When number of 1s on the inputs is odd, an odd output is high and even is low.

Parity checker
When this device is used as an even parity checker, the number of input bits should
always be even. When a parity error occurs the ∑even output goes low and the ∑odd
output goes high.
When it is used as an odd parity checker the number of inputs bits should always be
odd. When a parity error occurs, the ∑odd output goes low and the ∑even output goes
high.

Parity generator
When this device is used as an even parity generator the parity bit is taken at the ∑odd
output because their output is a 0. If there is an even number of input bits and it is a 1 if
there is an odd number.
When used as an odd parity generator, the parity bit is taken at the ∑even output because
it is a 0 when the number of inputs is odd.

Parity bit

Parity bit is a additional bits is used for a bit error detection

Parity bit are of two types
Even parity

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2. Odd parity

Even parity

If the total number of 1‘s is even in the code or number then it is called as even parity

Odd parity

If the total number of 1‘s is Odd in the code or number then it is called as Odd parity

Even parity Odd parity

BCD P BCD P
0000 0 0000 1
0001 1 0001 0
0010 1 0010 0
0011 0 0011 1
0100 1 0100 0
0101 0 0101 1
0110 0 0110 1
0111 1 0111 0
1000 1 1000 0
1001 0 1001 1

Only single bit errors can be detected using this method if doesn‘t check for 2 bit errors
in a group

Error correction code

Hamming code

The hamming code is used not only to detect a bit error but also to identify the bit that is
in error so that it can be corrected
The hamming code uses a number of parity bits depending on the number of information
bits, located at certain position in the code group
The steps are
Number of parity bits
Placement of parity bits in code
Assignment of parity bit values
Detecting & correcting an error

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Number of parity bits

The number of parity bits to be included with the information bits is to be determined by
the relationship
P
2 >=M+P+1
P->number of parity bits M-
>number of information bits
The information bits are known but parity bit are found by trial & error method until the
relationship is satisfy

Placement of parity bits in code

The parity bits are placed in the position that are ascending power of 2(1,2,4,8…)

1 2 3 4 5 6 7
Bits P1 P2 M1 P3 M2 M3 M4

P1,P2,P3=>parity bits
M1,M2,M3 & M4=>message bits or information bits
Assignment of parity bit values

Each parity bit should be assigned value of 1 or 0

Bit designation P1 P2 M1 P3 M2 M3 M4
Bit position 1 2 3 4 5 6 7
Binary position 001 010 011 100 101 110 111
Information bits (Mn)
Parity bits(Pn)

Each bit position is numbered is binary

Information or message and parity bit locations are indicated in two rows
Parity bit 1 checks all bit positions including itself that have 1‘s in the same location(right
most) in the binary position number i.e,p1 checks positions 1,3,5 &7
Parity bit 2 checks has a 1 in the middle position & so it checks positions 2,3,6 &7
Parity bit 3 checks has a 1 in the left most in the binary position and so it checks positions
4,5,6 &7

Detecting & correcting an error

The number of parity checks made depend on the number o parity bits in the error
correcting code
The method is as follows

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Checks the p1 group for proper parity

A ‗0‘ represent good parity check
A ‗1‘ represent bad parity check
Repeat this for each parity group
The binary number formed by the result of all parity checks designates the
position of the code bit that is an error. This is the error position code
If checks are good that means there is no error. The first parity check generate the LSB
and the last parity check generate the MSB

Problem

1. Find single error correcting code for 1001 using even parity

Solution:

a. Number of parity bits required

p
By relation 2 >=m+p+1
M=4
P=1 21>=4+1+1
2>=6-----F
P=2 22>=4+2+1
4>=7-------F
P=3 23>=4+3+1
8>=8-------T
So the number of parity bits is 3
The information bits are 4
Total number of bits is code 4+3=7bits
b. Placement of parity bits in code is
0 1 2
2 ,2 ,2 ,………….
1,2,4,………

c. Assignment of parity bit values

Bit designation P1 P2 M1 P3 M2 M3 M4
Bit position 1 2 3 4 5 6 7
Binary position 001 010 011 100 101 110 111
Information bits (Mn) 1 0 0 1
Parity bits(Pn) 0 0 1

Parity bits are to be determined

P1 checks position 1,3,5,7 =>-101

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Total number of 1‘s is 2 for even parity P1 should be 0

P2 checks position 2,3,6,7 =>-101
Total number of 1‘s is 2 so good parity is 0
P3 checks position 4,5,6,7 =>-001
Total number of 1‘s is 1 so bad parity is 1

The single error correcting code for information 1001 using even parity is 0011001

Problem 2

Suppose information transmitted is the code word 0011001 if it is received as 0010001, find the
error that has occurred in transmission if even parity is used

Solution: construct bit position table

Bit designation P1 P2 M1 P3 M2 M3 M4
Bit position 1 2 3 4 5 6 7
Binary position 001 010 011 100 101 110 111
Transmitted code 0 0 1 1 0 0 1
Received code 0 0 1 0 0 0 1

Here we are using detecting and correcting an error

There are 3 parity checks because number of parity bits is
3 First parity check
P1 checks position 1,3,5,7=0101(even number of 1‘s)->good
parity=>0(LSB) Second parity check
P2 checks position 2,3,6,7=0101(even number of 1‘s)->good
parity=>0 Third parity checks
P3 checks position 4,5,6,7=0001(odd number of 1‘s)->bad parity=>1(MSB)
so the error position code is 100.this shows that the bit in position 4 is in error
it is 0 in the received code but it should be a 1 so then the corrected code will be
0011001which will match the transmitted code

character code

ASCII[American standard code for information interchange)

It is a 7 bit code proposed by ANSI(American national standard institute)

The ASCII code is a 7 bit code with the format X6 X5 X4 X3 X2 X1 X0

Where each X is a 0 or 1

ASCII character set

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From the table the ASCII code of the upper case letter ‗A‘ has a code 100 0001 whose
equivalent in decimal number is 65
The range of ASCII set is from 0 to 127

Answer the following questions:

Subtract 11100(2) from 1110010(2). (1M OCT/NOV 2011)

What is hamming code?
Subtract 28 from 114 using 2‘s complement. (3M OCT/NOV 2011)
Explain 2421 code. (2M OCT/NOV 2011) (2M OCT/NOV 2012)
Convert (11011.1011)2 to decimal (1M OCT/NOV 2012)
What is positional number system? (1M OCT/NOV 2012)
Subtract 128 – 64 using 1‘s complement. (3M OCT/NOV 2012)
Convert (73)8 to () 2(2M OCT/NOV 2012)
Explain self complementing, weighted and excess-3 code with an example. (3M
NOV/DEC 2010)
List all the unused combinations in BCD, 2421, excess-3 and excess-3 gray code. .(3M
NOV/DEC 2010)
Derive a circuit for a 3 bit parity generator and a 4 bit parity checker using an even parity.
.(3M NOV/DEC 2010)

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Chapter-4
Basic Computer Organization And Design
Computer Organization
The organization of the computer is defined by its internal registers, timings and the set of
instructions that it uses.

Program
A program is a set of instructions that specify the operations, operands and the sequence by
which processing has to occur.

Instruction
An instruction is a binary code that specifies a sequence of micro operations for the computer.

Instruction Codes
An instruction code is a group of bits that instruct the computer to perform a specific operation.
It is usually divided into parts:
Operation code or opcode
Operand

Operation code or opcode:

The operation code of an instruction is a group of bits that define operations such as add,
subtract, multiply, shift and complement.

Operand:
The operand is the data on which the operation is to be performed and it is stored either in
processor register or in memory.

Opcode: specify 16 possible operations (4 bit)

Address: specify the address of an operand (16 bit)

Ex:
ADD A, B
ADD is an opcode
A and B are operands.
Stored Program Organization

The simplest way to organize a computer is to have one processor register called Accumulator
(AC) and an instruction code format consisting of two parts:
Opcode: specifies operation to be performed.
Operand: specifies an address of the data in the memory.

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The data read from the memory is operated together with the content of AC.
Instructions are stored in one section of memory and the data is stored in another section.

Fig: Stored program organization of a computer

Immediate, Direct And Indirect Address

When the second part of an instruction code specifies an operand, the instruction is said to
have an immediate operand.

When the second part specifies the address of an operand, the instruction is said to have a
direct address.

When the second part of the instruction specifies an address of a memory word in which the
address of the operand is found, it is called indirect address.

Effective Address: The address that can be directly used without modification to access an
operand in computation type instruction, or as the target address for a branch type instruction.

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Basic Computer Registers

A register is a very small amount of very fast memory that is built into the CPU.

The different registers available in basic computer are:

Accumulator (AC):
AC is an l6-bit register in which intermediate arithmetic and logic results are stored.

Data Register (DR):

DR is an l6-bit register used to hold memory operands (data).

Temporary Register (TR):

TR is a 16-bit register which provides temporary storage of variables or results.

Instruction Registers (IR):

IR is a 16-bit register used to hold a copy of the instruction which the processor is to execute.

Address Register (AR):

AR is an l2-bit register which specifies the address in memory for next read or writes operations.

Program Counter (PC):

PC is an l2-bit register used to holds the address of the next instruction to be read from
memory after the current execution is executed

Input Register (INPR):

INPR is an 8-bit register which receives a character from an input device and delivers it to the
AC.

Output Register (OUTR):

OUTR is an 8-bit register which receives information from AC and transfer it to the output
device.

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Common Bus System

The basic computer has eight registers, a memory unit, and a control unit.
Paths must be provided to transfer information from one register to another and between
memory and registers.
The memory places the output onto the bus when read input is activated.
The specific output that is selected for the bus lines at any given time is determined from
the binary value of the selection variables S2 S1, and S0.

S2 S1 S0 Register
0 0 0 X
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory

The particular register whose LD (Load) input is enabled receives the data from the
BUS.
The memory receives the contents of the bus when its write input is activated.
The content of any register can be applied onto the bus and an operation can be
performed in the adder and logic circuit during the same clock cycle.
The clock transition at the end of the cycle transfers the content of the bus into the
designated destination register and the output of the adder and logic circuit into AC.
For example, the two micro-operations:

This can be done by placing the content of AC on the bus (with S2S1S0 = 100), enabling
the LD(load) input of DR, transferring the content of DR through the adder and logic
circuit into AC, and enabling the LD (load) input of AC, all during the same clock cycle.

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Fig:common bus system

Basic Computer Instructions

Each format has 16 bits.

The operation code (opcode) part of the instruction contains 3- bits and the meaning of
the remaining 12 bits, depends on the operation code.
A memory reference instruction:
Opcode: 000 to 110
12 bits: specify an address and
th
Leftmost bit (15 bit I): specify the addressing
mode I=0 for direct address and

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I=1 for indirect address.

The register-reference instruction:
Opcode: 1 1 1
th
Leftmost bit (15 bit I):0.
12 bits: specifies an operation on the AC register.
Input output instruction:
Opcode: 1 1 1
th
Leftmost bit (15 bit I):1.
12 bits: specify the type of input-output operation or test performed.

The total number of instructions chosen for the basic computer is 25 as shown in Fig:

Instruction Set Completeness

The set of instructions are said to be complete if the computer includes a sufficient number of
Instructions in each of the following categories:

Arithmetic, logical, and shift instructions:

ADD, CMA, INC, CIR, CIL, AND, CLA

Instructions for moving information to and from memory and processor registers
LDA, STA

Program control instructions together with instructions that check status conditions
BUN, BSA, ISZ

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Input and output instructions

INP, OUT
Timing And Control

CPU is partitioned into Arithmetic Logic Unit (ALU) and control unit (CU).
"The function of control unit is to generate relevant timing and control signals to
all Operations in the computer."

It controls the flow of data between the processor and memory and peripherals.

There are two major types of control organization: Hardwired control and micro Programmed
control.

Hardwired control Micro programmed control

The control logic is implemented with gates, The control information

flip-flops, decoders, and other digital circuits. is stored in a control memory.
Control signals generation is fast Control signals generation is slower
Difficult to modify the design It is flexible, and easy to modify the design.

Fig: Hardwired Control Unit organization of basic computer

Control unit consists of:

Instruction register
Number of control logic gates
Two decoders

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4-bit Sequence counter
An instruction read from memory is placed in the instruction register (IR).
The instruction register is divided into three parts: the I bit, operation code, and address
Part.
First 12-bits (0-11) to specify an address, next 3-bits specify the operation code
(opcode) Field of the instruction and
Last left most bit specify the addressing mode I.
0 for direct address
1 for indirect address
First 12-bits (0-11) are applied to the control logic gates.
The operation code bits (12 - 14) are decoded with a 3 x 8 decoder.
The eight outputs (D0 through D7) from a decoder goes to the control logic gates
to Perform specific operation.
Last bit 15 is transferred to a I flip-flop designated by symbol I.
The 4-bit sequence counter SC can count in binary from 0 through 15.
The counter output is decoded into 16 timing pulses T0 through T15.
The sequence counter can be incremented by INR input or clear by CLR input
Synchronously.

For example:
Consider the case where SC is incremented to provide timing signals T0, Tl, T2, T3, and T4
in Sequence.

Instruction Execution Cycle

The steps that the control unit carries out in executing a program are:
(1) Fetch the next instruction to be executed from memory.

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Decode the opcode.

Read operand(s) from main memory.
Execute the instruction and store results.

The Flow chart for instruction execution cycle is as shown below:

Fig: Flowchart for instruction execution cycle

Fetch And Decode

Initially, the program counter PC is loaded with the address of the first instruction in the
Program.
The Sequence counter SC is cleared to 0, providing a decoded timing signal T0.
After each clock pulse, SC is incremented by one, so that the timing signals go through T0,
Tl, T2, and so on.
The micro operations for the fetch phase can be specified by the following
Register transfer statement:
T0: AR ← PC
The address stored in PC is transferred to AR.

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T1: IR ← M [AR], PC ← PC + 1
The instruction stored in memory address contained in AR is transferred to AR
and PC is incremented to point to the next instruction.

Register transfer for the fetch phase is as shown in fig:

Fig: Register transfer for the fetch phase

To provide the data path for the micro operation T0: AR←PC

The content of PC is placed onto the bus by making the bus selection inputs S2 Sl S0:010.
The content of the bus is transferred to AR by enabling the LD input of AR.

To provide the data path for the micro operation T1: IR←M [AR], PC←PC +1

The read input of memory is enabled.

The content of memory is placed onto the bus by making S2 SI S0: 111.
The content of the bus is transferred to IR by enabling the LD input of IR.
PC is Incremented by enabling the INR input of PC.

The micro operations for the decode phase con be specified by the following
Register transfer statements:

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T2: D0,…, D1 ← Decode IR (12-14), AR ← IR(0 −11), 1 ← IR (15)

l. The 3-bit Opcode in the IR which is stored from 12-I4 is decoded.

Address part of the instruction from 0-11 is transferred to AR
The indirect address in the 15th position is transferred to flip-flop 'I'.

Determining The Type Of The Instruction

After the decoding process, during clock transition T3, control-unit determines the type of
Instruction stored in IR.

1. If the decoder output is D7:1 then the opcode in binary is 1 1 l.

If opcode: l 1 1 then the instruction is either register transfer or input-output instruction.
th
Then if the 15 bit I=0, it is register transfer instruction.
th
Then if the 15 bit I=1, it is input output instruction.

If the-decoder output is D7:0 then the opcode in binary is must be one of the values from
to 110.
Then the instruction is memory reference instruction. Then
th
if the 15 bit I=0, it is direct address. Then if
th
the 15 bit I=1, it is indirect address.
.
This can be symbolized as follows:
D7'I T3: AR ← M [AR] D7'I'T3:
Nothing
D7 I' T3: Execute a register-reference instruction
D7I T3: Execute an input-output instruction

Register-Reference Instructions

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Register-reference instructions are recognized by the control when D7 = 1 and I= 0. These

instructions use bits 0 through 11 of the instruction code to specify one of 12 instructions.
These 12 bits are available in IR (0-11). They were also transferred to AR during time T2.

Memory -Reference Instructions

The effective address of the instruction is in the address register AR and was placed there
during timing signal T2 when I = 0, or during timing signal T3 when I=1.

AND to AC
This is an instruction that performs the AND logic operation on pairs of bits in AC and the
memory word specified by the effective address.
D0T4: DR←M[AR]
D0T5: AC←AC +DR, SC←O

ADD to AC
This instruction adds the content of the memory word specified by the effective address to the
value of AC.
The sum is transferred into AC and the output carry Cout is transferred to the E
(extended Accumulator) flip-flop.

D1T4: DR ←M[AR]
D1T5: AC ← AC + DR, E ←Cout, SC ← 0

LDA: Load to AC
This instruction transfers the memory word specified by the effective address to AC. The
Micro operations needed to execute this instruction are
D2T4: DR ←M[AR]
D2T5: AC ← DR, SC ← 0

STA: Store AC

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This instruction stores the content of AC into the memory word specified by the effective
address.
D3T4: M [AR] ← AC, SC ←0

BUN: Branch Unconditionally

D4T4: PC ←AR, SC ←0

BSA: Branch and Save Return Address

D5T4: M[AR] ←PC, AR ← AR + 1 D5T5: PC ←AR, SC ← 0

“The BSA instruction performs the function usually referred to as a subroutine call.
The indirect BUN instruction at the end of the subroutine performs the function referred to
as a subroutine return.”

This instruction is useful for branching to a portion of the program called a subroutine or
Procedure.

The BSA instruction is assumed to be in memory at address 20.

The I bit is 0 and the address part of the instruction has the binary equivalent of 135.
After the fetch and decode phases, PC contains 21, which is the address of the next
instruction in the program (referred to as the return address).
AR holds the effective address 135. This is shown in part (a) of the figure.
The BSA instruction performs the following numerical operation:
M [135] ← 21, PC ← 135 + 1 = 136
The result of this operation is shown in part (b) of the figure.
The return address 21 is stored in memory location 135 and control continues with the
subordinate program starting from address 136.
The return to the original program (at address 21) is accomplished by means of an
indirect BUN instruction placed at the end of the subroutine.

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When this instruction is executed, control goes to the indirect phase to read the effective
address at location 135, where it finds the previously saved address 21.
When the BUN instruction is executed, the effective address 21 is transferred to PC.
The next instruction cycle finds PC with the value 21, so control continues to
Execute the instruction at the return address.

ISZ: Increment and Skip if Zero

D6T4: DR ←M [AR]
D6T5: DR ← DR + 1
D6T6: M [AR] ← DR, if (DR = 0) then (PC ← PC + 1), SC ←0

Flowchart For Memory Reference Instructions

Input, Output And Interrupt

Instructions and data stored in memory must come from some input device.
Computational results must be transmitted to the user through some output device.
Input-Output Configuration
The terminal device (KEYBOARD and PRINTER) sends and receives serial information.
The transmitter interface receives serial information from the keyboard and transmits it to
INPR.
The receiver interface receives information from OUTR and sends it to the printer serially.

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The two control flags FGI and FGO are used to control the input and output transfer.
When a key is struck in the keyboard, an 8-bit alphanumeric code is shifted into INPR and
the input flag FGI is set to 1.
The computer checks the flag bit; if it is 1, the information from INPR is transferred in
parallel into AC and FGI is cleared to 0.
AC (0−7) ← INPR, FGI ← 0
The OUTR works similarly but the direction of information flow is reversed.
Initially, the output flag FGO is set to 1.
The computer checks the flag bit, if it is 1, the information from AC is transferred in parallel
to OUTR and FGO is cleared to 0.

Input Output Instructions

Input and output instructions are needed for transferring information to and from AC register,
for checking the flag bits, and for controlling the interrupt facility.
Input-output instructions have an operation code 1111 and are recognized by the control
when D7 = 1 and I = 1.
The control functions and micro operations for the input-output instructions are listed
below:
D7 IT3 = p (common to all input-output instructions) IR(i) = Bi [bit in IR (6−11) that
specifies the instruction]

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Interrupt Cycle

An interrupt flip-flop R is included in the computer.

When R = 0, the computer goes through an instruction cycle.

Instruction Cycle

During the execute phase of the instruction cycle IEN is checked by the control.
If IEN=0, it indicates that the programmer does not want to use the interrupt, so control
continues with the next instruction cycle.
If IEN = 1, control checks the flag bits FGI and FGO.
If both flags FGI=0 and FGO=0
It indicates that neither the input nor the output registers are ready for transfer of
information.
In this case, control continues with the next instruction cycle.
If either flag FGI or FGO is set to 1 while IEN = 1, flip-flop R is set to 1.

At the end of the execute phase, control checks the value of R, and if R=1, it goes to an
interrupt cycle instead of an instruction cycle.

Interrupt Cycle

The interrupt cycle is a hardware implementation of a branch and save return address
Operation.
The return address available in PC is stored in a specific location. Here we choose the
memory location at address 0 as the place for storing the return address.
M[0] ← PC
Then the address 1 is inserted into PC to branch to location 1.
PC ← 1
The IEN and R are cleared so that no more interruptions can occur until the interrupt
request from the flag has been serviced.
IEN ← 0 , R← 0

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Example:

Suppose that an interrupt occurs and R is set to 1 while the control is executing the
instruction at address 255. At this time, the return address 256 is in PC.
The programmer has previously placed an input-output service program in memory
starting from address 1120 and a BUN 1120 instruction at address 1.
The content of PC (256) is stored in memory location 0, PC = 1, and R=0.
At the beginning of the next instruction cycle,
The instruction that is read from memory is in address 1 since this is the content of PC.
The branch instruction at address 1 causes the program to transfer to the input-output
service program at address 1120.
This program checks the flags, determines which flag is set, and then transfers the required
input or output information.
Once this is done, the instruction ION is executed to set IEN to 1 (to enable further
interrupts), and the Program returns to the location where it was interrupted.

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Flowchart For Computer Operation

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Control Functions And Micro Operations For Basic Computer

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Questions:
Define computer organization? (Nov-2012:1-Mark)
Explain BUN and LDA instructions? (Nov-2012:5-Marks)
What is program?
What is an instruction code?
Define opcode and operand? (Nov-2012:1-Mark)
Explain basic computer three instruction code formats. (Nov-2011:9-Marks)
What is immediate address?
Define direct and indirect address?
What is effective address?
What is BUS?
What are the 3 control inputs for registers in common bus system?
Mention the 4 steps of instruction cycle?
Explain LDA and STA instructions? (Nov-2011:5-Marks)
Give the micro operations for fetch and decode phase?
What is interrupt?
Define micro operation. Give example. (Nov-2012 & Nov:2011:1-Mark)
Define macro operation. Give example.
What is hardwired control unit?
What is register transfer and register transfer language? (Nov-2011:1-Mark)
Explain stored program organization of a basic computer with a neat diagram?
Explain the various registers of basic computer how the basic computer registers are
connected to a common bus? (Nov-2010:14-Marks)
Distinguish between hardwired and micro programmed control unit organization?
Explain the control signals generation in basic computer (hardwired control unit
organization)?
Explain BSA, AND, ISZ memory reference instructions? (Nov-2010:5-Marks)
Explain any five register reference instructions?
Explain input and output configuration with a neat diagram?
Explain interrupt cycle with a neat diagram?
Explain various input output instructions?

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Chapter-5
Central Processor Organization

Central Processing Unit (CPU)

The CPU is the brains of the computer where most calculations take place.
The part of the computer that performs the bulk of data-processing operations is
called the CPU.

Major Components Of CPU

The CPU is made up of three major parts: Register set, ALU, Control units

Register set: Stores intermediate data during the execution of instructions.

Arithmetic logic unit (ALU): Performs the required micro-operations for executing the
instructions.
Control unit: supervises the transfer of information among the registers and instructs the ALU
as to which operation to perform by generating control signals.

Bus Organization Of CPU

Memory access is the most time-consuming operation in a computer. It is more
convenient and more efficient to store the values such as pointers, counters, return
address, temporary results and intermediate results in processor registers.
When a large number of registers are included in the CPU, it is most efficient to connect
them through a common bus system.

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The output of each register is connected to two multiplexers (MUX) to form the two
buses A and B.
The selection lines in each multiplexer select one register or the input data for the
particular bus.
The A and B buses form the inputs to a common arithmetic logic unit (ALU).
The operation selected in the ALU determines the arithmetic or logic micro operation that
is to be performed.
The result of the micro operation is available for output data and also goes into the inputs
of all the registers.
The register that receives the information from the output bus is selected by a decoder.
The decoder activates one of the register load inputs, thus providing a transfer path
between the data in the output bus and the inputs of the selected destination register.
The control unit that operates the CPU bus system directs the information flow through
the registers and ALU by selecting the various components in the system.

For example, to perform the operation.

R1 ← R2 + R3
The control must provide binary selection variables to the following selector inputs:

MUX A selector (SELA): to place the content of R2 into bus A.

MUX B selector (SELB): to place the content of R3 into bus B.
ALU operation selector (OPR): to provide the arithmetic addition A + B.
Decoder destination selector (SELD): to transfer the content of the output bus into R1.

Control Word
“Control word is a word whose individual bits represent the various control signals‖

Format:
3 3 3 5
SELA SELB SELD OPR

It consists of four fields.

Three fields contain three bits each, and one field has five bits.
The three bits of SELA select a source register for the A input of the ALU.
The three bits of SELB select a register for the B input of the ALU.
The three bits of SELD select a destination register using the decoder and its seven
load output.
The five bits of OPR select one of the operations in the ALU.

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The 14-bit control word when applied to the selection inputs specify a particular
micro operation.
The encoding of register selection is specified in the following table:

When SELA or SELB is 000, the corresponding multiplexer selects the external
input data.
When SELD = 000, no destination register is selected but the contents of the output
bus are available in the external output.
The ALU provides arithmetic and logic operations. The encoding of the ALU
operations for the CPU is specified in Table.

The OPR field has five bits and each operation is designated with a symbolic name.

Example Of Micro Operations

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Types Of CPU Organizations

Single Accumulator organization
General Register Organization
Stack organization

Single Accumulator organization:

―In This organization all operations are performed with an implied accumulator
register‖.

AC is the accumulator register and M[X] symbolizes the memory word located at
address X.

General Register Organization:

―In this organization the computer needs 3 register fields‖.

The number of address fields in the instruction can be reduced from three to two if
the destination register is the same as one of the source registers.
 Thus the instruction ADD R1, R2 denote the operation R1 ← R1 + R2.

Stack organization:
Stack: A storage device that stores information in such a manner that the item stored last
is the first item retrieved (LIFO policy).
Stack pointer (SP): points at the top item in the stack
Push: Operation to insert an item into the stack.
Pop: Operation to retrieve an item from the stack.

―In this organization all the operands are implied to be in the stack and hence there is no need
to specify operands with an address field‖

Ex: The instruction ADD in a stack computer consists of an operation code only with no address
field.

This operation has the effect of

Popping the two top numbers from the stack
Adding the numbers and
Pushing the sum into the stack.

There is no need to specify operands with an address field since all operands are implied to be in
the stack.

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Instruction Formats

Mode Opcode Address

The most common fields in instruction formats are:

Mode field: Specifies the way the effective address is determined
Operation code: Specifies the operations to be performed.
Address field: Designates a memory address or a processor register

Types Of Instructions
Based on the number of address fields present in the instruction the instruction can be classified
into following types:

Three Address Instructions

Computers with three-address instruction formats can use three address field to specify either
a Processor register or a memory operand.

Advantages:
Results in short programs
Instructions becomes long

Two Address Instructions

Computers with two-address instruction formats can use two address field to specify either
a Processor register or a memory operand.

One Address Instructions

All operations are done between the AC register and memory operand. Only one memory
address needs to be specified in the address filed of an instruction.

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Zero Address Instructions

No address field is specified in the instruction.

Addressing Modes
―Addressing mode specifies a rule for identifying the operand location‖.

Types Of Addressing Modes

Implied
Immediate
Direct
Indirect
Register
Register indirect
Auto Increment and Auto Decrement
Relative: PC Relative, Indexed, Base Register.

Implied:
In this mode the operands are specified implicitly in the definition of the instruction.
Ex:
The instruction "CMA" is an implied-mode instruction because the operand in the
accumulator register is implied in the definition of the instruction.
Zero-address instructions in a stack-organized computer are implied-mode instructions
since the operands are implied to be on top of the stack.
EA=AC or EA=stack [sp]

Immediate Mode:
In this mode the operand is specified in the instruction itself.
Ex: ADD 5 -----add operand 5 to the contents of accumulator.
Address field=operand.
Direct Address Mode:
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In this mode the effective address is equal to the address part of the instruction.
The operand resides in memory and its address is given directly by the address field of the
instruction.
Ex: ADD A —Add contents of location A to accumulator.
EA = address field A

Indirect Address Mode: In this mode the address field of the instruction gives
the address where the effective address is stored in memory.

Ex: ADD [A] Where A is an indirect address of the operand.

EA=M [A]

Register Mode: In this mode the operands are in registers that reside within the CPU.

Ex: ADD R —Add contents of register R to accumulator.

EA=R

Register Indirect Mode:

In this mode the instruction specifies a register in the CPU whose contents give the address of
the operand in memory.

Ex: ADD [R] where register R contains the address of the operand

EA=M[R]

Autoincrement or Autodecrement Mode:

This is similar to the register indirect mode except that the register is incremented or
decremented after (or before) its value is used to access memory

When the address stored in the register refers to a table of data in memory, it is necessary to
increment or decrement the register after every access to the table.
This can be achieved by using the auto increment or auto decrement mode.

Relative addressing:
EA=Address part of the instruction + Contents of some register

1) PC Relative Address Mode:

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In this mode the content of the program counter is added to the address part of the instruction in
order to obtain the effective address.

EA=Address part of the instruction +contents of PC

2) Indexed Addressing Mode:

In this mode the content of an index register is added to the address part of the
instruction to obtain the effective address.
The index register is a special CPU register that contains an index value.
An index register is assumed to hold an index number that is relative to the address
part of the instruction.

EA=Address part of the instruction +contents of Index Register

Base Register Addressing Mode:

In this mode the content of a base register is added to the address part of the
instruction to obtain the effective address.
A base register is assumed to hold a base address and the address field of the
instruction gives a displacement relative to this base address.

EA=Address part of the instruction +contents of Base

Register. Types Of Computer Instructions
Computers provide different types of instructions to perform various computational tasks.
The computer instructions can be classified into following types:
Data transfer instructions
Data manipulation instructions
Program control instructions

Data Transfer Instructions

Data transfer instructions move data from one place to another place in the computer
without
Changing the data content.
The most common transfers are between memory and processor registers, between
processor registers and input or output, and between the processor registers themselves.

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Data Manipulation Instructions

Data manipulation instructions perform operations on data and provide the computational
Capabilities for the computer.
The data manipulation instructions in a computer are usually divided into three basic types:
Arithmetic instructions
Logical and bit manipulation instructions
Shift instructions

Arithmetic Instructions
These instructions are used to perform arithmetic operations such as addition, subtraction,
multiplication, and division.

Logical and Bit Manipulation Instructions

They are useful for manipulating individual bits or a group of bits that represent binary-
coded information.
Logical Instructions:AND,OR,XOR
Bit Manipulation Instructions: CLR, COM, CLRC, SETC, EI, DI

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Shift Instructions
Shift operations are used to move the the bits of a word to the left or right.

Types of shift operations:

Logical: SHL,SHR
Arithmetic:SHLA, SHRA
Rotate:ROL,ROR,RORC,RORL
In a logical shift, the bit is shifted to the left or right and the vacant bit-positions are
filled in with zeros and shifted bit is discarded.
An arithmetic left shift is identical to a logical left shift, but an arithmetic right shift
causes the most significant bit, the sign bit, to be propagated right.
In a circular shift, the bit shifted out is moved to the position of the bit shifted in.

Program Control
Instructions are stored in memory in consecutive locations.
When processed in the CPU, the instructions are fetched one by one from the memory
and are executed.
Program control instructions are used to alter the flow of execution of a program.

Branch and jump instruction

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Branch ADR or Jump ADR

Allows the programmer to skip sections of a program and branch to any part of the
memory for the next instruction.
Branch and jump instruction causes a transfer of the value of ADR into the PC.
Since PC contains the address of the instruction to be executed, the next instruction
will come from location ADR.

Types of Branch and Jump instructions:

Conditional branch:
Specifies a condition such as branch if zero or branch if positive. If the condition
is met, the PC is loaded with branch address and the next instruction is taken from
this address.

Unconditional branch:
Causes a branch to the specified address without any conditions.

Skip
This is a zero address instruction used to skip the next instruction if the condition is
met.

Call and return

Used with subroutine call and return.

Compare and Test

Used to compare the two operands by performing subtraction and AND operations
between operands and storing the result in status bits.

Status Bit Conditions

It is sometimes convenient to supplement the ALU circuit in the CPU with a status register
where status bit conditions can be stored for further analysis. Status bits are also called
condition-code bits or flag bits.

The four status bits are:

Carry C
Sign S
Zero Z
Overflow V

The bits are set or cleared as a result of an operation performed in the ALU.
1. Bit C (carry) is set to 1 if the end carry C8 is 1. It is cleared to 0 if the carry is 0.

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Bit S (sign) is set to 1 if the highest-order bit F7 is 1. It is set to 0 if the bit is 0.

Bit Z (zero) is set to 1 if the output of the ALU contains all 0's. It is cleared to 0
otherwise.
In other words, Z = 1 if the output is zero and Z = 0 if the output is not zero.
Bit V (overflow) is set to 1 if the exclusive-OR of the last two carries is equal to 1,
and Cleared to 0 otherwise.
This is the condition for an overflow when negative numbers are in 2's complement.
For the 8-bit ALU, V = 1 if the output is greater than +127 or less than -128.

Fig: Block diagram of an 8-bit ALU with a 4-bit status register.

Conditional Branch Instructions

Subroutine Call And Return

―A subroutine is a self-contained sequence of instructions that performs a given
computational Task.‖

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Subroutine call: Transferring the control from main program to the subroutine is called
as subroutine call.
Subroutine return: Transferring the control from the subroutine back to the main
program is called subroutine return.

In assembly language subroutine call is performed using BSA instruction and subroutine return
is performed by placing BUN instruction at the end of the subroutine.

The Subroutine call (BSA) instruction is executed by performing two operations:

The return address available in the PC is stored in a temporary location.
Return address: The address of the next instruction in the main program that has to be
executed next after returning from the subroutine.
Then the control is transferred to the beginning of the subroutine.
This is done by storing the address of the first instruction in the subroutine into PC.
Return From subroutine (BUN):
The last instruction of every subroutine, commonly called return from subroutine, transfers the
return address from the temporary location into the PC.
This results in a transfer of program control to the main program.

The return address can be stored:

In the first memory location of the subroutine or
In a fixed location in memory or
In a processor register or
In a memory stack.

The most efficient way is to store the return address in a memory stack.

The advantage of using a stack for storing the return address is that:
When a succession of subroutines is called, the sequential return addresses can be pushed
into the stack.
The return from subroutine instruction causes the stack to pop and the contents of the top
of the stack are transferred to the program counter.

A subroutine call is implemented with the following micro operations:

SP ←SP - 1 //Decrement stack pointer
M [SP] ←PC //Push content of PC onto the stack
PC ←effective address //Transfer control to the subroutine

If another subroutine is called by the current subroutine, the new return address is pushed
into the stack and so on.
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The instruction that returns from the last subroutine is implemented by the micro operations:
PC←M [SP] Pop stack and transfer to PC
SP ←SP + 1 Increment stack pointer

Program Interrupt
―Program interrupt refers to the transfer of program control from a currently running program
to another service program as a result of an external or internal generated request.‖
Control returns to the original program after the service program is executed.

The interrupt procedure is, in principle, quite similar to a subroutine call except for
three variations
The interrupt is usually initiated by an internal or external signal rather than
from the execution of an instruction.
The address of the interrupt service program is determined by the hardware rather
than from the address field of an instruction. and
An interrupt procedure usually stores all the information.

Comparision Between Interrupt and Subroutine Call:(Nov-2012:5-marks)

Interrupt Subroutine Call

Transferring the control from the main Transferring the control from the main
program to the input output service program to the subrotine
program
Interrupt is initiated by an internal or Subroutine Call is initiated by the execution
external signal of an instruction
The address of interrupt service routine is The address of subroutine call is determined
determined by the hardware by the address field of an instruction.
All the information necessary to define the Only content of the PC is stored
state of the CPU is stored
ION and IOF instruction are used to enable BSA and BUN instructions are used for
and disable interrupts subroutine call and return

The state of the CPU at the end of the execute cycle (when the interrupt is recognized) is
determined from:
The content of the program counter
The content of all processor registers
The content of certain status conditions

Program Status Word

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The collection of all status bit conditions in the CPU is sometimes called a program status word
or PSW.
The PSW is stored in a separate hardware register and contains the status information that
characterizes the state of the CPU.

Types Of Interrupts
There are three major types of interrupts that cause a break in the normal execution of
a program.
They can be classified as:
External interrupts
Internal interrupts
Software interrupts

External interrupts
External interrupts come from input-output (I/O) devices, from a timing device, from a
circuit
monitoring the power supply, or from any other external source.

Internal interrupts arise from illegal or erroneous use of an instruction or data.

Internal interrupts are also called traps.
Examples of interrupts caused by internal error conditions are register overflow,
attempt to divide by zero, an invalid operation code, stack overflow, and protection
violation.

Software interrupt is initiated by executing an instruction.

Software interrupt is a special call instruction that behaves like an interrupt rather than a
subroutine call.
It can be used by the programmer to initiate an interrupt procedure at any desired point in
the program.

Comparision Between Internal and External Interrupts:(Nov-2011:5-marks)

Internal interrupt External interrupt

It is initiated by some exception condition It is initiated by an external event
Caused by program
The error condition occur due to premature External events are caused due to I/O
termination of instruction execution devices,Timing devices,power supply etc.
It is synchronous with program(acts according It is asynchronous with program(acts
to the program) independent of program)
If program is re run , it occurs at the same place It depends on external condition which is

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each time independent of program being executed at

that point of time
Ex: Register overflow, divide by zero,stack Ex:Power failure,I/O transfer,I/O
overflow,invalid opcode etc., completion.elapsed time of event etc.,

Microprocessor Organization
An important aspect of computer architecture is the design of the instruction set for
the Microprocessor.
The instruction set chosen for a particular computer determines the way that machine
language programs are constructed.

Complex Instruction Set Computer(CISC):

A computer with a large number of instructions is classified as a complex instruction Set
computer.

CISC Characteristics:
Variable length instructions formats are used.
A large number of instructions—typically from 100 to 250 are provided.
Some instructions that perform specialized tasks and are used infrequently.
A large variety of addressing modes—typically from 5 to 20 are provided.
The Instructions provide direct manipulatio of operands residing in memory.

Reduced Instruction Set Computer(RISC):

Computers use fewer instructions with simple constructs so they can be executed much
faster Within the CPU without having to use memory as often.
This type of computer is classified as Reduced instruction set computer or RISC.

RISC Characteristics:
It has Relatively few instructions.
There are Relatively few addressing modes.
Memory access limited to load and store instructions.
All operations done within the registers of the CPU.
Instruction format is of Fixed-length.
Instructions easily decodable.
Instruction execution takes place in a Single clock cycle.
Hardwired control is used.
Compiler support for efficient translation of high-level language programs into
machine language programs.
A relatively large number of registers in the processor unit.
Efficient instruction pipeline.

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Comparision Between CISC and RISC prcessor organization:(Nov-2011:6-marks)

CISC RISC
Emphasis is on hardware Emphasis is on Software
It includes Multi clock complex instructions It includes single clock reduced instructions
Memory-to-memory: Register to Register:
―LOAD‖ and ―STORE‖ incorporated in ―LOAD‖ and ―STORE‖ are independent
instructions instructions
Code size is small but complex Code size is large but simple
Transistors are used for storing complex More transistors are used for memory
instructions registers
Variable length instruction formats are used Fixed length instruction formats are used
Instruction decoding is complex Instruction decoding is easy
No instruction pipelining is used It uses instruction pipelining
Large number of instructions and addressing Relatively lower number of instructions and
modes are provided addressing modes are used
Ex:VAX,IBM 370 computer Ex:Alpha,ARC,ARM,SPARC,MIPS,SuperH

Questions:

1.What is CPU?Mention its components.

Explain various addressing modes.(Nov-2012:10-Marks)
Explain the bus system organization for CPU registers with a neat diagram (Nov-2012:10-
Marks)
Explain interrupt and subroutine call. (Nov-2012:5-Marks)
Compare between CISC and RISC processor organization. (Nov-2012:5-Marks)
What is the significance of addressing modes? (Nov-2012:1-Mark)
What is recursive subroutine? (Nov-2012:1-Mark)
Explain any 3 types of data manipulation instructions with an example for each.
(Nov-2010:6-Marks)
Compare between Internal and External interrupts. (Nov-2011:5-Marks)
Write a note on condition code flags.
Explain the 3 types of CPU organization.
Explain the types of computer instructions based on number of address.
Explain program control instructions.
What is a software interrupt? Explain.
15.Explain the control word format.

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Chapter-6
Input Output Organization

I/O Subsystem
The I/O subsystem provides the mechanism for communication between the CPU and the
outside world (I/O devices).

Peripheral (or I/O Device)

Input or Output devices attached to the computer are called peripherals.

There are 3 types of peripherals

1. Input Peripherals (Devices):
The devices used to enter information and instructions into a computer for storage or
processing are called input peripherals.
An input device converts incoming data and instructions into a pattern of electrical
signals in binary code that are comphrensible to a digital computer.
Ex: Keyboard, Light Pen, Mouse, Touch Screen, Joy Stick, Digitizer, Light Pen, Scanner,
OCR, MICR, Barcode Reader.
Input devices also include sensors that provide information about their environment
(temperature, pressure, etc.,) to a computer.

2. Output Peripherals (Devices):

The devices used to deliver the processed data to a human operator are called output
peripherals.
An output device translates the digitized signals into a form understood by the user.
Ex: Printers, Monitors, Plotters, Speakers.

3. Input Output Peripherals (Devices):

The devices used to provide both input and outputs are called Input output peripherals.
Ex: Magnetic Tape, Magnetic Disk, Optical Disk, Modem, Touch Screen Display.

Input-Output Interface
Interface is a boundary across which two independent components communicate with
each other.
I/O Interface: is a special hardware component included between the CPU and
peripherals to supervise and synchronize all input and output transfers.
The purpose of the I/O interface is to resolve the differences that exist between the CPU
and peripherals.

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Peripherals CPU
Peripherals are electro mechanical devices. CPU is an electronic device

Data rate is slower Data rate is high

Uses ASCII formats for data Uses binary formats for data
The operation of peripherals is to be controlled CPU is not controlled by other devices
by the CPU

The differences between CPU and peripherals are:

Peripherals are electromechanical and electromagnetic devices and their manner of
Operation is different from the operation of the CPU and memory, which are electronic
devices. Therefore, a conversion of signal values may be required.
The data transfer rate of peripherals is usually slower than the transfer rate of the CPU
and consequently, a synchronization mechanism may be need.
Data codes and formats in peripherals differ from the word format in the CPU and
memory.
The operating modes of peripherals are different from each other and each must be
Controlled so as not to disturb the operation of other peripherals connected to the CPU.

I/O Bus and Interface Modules

I/O BUS: A communication link between the CPU and I/O peripherals.
The I/O bus consists of data lines, address lines, and control lines.

Each peripheral device has an interface unit associated with it.

The functions performed by the interface unit are as follows:
It decodes the address and control received from the I/O bus.
It interprets them for the corresponding peripheral.
It provides signals for the peripheral controller.

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It synchronizes the data flow.

It supervises the transfer of data between peripheral device and the processor.

The communication between processor and the peripheral takes place as follows:
In order to communicate with a particular device, the processor first places a device
address on the address lines.
Each interface attached to the I/O bus contains an address decoder that monitors the
address lines.
When the interface detects in own address, it activates the path between the bus lines and
the device that it controls.
All peripherals whose address does not correspond to the address in the bus are disabled
by their interface.
The processor simultaneously provides a function code (I/O command) in the control
lines.
The selected interface responds to the function code and executes it.

Function Code or I/O command

The function code or I/O command is an instruction that is executed in the interface and
its attached peripheral unit.
The interpretation of the command depends on the peripheral that the processor is
addressing.

Types of I/O command:

There are 4 types of commands. They are:
Control
Status
Data Output
Data Input

Control Command:
A control command is issued to activate the peripheral and to inform it what to do.
Ex: A magnetic tape unit may be instructed to backspace the tape by one record, to
rewind the tape, or to start the tape moving in the forward direction.

Status command
A status command is used to test various status conditions in the interface and the
peripheral.
Ex: The computer may wish to check the status of the peripheral before a transfer is
initiated.

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During the transfer, one or more errors may occur which are detected by the interface.
These errors are designated by setting bits in a status register that the processor can read
at certain intervals.

Data Output
A data output command causes the interface to respond by transferring data from the
bus into one of its registers.
Ex: with a tape unit. The computer starts the tape moving by issuing a control
command.The processor then monitors the status of the tape by means of a status
command.When the tape is in the correct position, the processor issues a data output
command.The interface responds to the address and command and transfers the
information from the data lines in the bus to its buffer register. The interface then
communicates with the tape controller and sends the data to be stored on tape.

Data Input
This command causes the interface to receive data from the peripheral and place it in the
buffer register.
When data is available (The processor checks if data are available by means of a status
command) the interface places the data on the data lines, which are accepted by the
processor.

I/O and Memory Bus

In addition to communicating with I/O, the processor must communicate with the memory unit.
Like the I/O bus, the memory bus contains data, address, and read/write control lines.

There are three ways that computer buses can be used to communicate with memory and
I/O:
Independent I/O: Use two separate buses, one for memory and the other for I/O.
Isolated I/O: Use one common bus for both memory and I/O but have separate control
lines for each.
Memory mapped I/O: Use one common bus for memory and I/O with common
control lines.

Independent I/O
In this method, the computer has independent sets of data, address, and control buses,
one for accessing memory and the other for I/O.
This is done in computers that provide a separate I/O processor (IOP) in addition to
the central processing unit (CPU).
The memory communicates with both the CPU and the IOP through a memory bus.

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The IOP communicates also with the input and output devices through a separate I/O
bus with its own address, data and control lines.
The purpose of the IOP is to provide an independent pathway for the transfer of
information between external devices and internal memory.

Isolated I/O
It uses one common bus to transfer information between memory or I/O and the
CPU.
The CPU has distinct input and output instructions, and each of these instructions is
associated with the address of an interface register.
When the CPU fetches and decodes the operation code of an input or output instruction, it
places the address of the I/O interface associated with the instruction into the common
address lines.
At the same time, it enables the I/O read (for input) or I/O write (for output) control
line.
This informs the external components that are attached to the common bus that the
address in the address lines is for an interface register and not for a memory word.
On the other hand, when the CPU is fetching an instruction or an operand from memory,
it places the memory address on the address lines and enables the memory read or
memory write control line.
So the isolated method isolates memory and I/O addresses such that memory addresses are not
affected by interface addresses as each one has its own address space.

Memory Mapped I/O

It uses one common bus to transfer information between memory or I/O and the CPU.
The same address space is used for both memory and I/O.
Only one set of read and write signals are used.
There is no distinction between memory and I/O addresses.
The interface register is considered to be a part of the memory system.
The assigned addresses for interface registers cannot be used for memory words which
reduce the memory addresses range available.
In a memory-mapped I/O organization there are no specific inputs or output instructions.
The CPU can manipulate I/O data residing in interface registers with the same
instructions that are used to manipulate memory words.
Computers with memory-mapped I/O can use memory-type instructions to access I/O
data.
It allows the computer to use the same instructions for either input-output transfers
or for memory transfers.

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Isolated I/O Memory Mapped I/O

CPU has distinct input and output and Same instructions can be used for input-
memory instructions output or memory transfers
Control signals are I/O read and I/O write Control signals are memory read and
memory write
Isolates memory and I/O addresses Same address space is used for memory and
I/O.

Asynchronous Data Transfer

The data transfer between two units may be done in two ways
1) Parallel Transmission
All the bits of data are transmitted simultaneously.

2) Serial Transmission
Data is transmitted one bit at a time one after the other.

Serial transmission can be of two types:

1) Synchronous data transfer
The data transfer takes place at regular intervals and the transmission is controlled by
clock.

2) Asynchronous data transfer

The data transfer takes place at any time.

Therefore Asynchronous data transfer between two independent units requires that control
signals be transmitted between the communicating units to indicate the time at which data is
being Transmitted.

There are different ways of doing this they are:

Strobe control
In this method a strobe pulse supplied by one of the units to indicate to the other
unit when the transfer has to occur.
A single strobe control line transmits the strobe pulse each time data transfer is
initiated.
The strobe may be activated by either the source or destination unit.

Data transfer using strobe control can be of two types:

Source(transmitting unit) initiated
Destination(receiving unit) initiated

Source initiated strobe control

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Procedure:
The source unit first places data on the data bus.
There is a brief delay to ensure that data settles to a steady value.
The source then activates the strobe pulse.
The data on the data bus and strobe pulse remain in active state for a certain period of time
The destination uses the falling edge of the strobe pulse to transfer the contents of data bus
into of its internal registers.
The source then disables the strobe pulse.
After a brief period, the source removes the data from the bus.

Destination initiated strobe control

Procedure:
The destination unit activates the strobe pulse, informing the source to provide the data.
The source unit responds by placing the requested binary information on the data bus.

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The data must be valid and be available on the bus for certain duration so that the
destination can accept it.
The destination register can be triggered by the falling edge of the strobe pulse.
The destination unit then disables the strobe.
The source removes the data from the data bus after a predetermined time interval.

Example: For a memory read operation, the strobe could be memory read control signal from
the CPU to a memory unit.The CPU (destination), indicates the read operation to inform the
memory unit (source) to place a selected word into the data bus.

Disadvantages of strobe control:

The source unit that initiates the transfer has no way of knowing whether the destination
unit actually received the data item that was placed in the bus.
The destination unit that initiates the data transfer has no way of knowing whether the
source unit has actually placed data on the bus or not.

Handshaking
Each data item being transferred can along with it have a control signal that indicates the
presence of data on the bus.
The unit receiving the data item responds with another control signal to acknowledge receipt of
the data. This type of agreement is called Handshaking.

The data transfer using handshaking can be of two types:

1) Source initiated data transfer using Handshaking

Here,
The data bus is used for carrying data that is transferred.
The two handshaking signals are:
Data valid that is generated by the source unit and
Data accepted that is generated by the destination unit.

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The timing diagram shows the exchange of signals between two units.

The 4 possible states in which the system can be set at any given time is as shown below:

Procedure:
i. The source unit initiates the data transfer process by placing the data on the data bus and
enabling its data valid signal.
The data from the bus is accepted by the destination unit.
The destination unit then activates the data accepted signal.
The source unit then disables its data valid signal which in turn removes the data on the bus.
The destination unit then disables its data accepted signal .This shows that the destination
unit is ready to accept the new data.
The system then goes into initial state.
The rate of data transfer is determined by the slowest unit.

Destination initiated data transfer using Handshaking

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The data bus is used for carrying data that is transferred.

The two handshaking signals are:
Data valid that is generated by the source unit and
Ready for data that is generated by the destination unit.

The timing diagram shows the exchange of signals between the two units.
The four possible states in which the system can be at any given time is shown below:

Procedure:
i. When the destination unit is ready to accept data, it sends the control signal ready for data
to the source unit.
The source unit then place data on the bus and sends the control signal data valid to the
destination unit.
The destination unit accepts data from the bus and then disables the ready for data control
signal.
The source unit then disables data valid signal
It then invalidates the data on the data bus.
The system then goes into the initial state.

Asynchronous Serial Transmission

In Asynchronous serial transfer, each bit of message is sent a sequence at a time, and binary
information is transferred only when it is available. When there is no information to be
transferred, line remains idle.
In this technique each character consists of three points:
i. Start bit
Character bit
Stop bi

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Start Bit- First bit, called start bit is always zero and used to indicate the beginning character.
Stop Bit- Last bit, called stop bit is always one and used to indicate end of characters. Stop bit is
always in the 1- state and frame the end of the characters to signify the idle or wait state.
Character Bit- Bits in between the start bit and the stop bit are known as character bits. The
character bits always follow the start bit.

I/O Processor

A processor with direct memory access capability that communicates with I/O devices.
The IOP is similar to a CPU except that it is designed to handle the details of I/O
processing. The IOP can fetch and execute its own instructions. IOP instructions are
specifically designed to facilitate I/O transfers.
Block diagram of
computer with
IOP

The memory unit occupies a central position and can communicate with each processor
by means of direct memory access.
The CPU is responsible for processing data needed in the solution of computation tasks.
The IOP provides a path for transfer of data between various peripheral devices and the
memory unit.

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CPU - IOP Communications

The CPU sends a test I/O instruction to IOP to test the IOP path.
The IOP path responds by inserting a status word in memory location.
The CPU refers to the status word in memory. If everything is in order, the CPU sends
the start I/O instruction to start the I/O transfer.
The IOP accesses memory for IOP program.
The CPU can now continue with another program while the IOP is busy with the
program.
Both programs refer to memory by means of DMA transfer.
When the IOP terminates the execution of its program, it sends an interrupt request to the
CPU.
The CPU then issues a read I/O instruction to read the status from the IOP.
The IOP transfers the status word to memory location.
The status word indicates whether the transfer has been completed satisfactorily or if any
error has occurred during the transfer.

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Modes Of Data Transfer

Data transfer between the central computer and I/O devices may be handled in a variety of
modes.
Data transfer to and from peripherals may be handled in one of three possible modes:
Programmed I/O
Interrupt-initiated I/O
Direct memory access (DMA)

Programmed I/O
Programmed I/O operations are the result of I/O instructions written in the computer
program. Each data item transfer is initiated by an instruction in the program.
Transferring data under program control requires constant monitoring of the
peripheral by the CPU.
Once a data transfer is initiated, the CPU is required to monitor the interface to see
when a transfer can again be made.
In the programmed I/O method, transfer from an I/O device to memory requires the
execution of several instructions by the CPU such as:
o input instruction to transfer the data from the device to the CPU, and
o a store instruction to transfer the data from the CPU to memory.
Other instructions may be needed to verify that o
The data are available from the device and
to count the numbers of words transferred.
An example of data transfer from an I/O device through an interface into the CPU is shown in
Fig.

When a byte of data is available, the device places it in the I/O bus and enables its
data valid line.
The interface accepts the byte into its data register and enables the data accepted line.
The interface sets a it in the status register that we will refer to as an F or ―flag‖ bit.
The device can now disable the data valid line, but it will not transfer another byte
until the data accepted line is disabled by the interface.

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A program is written for the computer to check the flag in the status register to
determine if a byte has been placed in the data register by the I/O device.
This is done by reading the status register into a CPU register and checking the value
of the flag bit.
If the flag is equal to 1, the CPU reads the data from the data register.
The flag bit is then cleared to 0 by either the CPU or the interface, depending on how
the interface circuits are designed.
Once the flag is cleared, the interface disables the data accepted line and the device
can then transfer the next data byte.
A flowchart of the program that must be written for the CPU is shown in Fig.

It is assumed that the device is sending a sequence of bytes that must be stored in memory.
The transfer of each byte requires three instructions:
Read the status register.
Check the status of the flag bit and branch to step 1 if not set or to step 3 if set.
Read the data register.

Direct Memory Access (DMA)

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DMA is a technique for transferring data from main memory to a device without
passing it through the CPU.
CPU is only involved at the beginning and end of the transfer and interrupted only
after entire block has been transferred.
Direct Memory Access needs a special hardware called DMA controller (DMAC)
that manages the data transfer between memory and I/O device.

DMA Controller

The unit communicates with the CPU via the data bus and control lines.
The DMA controller has three registers: an address register, a word count register, and a
control register.
Address register: contains an address to specify the desired location in memory.
Word count register: holds the number of words to be transferred.
Control register: specifies the mode of transfer
Ex: read/write, burst/stealing, I/O to memory, I/O to I/O, memory to memory etc.
The registers in the DMA are selected by the CPU through the address bus by enabling
the DS (DMA select) and RS (register select) inputs.
The RD (read) and WR (write) inputs are bidirectional.
When the BG (bus grant) input is 0, the CPU can communicate with the DMA registers
through the data bus to read from or write to the DMA registers.
When BG = 1, the CPU has relinquished the buses and the DMA can communicate
directly with the memory by specifying an address in the address bus and activating the
RD or WR control.

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The DMA communicates with the external peripheral through the request and
acknowledge lines.

DMA Transfer

The DMA is first initialized by the CPU. After that, the DMA starts and continues to transfer
data between memory and peripheral unit an entire block is transferred.

The CPU initializes the DMA by sending the following information through the data bus:
The starting address of the memory block where data are available (for read) or
Where data are to be stored (for write)
The word count, which is the number of words in the memory block
Control to specify the mode of transfer such as read or write
A control to start the DMA transfer

Then the DMA transfer continues as follows:

The peripheral device sends a DMA request to the DMA controller.
DMA controller activates the BR line, informing the CPU to relinquish the buses.
The CPU responds with its BG line, informing the DMA that its buses are disabled.
The DMA then puts the current value of its address register into the address bus,
initiates the RD or WR signal, and sends a DMA acknowledge to the peripheral
device.
When the peripheral device receives a DMA acknowledge, it puts a word in the data
bus (for write) or receives a word from the data bus (for read).
When the last word of data in the DMA transfer is transferred, the DMA controller
informs the termination of the transfer to the CPU by means of the interrupt line.

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Interrupt initiated I/O

In this the interface informs the computer when it is ready to transfer data by using
the interrupt facility.
Then the CPU takes care of the input and output transfer.
After the transfer is completed, the computer returns to the previous programs to
continue what it was doing before the interrupt.
The return address from program counter is stored into a memory stack.
Control branches to a service routine that processes the required I/O transfer.

The branch address of the service routine can be chosen in two different ways:

Vectored interrupt:
In vectored interrupt, the source that interrupts supplies the branch information to the computer.
This information is called the interrupt vector.

Non vectored interrupt

In a non vectored interrupt, the branch address is assigned to a fixed location in memory.

Priority Interrupt

A priority interrupt is a system that determines which condition is to be serviced first

when two or more requests arrive simultaneously.
Highest priority interrupts are serviced first.
Devices with high speed transfers are given high priority and slow devices such as
keyboards receive low priority.
When two devices interrupt the computer at the same time the computer services the
device, with the higher priority first.
Establishing the priority of simultaneous interrupts can be done by software or
hardware.

Software:
Polling is the software method used to identify the interrupt source having the highest
priority.
Only one branch address is used for all interrupts.
The priority of each interrupt source determines the order in which it is polled.
The source with the highest priority is tested first, and if its interrupt signal is on,
control branches to a routine that services that source.
Otherwise, the source with the next lower priority is tested, and so on.
―Polling is like picking up your phone every few seconds to see if you have a call.
…‖

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Hardware
A hardware priority interrupt unit functions as an overall manager in an interrupt
system environment.
The unit accepts interrupt requests from many sources, determines which request has
the highest priority, and issues an interrupt request to the computer based on this
determination.
To speed up the operation, each interrupt source has its own interrupt vector address
to access its own service routine directly.
The hardware priority function can be established by either a serial or parallel
connection of interrupt lines.
The serial connection is called the daisy chain method.

Daisy-Chaining Priority

In daisy chaining method all the devices are connected in serial. The device with the highest
priority is placed in the first position, followed by lower priority devices.

All devices that can request an interrupt are connected serially and in priority order with the
highest priority device placed first on the daisy chain, farthest from the CPU, and the lowest
priority device placed last and closest to the CPU.
First, any (or all) of the devices signal an interrupt on the Interrupt Request line.
Next, the CPU acknowledges the interrupt on the Interrupt Acknowledge line.
A device on the line passes the Interrupt Acknowledge signal to the next lower priority device
only if it has NOT requested service.
The first device on the priority chain requiring service asserts it interrupt vector address
(VAD) on the CPU data bus.
The CPU services the device
The Interrupt Acknowledge signal is passed to the next lower priority device and steps 2 – 6
are performed for the next lower priority device.

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Parallel Priority Interrupt

It has an interrupt register whose bits are connected to the interrupt request lines of
different devices in the system.
It also has a mask register whose bits can be used to control the status of each
interrupt request.
The mask register has the same number of bits as the interrupt register.
Each interrupt bit and its corresponding mask bit are applied to an AND gate.

Parallel Priority Interrupt Hardware

This produces the four inputs to a priority encoder.
The priority encoder generates two bits of the vector address.
This is transferred to the CPU.
Another output from the encoder sets an interrupt status flip flop IST.
The outputs of interrupt enable flip-flop IEN and IST are applied to an AND gate.
The outputs of this AND gate provide a common interrupt signal for the CPU.
The interrupt acknowledge INTACK signal from the CPU enables the bus buffers in
the output register and a vector address VAD is placed into the data bus.

Priority Encoder
The priority encoder is a circuit that implements the priority function. The logic of the
priority encoder is such that if two or more inputs arrive at the same time, the input having the
highest priority will take precedence. The truth table of a four-input priority encoder is given
below.

Inputs Outputs

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I0 I1 I2 I3 x y IST
1 x x x 0 0 1
0 1 x x 0 1 1
0 0 1 x 1 0 1

0 0 1 1 1 1
0 0 0 x x 0

= I'0I'1
= I'0I'1 + I'0I'2
(IST) = I0 + I1 + I2 +I3

The X's in the table designate don't care conditions.

Input I0 has the highest priority.
When I0 input is 1, the output generates an output xy=00.
I1 has the next priority level.
The output is 01 if I1 =1 and I0 =0.
The output for I2 is generated only if higher priority inputs are 0 and so on.
The interrupt status IST is set only when one or more inputs are equal to 1.
If all inputs are 0, IST is cleared to 0 and the other outputs of the encoder are not used, so
they are marked with don't care conditions.

Questions:
Write short notes on Isolated and memory mapped I/O (Nov-2010:3-Marks)
Explain the working of a DMA controller with a neat block diagram.(Nov-2010:8-Marks)
What is DMA? (Nov-2011:1-Mark)
Define Baud rare (Nov-2011:1-Mark)
Explain DMA transfer in a computer system? (Nov-2011:7-Marks)
What are online devices? (Nov-2012:1-Mark)
Explain Daisy chaining priority method.(Nov-2012:5-Marks)
Explain CPLI-IOP communication in detail. (Nov-2012:7-Marks)
Explain l/o bus and interface modules in a computer system. (Nov-2012:8-Marks)
Asynchronous Serial Transmission. (Nov-2012:5-Marks)
Explain programmed I/O. (Nov-2012:5-Marks)
What is polling?
Explain different types of I/O commands.
15.Explain handshaking method of asynchronous communication.
16.Explain strobe control method.
17.What are peripheral devices?

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Chapter-7
Memory Organization
Memory:
Memory is storage unit used to store data and programs in a computer.

There are two types of memory:

Main memory: It stores data and programs during execution time and its directly
communicates with the CPU.
Secondary memory/Auxiliary memory: It provides backup storage.

Memory Hierarchy:
Memory hierarchy is the combination of various storage devices arranged from fastest to
slowest of their access times.

Memory Hierarchy is to obtain the highest possible access speed while minimizing the
total cost of the memory system.
At the bottom of the hierarchy are the slow magnetic tapes used to store removable
files.
Next are the magnetic disks that are used as backup storage.
Next is the main memory that directly communicates with CPU and also with
auxiliary memory through I/O processor.

Cache Memory
The cache memory is a high speed memory that is used to compensate for the difference
in speed between main memory and CPU.
Parts of the current program and the data are copied from the main memory into the high
speed cache memory.
When the CPU refers to an instruction, it is fetched from the cache if it is already there.
The cache memory would be 5 times faster than main memory.

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Levels of Cache
There are two levels of cache:
Level 1(L1) cache: It is on the processor chip.
Level 2(L2) cache: It is external to the processor chip.

Difference between Auxiliary memory and Cache memory

Cache memory Auxiliary memory

1)Low storage capacity 1)Large storage capacity

2)Expensive 2)Inexpensive
3)Stores programs and data that are currently 3)Stores programs and data that are not
used by the CPU currently used by the CPU
4)CPU has direct access to the cache 4)CPU does not have direct access to the
Auxiliary memory
5)High access speed 5)Low access speed
6)Block size is typically 1 to 16 words 6)Block size ranges from 256 to 2048 words

Main Memory
It stores programs and data for immediate access and use by the CPU during processing.
It is in the form of semiconductor integrated circuits.
A computer with memory word length s-bits and m-bit address has a memory capacity
of
m m
2 s-bits memory words giving a memory bit capacity of 2 -1.

Ex: For a computer with word length=16 bits(s-bits)

If 12 bits (m-bits) are used to specify the address.
12 m
Then the capacity of 2 x16 (2 s-bits) memory words giving a memory
12 m
bit capacity of 2 =4096 ( 2 -1)

There are two Types of main memory

Random access memory(RAM) or Read write memory(R/W M)
Read Only Memory(ROM)

RAM
The Read and write (R/W) memory of a computer is called RAM.
The User can write information to it and read information from it.
With RAM any location can be reached in a fixed (and short) amount of time after
specifying its address.

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The RAM is a volatile memory; it means information written to it lost when the
computer is turned off.

There are two types of RAM

Static RAM
S-RAM retains stored information only as long as the power supply is on.
In SRAM, a bit of data is stored using the state of a flip-flop.
A flip-flop for a memory cell takes four or six transistors along with some wiring, but
never has to be refreshed.
However, because it has more parts, a static memory cell takes up a lot more space on
a chip than a dynamic memory cell.
Static RAM is fast and expensive
Static RAM is used to create the CPU‘s speed sensitive cache.

Dynamic RAM
Loses its stored information in a very short time (for milli sec.) even when power
supply is on.
DRAM stores a bit of data using a transistor and capacitor pair, which together
comprise a memory cell.
A capacitor is like a small bucket that is able to store electrons.
The problem with the capacitor‘s bucket is that it has a leak.
In a matter of a few milliseconds a full bucket becomes empty.
Therefore, for dynamic memory to work, either the CPU or the Memory Controller
has to come along and recharge all of the capacitors holding it before they discharge.
To do this, the memory controller reads the memory and then writes it right back.
This refresh operation happens automatically thousands of times per second.
This refresh operation is where dynamic RAM gets its name.
It takes time and slows down the memory.
D-RAM‘s are cheaper & slower.
Dynamic RAM forms the larger system RAM space.

ROM (Read only memory):

Its non volatile memory, ie, the information stored in it, is not lost even if the power
supply goes off.
It‘s used for the permanent storage of information.
It also posses random access property.
Information cannot be written into a ROM by the users/programmers.
The contents of ROMs are decided by the manufactures.

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Programs and data written into ROM permanently during manufacturer is called
firmware.

ROMs are broadly classified as:

Masked programmed: The contents are written at the time of manufacturer of IC.
They are least expensive.
User programmed: The contents can be written by the as desired by user and memory
contents can be erased later and new values can written in the ROM.

Types of user programmed ROM:

PROM:
It‘s programmable ROM.
Its contents are decided by the user.
The user can store permanent programs, data etc in a PROM.
The data is fed into it using a PROM programs.

EPROM:
An EPROM is an erasable PROM.
The stored data in EPROM‘s can be erased by exposing it to UV light for
about 20 min.
It‘s not easy to erase it because the EPROM IC has to be removed from the
computer and exposed to UV light.
The entire data is erased and not selected portions by the user. EPROM‘s are
cheap and reliable.

EEPROM (Electrically Erasable PROM) :

The chip can be erased & reprogrammed on the board easily byte by byte.
It can be erased within a few milliseconds.
There is a limit on the number of times the EEPROM‘s can be reprogrammed, i.e.;
usually around 10,000 times.
Ex: Flash ROM

RAM Chip

A RAM chip can have one or more control inputs that select the chip only when needed.
This is best suited for RAM chip communication with the CPU.
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A Bidirectional data bus is used to allow transfer of data either from memory to CPU
during read operation or from CPU to memory during write operation.
A bidirectional bus is constructed with three state buffers.
A three state buffer output can be placed in one of three possible states.
o Signal at logic 1
o Signal at logic 0
o High impedance

The high impedance state behaves like an open circuit and so the signal has no significance.
The memory capacity of RAM chip is 128 words each of 8 bits.
It has an 8 bit bi directional data bus.
The read and write inputs specify the two memory operations.

Read operation:
During read operation the CPU reads from memory by asserting READ and the address
from which to read.
The memory system responds by loading the data lines with the data stored at address
and asserts completion signal.

READ (in: Address; out: Word, completion signal)

On Entry: MAR (memory address register) contains address to be read from.
On Exit: Completion signal is true and MDR (memory data register) contains word stored at
address.

Write Operation:
The CPU writes a word into memory by first placing address in MAR and the word in
MDR.
It then asserts the WRITE signal.
After the value in MDR is stored in memory with address, contained in MAR, the
memory asserts the completion signal.

This completion signal may be any one of the following:

Done
Acknowledge
Accept
Ready

WRITE (in: Address, Word; out: Completion signal)

On Entry: MAR contains address to be written to.
On Exit: Completion signal is true.

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The operation of the RAM chip can clearly be understood by the function table.

The unit is in operation only when CS1=1 and CS2 =0

Memory is inhibited if
Chip select inputs are not enabled
Chip select inputs are enabled but read or write inputs are not enabled.

When CS1=1 and CS2 =0, the memory can be placed in a write or read mode.
When WR=1 , the memory stores a byte from the data bus into a location specified by the
address input lines.
When RD=1, the contents of the selected byte is placed into the data bus.

ROM Chip

The data bus can be only in output mode since ROM can only read.
The nine address lines in the ROM chip specify any one of 512 bytes stored in it.
The two chip select inputs must be CS1=1 and CS2 =0 for the operation.Otherwise,data
bus is in high impedence state.

There is no need for RD or WR signals.The operation by default is RD, when chip is

selected. Memory address map
It is a pictorial representation of assigned address space for each memory chip in the system.
Example: consider a computer system that needs 512 bytes of RAM and 512 bytes of ROM.

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Since each RAM chip is of 128x8 capacities, 4 RAM chips are required. (128x4=512)
Since ROM chip capacity is 512x8, only one ROM chip is required.
10 address lines are used.
The ‗X‘ indicates those lines that must be connected to the address input in each chip.
7
RAM chips have 128 bytes (2 ) and so required 7 address lines.
9
ROM chip has 512 bytes (2 ) and so required 9 address lines.

From the table:

When line A10=0, CPU selects RAM.
When line A10=1, it selects a ROM.
Lines A9 and A8 can be used to differentiate between RAM1,RAM2,RAM3,RAM4
a. With bit patterns 00,01,10,11.
Address bus lines are sub divided into groups of 4 bits each so that each group can be
represented with hexadecimal digit.
First hexadecimal digit represents lines 13 to 16 and is always 0.
The next hexadecimal digit represents lines 9 to 12 and
Lines 11 and 12 are always 0.
The range of addresses is determined from the value of address lines from all 0‘s to all
1‘s.

Connection of Memory to CPU

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RAM and ROM chips are connected to a CPU through the data and address buses
The low-order lines in the address bus select the byte within the chips and other lines in
the address bus select a particular chip through its chip select inputs.
Each RAM receives the 7 lower bits of the address bus to select one of the 128 possible
bytes.
A specific RAM chip selection can be determined from lines 8 and 9 in the address bus.
This is done with 2x4 decoder whose output is connected CS1 inputs of each RAM chip.
When
00=RAM1 is selected.
01=RAM2 is selected
10=RAM3 is selected.
11=RAM4 is selected
The RD and WR outputs from the CPU are applied to the inputs of each RAM is to
selected or ROM is to be selected.
If line
10 =0, RAM is selected.
10=1, ROM is selected.
CS1 is connected to RD control line for the ROM chip to be enabled only during read
operation.
Address line 1 to 9 are applied to input address of ROM.
RAM addresses assigned are 0 to 511.ROM addresses are assigned are 512 to 1023.

Auxiliary memory
The most common auxiliary devices used in computer systems are: Magnetic disks and tapes.

Magnetic disk

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Disks are made of magnetic material shaped as a thin circular disk and protected by
plastic cover.
A disk can store information on both the surfaces.
To increase the capacity disks are assembled into disk pack which may include many
disks and hence many surfaces.
Information is stored on a disk surface in concentric circles of small width called tracks
each having a distinct diameter.
For disk packs, the tracks with the same diameter on the various surfaces are called a
cylinder.
A track is divided into smaller blocks called sectors.
The division of track into equal sized disk blocks (sectors) is set by the Operating system
during disk formatting (initialization).
Blocks are separated by fixed size interblock gaps, which include specially coded
control information written during disk formatting.
Transfer of data between main memory and disk takes place in units of disk blocks.
The disk pack is mounted in disk drive that includes a motor that rotates the disks.
The read/write head is the actual hardware mechanism that reads/writes a block.
There are separate read /write heads used on both sides of the platter to read from or write
to disk by magnetically storing the information on the surface of the disk.
The read or write heads are mounted on arms that can move them towards the central
spindle or towards the edge.
The arms are mounted on a common actuator that moves the heads together horizontally
inwards and outwards.

The important characteristics of any auxiliary memory device are:

Access mode
Access time
Transfer rate
Capacity
Cost

Access time
It is the average time required to reach a storage location in memory and obtain its contents.

Access time=Seek time + Rotational delay (latency) +Block transfer time

Seek time
It is the time required by the disk controller to mechanically position the read/write head on the
correct track given the address of a disk block.

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Rotational delay (latency)

The time taken to rotate and position the beginning of the desired block under read/write head.
It depends on the rpm of the disk.

Block transfer time

The time required to transfer the data is called block transfer time.
Magnetic tape

Magnetic tapes are sequential access devices.

th
To access the n block on tape, the preceding n-1 blocks must be first scanned.
Data is stored on reels of high capacity magnetic tape.
A tape drive is required to read the data from or write data to a tape reel.
Bytes are stored consecutively on the tape.
Modern magnetic tape is commonly packaged in cartridges and cassettes.
The device that performs actual writing or reading of data is a tape drive.
A read/write head is used to read or write data on tape.
Data records are stored as blocks with interblock gaps.
Magnetic tapes are mainly used for backup and as medium for transferring information
from one system to another.

Associative Memory
The memory unit accessed by content is called an associative memory or content addressable
memory (CAM).
In an associative memory, when a word is written, no address is specified.
An empty unused location is used to store the word.
To read a word from associative memory, the content of the word, or part of the word, is
specified.
The memory locates all words which match specified content and marks them for reading.

Advantages:

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This is suitable for parallel searches. It is also used where search time needs to be short

Disadvantages:
This is expensive than RAM, as each cell must have storage capability and logical circuits for
matching its content with external argument

Block diagram of as associative memory is as shown below:

Argument register-It holds the external argument, which needs to be searched.

Key register -This specifies which part of the argument word needs to be compared with words
in memory. If all bits in register are 1, the entire word should be compared. Otherwise, only the
bits having k-bit set to 1 will be compared.

Match Register- This has one bit for each word in memory. The corresponding bit will be set to
1, if it is matching
Each word in memory is compared in parallel with the content of the argument register.
The word that matches the bits of the argument register set a corresponding bit in the
match register.
Those bits in the match register that have been set indicate that their corresponding words
have been matched.
A sequential access to memory for those words, whose corresponding bits in the match
register have been set, causes reading of words in memory.
The key register provides a mask choosing a particular field or key in the argument word.
Those bits in the argument that have 1‘s in their corresponding position of the key
register are compared.
Ex:
 Let the argument register A have the bit configuration 101 111100
 Let the key register K have the bit configuration 111 000000
Since K has 1‘s in three left most positions, only the three left most position bits of A are
compared with memory words.

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Let the memory word be 100 111100. Since A has 101 in these positions and memory
word has 100, there is no match.
Consider another memory to be 101 000001. Since A has 101 in the three left most
positions, and also the memory word, there is a match.

Cache Memory
Cache is a fast small memory which stores the active portions of the program and data.
The performance of the cache memory is measured in terms of a quality called ―Hit
Ratio”.
When the CPU refers to memory and finds the word in cache, it produces a hit.
If the word is not found in cache, it counts it as a miss.
The ratio of the number of hits divided by the total CPU references to memory (hits +
misses) is the hit ratio.
The hit ratios of 0.9 and higher have been reported.

The cache is placed between the CPU and main memory.

It is the faster component in the hierarchy and approaches the speed of CPU
components.
When the CPU needs to access memory, the cache is examined.
If it is found in the cache, it is read very quickly.
If it is not found in the cache, the main memory is accessed.
A block of words containing the one just accessed is then transferred from main
memory to cache memory.

For example,
A computer with cache access time of 100ns, a main memory access time of 1000ns
and a hit of 0.9 produce an average access time of 200ns.
This is a considerable improvement over a similar computer without a cache
memory, whose access time is 1000ns.
The basic characteristic of cache memory is its fast access time.
Therefore, very little or no time must be wasted when searching for words in the
cache.
―The transformation of data from main memory to cache memory is referred to as a
―Mapping Process”.”
There are three types of mapping procedures are available.
Associative Mapping
Direct Mapping
Set – Associative Mapping.

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Consider the following memory organization to show mapping procedures of the cache
memory.

The main memory can stores 32k word of 12 bits each.

The cache is capable of storing 512 of these words at any given time.
For every word stored in cache, there is a duplicate copy in main memory.
The CPU communicates with both memories
It first sends a 15 – bit address to cache.
If there is a hit, the CPU accepts the 12 bit data from cache
If there is a miss, the CPU reads the word from main memory and the
word is then transferred to cache.

Associative Mapping
The associative mapping stores both the address and content (data) of the memory word.

A CPU address of 15 bits is placed in the argument register and associative

memory is searched for a matching address.
If the address is found, the corresponding 12 bit data is read and sent to the CPU.
If no match occurs, the main memory is accessed for the word.
The address – data pair is then transferred to associative cache memory.
If the cache is full, it must be displayed, using replacement algorithm. FIFO may be
used.

Direct Mapping
The 15-bit CPU address is divided into two fields.
The 9 least significant bits constitute the index field and the remaining 6 bits form
the tag fields.
The main memory needs an address but includes both the tag and the index bits.

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The cache memory requires the index bit only i.e., 9 bits.

k n
There are 2 words in the cache memory & 2 words in the main memory.
e.g: k = 9, n = 15

The word at address zero is stored in the cache (index=000,tag=00,data=1220)

Suppose the CPU wants to read the data at address 02000.
The index address=000
So it is used to access the cache.
The two tags are compared.
The cache tag is 00 but the address tag is 02.
There is no match. (Miss)
So the main memory is accessed and the data word 5670 at that location is transferred to
the CPU.
The cache word at index 000 is then replaced with a tag of 02 and data of 5670.

Set – Associative Mapping

The disadvantage of direct mapping is that two words with the same index in their
address but with different tag values cannot reside in cache memory at the same time.
Set-Associative Mapping is an improvement over the direct-mapping in that each
word of cache can store two or more word of memory under the same index address.

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Each data word is stored together with its tag and the number of tag – data items in
one word of cache is said to form a set.
Each index address refers to two data words and their associated tags.

Each tag requires 6 bits & each data word has 12 bits, so the word length is 2(6+12)
=36 bits.
An index address of 9 bits can accommodate 512 cache words. It can accommodate
1024 memory words.
When the CPU generates a memory request, the index value of the address is used to
access the cache.
The tag field of the CPU address is compared with both tags in the cache.

Virtual Memory
Virtual memory management is a memory management technique that allows the
execution of processes that is not completely in memory.
The main advantage of this scheme is that user programs can be larger than physical
memory.
Each address referenced by the CPU goes through an address mapping from virtual
address to a physical address in main memory.
A virtual memory system provides mechanism for translating program generated
addresses into correct main memory locations.
This is done with dynamically, while programs are being executed in the CPU.
The mapping is handled automatically by means of mapping table.

Address space and memory space

Address space
The address used by a programmer to reference instructions and data is called the virtual
address.
The set of such virtual addresses is called the address space.

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Memory space
The address in main memory directly accessible for processing is called a physical
address.
The set of such physical addresses is called Memory space.
With virtual memory concept, the address space is allowed to be larger than the memory
space.

Example:
Let main memory capacity be 32K words. (32X1024=32768)
15
Physical address requires 15 bits since 32K=2
Let auxiliary memory capacity be 1M words=1024K words.
20
The address requires 20 bits as 2 =1M.
Thus auxiliary memory has a capacity for storing information equivalent to the capacity
5
of 2 =32 main memories.(20-5=5 address bits).
The address space is N=1024 K and main memory space M=32K.

Relationship between address and memory space in a virtual memory system.

Programs and data are transferred between main memory and auxiliary memory based on
the demands of CPU.
If program 1 is currently being executed then program 1and associated data will be
moved from auxiliary memory into main memory.

The diagram shows memory table for mapping a virtual address.

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Logical address is of 20 bits and physical address is of 15 bits.

A table is needed to map virtual address of 20 bits to a physical address of 15 bits.
Mapping is done dynamically as each word is referenced by CPU, the address is
translated.
Example
Let address space be 8K and memory space be 4K.
If each is split into groups of 1K words, then we will have 8 pages and 4 blocks.

Virtual address can be represented with the two numbers.

A page number address
Line within a page

The memory page table consists of 8 words, one for each page.
The address in the page denotes the page number and the content of the word gives the
block number where that page is stored in main memory.
The pages 1, 2, 5 and 6 are in main memory in blocks 3, 0, 1 and 2 respectively.
The presence bit in each location indicates whether the page has been transferred from
auxiliary memory to main memory.
If presence bit=1,
The block number read is transferred to the two high order bits of the MAR.

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The line number from the virtual address is transferred into the 10 low order bits of
the MAR.
A read signal to memory, transfers the content of the word to the main memory
buffer register to be used by the CPU.
If presence bit=0,
Then the word referenced by virtual address is not in main memory.
A call to the operating system is generated to fetch the required page from auxiliary
memory and place it into main memory before resuming computation.

Mapping table may be stored in

Separate memory
Main memory
Associative memory

Associative memory page table

So a more efficient way of organizing page table would be with associative memory
having each word in memory containing a page number together with its
corresponding block number
By this, size of memory would be reduced and each location will be fully utilized.
The page field in each word is compared with the page number in the virtual address.
If a match occurs, the word is read from memory and its corresponding block number
is extracted.

Fig: An associative memory page table

An associative memory of 4 words is used. Each entry in the associative memory

array consists of two fields of two fields.
The first three bits specify a field for storing the page number. The last two bits
constitute a field for storing the block number.
The virtual address is placed in the argument register.

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The page number bits in the argument register are compared with all page numbers in
the page filed of the associative memory.
If the page number is found the 5 bit word is read out from memory. The
corresponding block number, being in the same word, is transferred to the main
memory address register.
If no match occurs, a call to the operating system is generated to bring the required
page from auxiliary memory.

Page Replacement
When a program starts execution, one or more pages are transferred into main
memory and the page table is set to indicate their position.
The program continues executing from main memory until it attempts to reference a
page from auxiliary memory. This condition is called a page fault.
When page fault occurs, the execution of the present program is suspended until the
required page is brought into main memory.
The operating system assigns this task to the I/O processor.
Meanwhile, control is transferred to the next program in memory that is waiting to be
processed in the CPU.
When the memory block has been assigned and the transfer completed, the original
program can resume its operation.
When there is no space in main memory, it is necessary to remove a page and then
bring in a new page from auxiliary memory.
The page that is least likely to be referenced in the immediate future should be
removed.

Two commonly used replacement algorithms are:

First In First Out (FIFO)
Least Recently Used(LRU)

FIFO algorithm
The FIFO algorithm selects for replacement, the page that has been in memory for the
longest period time.
Each time a page is loaded into memory, its identification number is punished into a
FIFO stack.
FIFO will be full whenever memory has no more empty blocks.
When a new page has to be loaded, the page least recently brought in is removed.
The page to be removed is easily determined because its identification number is at
the top of the FIFO stack.
Advantage:
It is easy to implement.
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Disadvantage:
Under certain circumstances, pages are removed and loaded from memory too frequently.

LRU algorithm
It can be implemented by associating a counter with every page that is in main memory.
When a page is referenced, its associated counter is set to zero.
At the fixed interval of time, the counter associated with all page presently in memory are
incremented by 1.
The least recently used page is the page with the highest count.
The counters are often called aging registers, as their count indicates their age, that is,
how long ago their associated pages have been referenced.

Advantage:
It is more attractive because least recently used page is a better candidate for removal.

Disadvantage:
It is difficult to implement

Questions:
Write short note on address space and memory space. (Nov-2010:3-Marks)
Explain ROM with a neat block diagram and write a note on different types
Of ROM.(Nov-2010:6-Marks)
Explain associative memory with a neat diagram (Nov-2010:7-Marks)
What is the flash memory? (Nov-2011:1-Mark)
What is multiprogramming? (Nov-2011:1-Mark)
Explain FIFO page replacement algorithm. (Nov-2011:5-Marks)
Write a note on cache memory. (Nov-2011:5-Marks)
What is cache memory (Nov-2012:1-Mark)
Explain virtual memory. (Nov-2012:5-Marks)
Compare RAM and ROM. (Nov-2012:5-Marks)
Explain magnetic disk memory. (Nov-2012:5-Marks)
What is Hit Ratio?
Write a note on memory address map.
15.What is refreshing of dynamic memory.
16.Explain different types of mapping procedures used in the organization of cache memory?
17.What is page fault?

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