CHAPTER 5

8255 PPI (Programmable Peripheral

Interface)
 Interfacing I\O devices
• To make a microcomputer system the microprocessor has to connected

with memory and input/output devices.

• The technique of connection between input/output devices and the

microprocessor is known as interfacing input/output devices .

• Special attention must be always given during the connection of pins of

peripheral devices and microprocessor pins.

 Interfacing I\O devices
• Memory ICs and input/output devices are selected as per requirement
of the system and then interfaced with the microprocessor.

• Address, data and control lines are used for connecting peripherals.

• After connecting them properly, programs are embedded in to the

microprocessor.

• When a program is executed, the microprocessor communicates with

input/output devices and performs system operations.
 Steps in Interfacing an I/O Device
• Steps to interface a general I/O device with a Microprocessor:

1. Connect the data bus of the microprocessor system with the

data bus of the I/O port.
2. Derive a device address by decoding the required address and
use it as the chip select of the device.
3. Use a suitable control signal, i.e. RD* and /or WR* to carry out
operations.
• Input port
• The input device is connected to the microprocessor through buffer.

• Its input is available only when enable signal is active.

• When microprocessor wants to rad data, the control signals from the
microprocessor activates the buffer by asserting enable input of the
buffer.

• Once the buffer is enabled, data from the device is available on the
data bus.
• Output Port

• It is used to send the data to the output device such as display

from the microprocessor.

• The output device is connected to the microprocessor through

latch.

• When microprocessor wants to write data, it sends the data on the

data bus and activates the clock signal of the latch.

• It is then available at the output of latch for the output device.

• Three-State Buffers, Latches, and Transceivers
• A group of flip-flops is called n-bit register and function as a buffer, a
latch or a transceiver.
• A buffer will pass a digital bit from it input to its output unchanged
when the buffer is enabled.
• A latch remember digital data and can be used to interface the
output of a microprocessor to other devices.
• A transceiver is a bidirectional buffer, a microprocessor can receive or
send data in to \ out from an I/O device over the same set of
common lines (data bus).
I/O Interfacing Techniques
• Input/output devices can be interfaced with microprocessor systems in
two ways:
1. Memory mapped I/O
2. I/O mapped I/O
1. Memory mapped I/O
• In this type of I/O interfacing, the 8086 uses 20-bit address lines to
identify an I/O device.

• The I/O device is connected as if it is a memory device.

• The 8086 uses the same control signals and instructions to access I/O
as those of memory.
2. I/O mapped I/O:

• 8086 has special instructions IN and OUT to transfer data through the
input/output ports in I/O mapped I/O system.

• The IN instruction copies data from a port to the Accumulator.

• If an 8-bit port is read data will go to AL and
• If 16-bit port is read the data will go to AX.
• The OUT instruction copies a byte from AL or a word from AX to the
specified port.

• In this mode, address of I/O device is 8-bit for Direct addressing and 16-
bit for Indirect addressing.
Description of 8255A Internal Block Diagram
• Data Bus Buffer
• This three-state bi-directional 8-bit buffer is used to interface
the 8255 to the system data bus.
• Data is transmitted or received by the buffer upon execution of
input or output instructions by the Microprocessor.
• Control words and status information are also transferred
through the data bus buffer.
 Description of 8255A Internal Block Diagram

• Group A and Group B Controls

• Each of the Control blocks (Group A and Group B) accepts
"commands" from the MP as "control word" and configure the ports
(Port A, Port B and Port C) accordingly.
• Port A and upper 4 bits of Port C are controlled by Group A
• Port B and lower part of Port C are controlled by Group B
 Description of 8255A Internal Block Diagram

• Ports A, B, and C
• The 8255 has three 8 bit I/O ports and each one can be connected to
the physical lines of an external device.
• All can be configured to a wide variety of functional characteristics by
the system software.
• These ports are labeled as PA0-PA7 (Port A), PB0-PB7 (Port B) and
PC0-PC7 (Port C).

• GND (Ground) and Vcc

 Description of 8255A Internal Block Diagram
• Read/Write Control Logic
• The function of this block is to manage all of the internal and external
transfers of both Data and Control or Status words.

• (CS) Chip Select. Is Active "low" signal this input pin enables the
communication between the 8255 and the CPU.

• (RD) Read. Is Active "low" signal this input pin enables 8255 to send the data
or status information to the CPU on the data bus. In essence, it allows the
CPU to "read from" the 8255.

• (WR) Write. Is Active "low" signal this input pin enables the CPU to write data
or control words into the 8255.
 Description of 8255A Internal Block Diagram
• (A0 and A1) These input signals, control the selection of one of the three
ports or the control word register.
• (RESET) Reset. Is Active "high" signal this input initializes the control register
to 9Bh and all ports (A, B, C) are set to the input mode.
A0 and A1, with RD*, WR* and CS*:

CONTROL
REGISTER
• Control Word is an 8-bit data that stored in control register.
Control
Word
Register
 Bit number Functionality

D7 0

D6, D5 and D4 Don’t care

D3, D2 and D1 Individual port C

Selection
D0 Bit set = 1
Bit reset = 0
 Bit Set Reset Mode
• If bit 7 of control word is a logic 0 then 8255 will be configured as
Bit SET RESET (BSR) mode
• Only port C (PC0-PC7) can be used to set or reset its individual
port bits depending on D0 of the control word.
• Example:
• Write a control word to reset PC5.
• (Ans: 0AH) 0 0 0 0 1 0 1 0
• Write a control word to set PC2.
• (Ans: 05) 0 0 0 0 0 1 0 1

NB: Don’t Cares can be set as Zero or One, In this solution all the
don’t cares are set as zero.
So we can have another solutions in addition to the solutions
specified here.
• Example:
• Write a program to blink port C bit 0 of the 8255. assume the
address of control word register is 83H and all don’t cares are 0.
✓control word to make bit 0 high is: 01H
0 0 0 0 0 0 0 1
✓Control word to make bit 0 low is: 00H
0 0 0 0 0 0 0 0
 Input \ Output Mode
• If bit D7 of control word register is 1 then 8255 is configured as a
programmable I\O mode

• The I/O mode is further divided in to three modes:

✓Mode 0 (Simple input/output, without Handshaking)
✓Mode 1 (Handshake mode)
✓Mode 2 (Bidirectional Data Transfer)
• D6, D5 and D2 are all 0 to configure all the ports of 8255 in mode 0.
• D4, D3, D1 and D0 determine whether the corresponding ports are
Input or Output.
• No handshaking signal is required, Data is simply writing to or reading
from a specified port.
• 8255 programmable peripheral interface has 16 different configuration
in mode 0.
 Group B

Group A
• Example:
• Find the control word for the following arrangement of
8255-PPI in Mode 0.
✓Port A, port B, port CL and port CH as an Output
ports.
Solution: 80H
1 0 0 0 0 0 0 0

• Find the control word for the following of 8255-PPI in

Mode 0.
✓Port A, port B, port CL and port CH as an Input ports.
Solution: 9BH
1 0 0 0 0 0 0 0
• Handshaking Signal
• The making of inter relation between slower peripheral device and
microprocessor is called handshaking.

• Before making the inter-relation between peripheral device and

microprocessor the PPI send some signals to microprocessor and
peripheral device to perform the process.

• These signals are called handshaking signal.

• 8255-based devices that perform handshaking support following

handshaking signals:
• Input control signal
• STB* (Strobe Input): is an active Low input signal for 8255 and output
signal for the input device.

• The input device activate it to indicate the MP that, the data to be read is
already sent on the port lines of 8255 port.

• Upon activation of this signal 8255 loads the data from the input port
lines into the input buffer of that port.
• Input control signal
• IBF (Input Buffer Full F/F): is an active high output signal for 8255
and an input signal for the input device.

• This signal is generated by 8255 in response to STB* signal as an

acknowledgment to the input device.

• It also indicates to the input device that, the input buffer is full and it is
not ready to accept next data from the input device.

• Therefor, input device sends data on the port lines only when IBF signal is
not active.

• The IBF signals is deactivated when MP reads the data from input buffer
of the respective port by activation of RD* signal.
• Input control signal
• INTR (Interrupt Request): is an active high output signal
generated by 8255.
• The 8255 sets the INTR when STB* signal is 1, IBF signal is 1
and INTE is 1.
• Indicating MP that, the data form the input device is available
in the input buffer.
• INTE (Interrupt Enable): is used to enable or disable INTR
(Interrupt Request) signal.
• Output control signal
• OBF* (Output Buffer Full F/F): is an active low output signal for 8255
and input signal for the output device.

• 8255 activates this signal to indicate output device that the data is
available on the output port.

• Output device reads the data from the output port and acknowledges
8255 by ACK* signal.

• ACK* (Acknowledge Input): is an active low input signal for 8255 and
output signal for the output device.

• The output device generates this signal to indicate 8255 that, the data
from output port has been accepted.
• Interrupt signal
• INTR (Interrupt Input): is an active high output signal
generated by 8255.
• The 8255 sets the INTR when ACK* signal is 1, OBF is 1 and
INTE is 1, indicating that the output device is ready to accept
next data byte.
• It reset by the falling edge of WR* signal, immediately after
sending the data to the output port.
• The different handshake signals used are STB, IBF and INTR.

• Now the following action takes place:-

• Peripheral devices places data in the port bus and inform 8255
making STB low.

• Now input port accepts the data.

• After that IBF goes high and then STB also goes high.

• Now INTR goes high if internal INTE F/F is enabled.

• Now microprocessor is interrupted to read data or microprocessor

can read data by checking Port C.

• Once microprocessor reads data IBF goes low.

• Now Peripheral devices places next data.

• The different handshake signals used are OBF, ACK & INTR.

• ACK & OBF are handshake signals.

• Now the following action takes place.

• When Output Port is empty, microprocessor writes data in the port.

• Now OBF goes low to indicate peripheral that data is available.

• Peripheral devices accepts the data by making ACK low.

• Now OBF goes high and then ACK goes high.

• Now INTR goes high, if internal INTE F/F is set.

• Now microprocessor is interrupted to write next data or

microprocessor can write next data by checking Port C.

• Now microprocessor writes next data.

 MODE 2: BIDIRECTIONAL DATA TRANSFER
• This functional configuration provides a means for communicating with a
peripheral devices on a single 8-bit bus for both transmitting and receiving
data (bidirectional bus I\O).

• Handshaking signals are provided to maintain proper bus flow discipline in

a similar manner to MODE 0.

• Interrupt generation and enable/disable functions are also available.

• Features are:
• Used in group A only.

• One 8-bit bidirectional bus port

(port A) and a 5-bit control port
(port C).

• Both input and output are latched.

• The 5-bit control port is used for

control and status for the 8-bit
bidirectional bus port A.
Bidirectional Bus I\O Control Signals

Input Operations
• STB* (Strobe Input): a “low” on this input loads data into latch.
• IBF (Input Buffer Full F/F): a “high” on this output indicates
that data has been loaded into the input latch.
• INTR 2 (The INTR Flip-Flop Associated with IBF): controlled
by bit set/reset of PC4.
Output operations
• OBF* (Output Buffer Full): the OBF* output will go “low” to
indicate the MP has written data out to port A.
• ACK* (Acknowledge): a “low” on this input enables the tri-state
output buffer of port A to send out the data.
• Otherwise, the output buffer will be in high impedance state.
• INTE 1 (The INTE Flip-Flop Associated with OBF): controlled
by bit set/reset of PC4.
Mode 2: I\O Configuration
• Example:
• A control word is given CWR = CDH. Explain the condition of ports of
8255-PPI.
• Solution:
The binary equivalent value of control word will be:

D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 0 1 1 0 1

Since D7 = 1, I\O mode

D6 = 1 and D5 = 0, port A in mode 2
D4 = 0, port A is an output
D3 = 1, upper four bits of port C are inputs
D2 = 1, port B in mode 1
D1 = 0, port B is an output port
D0 = 0, lower four bits of port C are outputs
• Example:
• What is the Mode and I\O configuration for port A, B and C of an 8255
after its control word register is loaded with 82H.
• Solution:
Expressing the control word in binary we get:
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 1 0 = 82H
Since D7 = 1, the mode of operation I\O mode and mode of operation
ports are selected by the rest bits.
D6 and D5 = 0, port A in mode 0
D4 = 0, port A is an output
D3 = 0, upper four bits of port C are output
D2 = 0, port B in mode 0
D1 = 1, port B is an input port
D0 = 0, lower four bits of port C are output
• Example:
• What control word must be written into CWR of 8255 such that port A
is configured for bidirectional operation and port B is set up with mode
1 outputs?.
• Solution:
• To config the operating mode of 8255 as I\O mode D7 will be 1.
• Port A is setup for bidirectional operation, which is mode 2 by making
D6 = 1.
• D5-D3 are Don’t care states
• Mode 1 is selected for port B by making D2 = 1 and output operation
by making D1 = 0.
• D0 is also don’t care state
• Therefor the control word register will hold the value:
D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 0 0 1 0 0 = C4H
Example:
What is the mode and I/O configuration for ports A, B, and C of an 8255A
after its control register is loaded with 82Hex

Solution: D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 0 0 1 0 0
D0 = 0 lower 4 bits of Port C are outputs
D1 = 1 Port B are inputs
D2 = 0 mode 0 operation for both Port B and the lower 4 bits of Port C
D3 = 0 upper 4 bits of Port C are outputs
D4 = 0 Port A are outputs
D6 and D5 = 00 mode 0 operation for both Port A and the upper part Of
Port C
D7 =1 mode enable (I\O mode)
Thank You!
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