IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

Received 30 January 2023; revised 20 February 2023; accepted 10 March 2023.

Date of publication 14 March 2023; date of current version 29 May 2023.
Digital Object Identifier 10.1109/JXCDC.2023.3256981

A Full-Stack View of Probabilistic Computing

With p-Bits: Devices, Architectures,
and Algorithms
SHUVRO CHOWDHURY 1 , ANDREA GRIMALDI 2 (Graduate Student Member, IEEE),
NAVID ANJUM AADIT 1 , SHAILA NIAZI 1 , MASOUD MOHSENI 3 , SHUN KANAI 4,5 ,
HIDEO OHNO 4,5 (Life Fellow, IEEE), SHUNSUKE FUKAMI 4,5 (Member, IEEE),
LUKE THEOGARAJAN 1 , GIOVANNI FINOCCHIO 2 (Senior Member, IEEE),
SUPRIYO DATTA 6 (Life Fellow, IEEE), and KEREM Y. CAMSARI 1 (Senior Member, IEEE)
1 Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA 93106 USA
2 Department of Mathematical and Computer Sciences, Physical Sciences and Earth Sciences,
University of Messina, 98166 Messina, Italy
3 Google Quantum AI, Venice, CA 90291 USA
4 Research Institute of Electrical Communication, Tohoku University, Sendai 980-8577, Japan
5 Center for Science and Innovation in Spintronics, Tohoku University, Sendai 980-8577, Japan
6 Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907 USA

CORRESPONDING AUTHOR: S. CHOWDHURY ([email protected])

This work was supported in part by the U.S. National Science Foundation under Grant CCF 2106260, in part by the Office of Naval
Research Young Investigator Grant, and in part by the Semiconductor Research Corporation. The work of Shun Kanai was supported
by the Japan Science and Technology Agency (JST)-PRESTO under Grant JPMJPR21B2. The work of Shunsuke Fukami was supported in
part by JST-CREST under Grant JPMJCR19K3 and in part by MEXT Initiative to Establish Next-generation Novel Integrated Circuits Centers
(X-NICS) under Grant JPJ011438. The work of Andrea Grimaldi and Giovanni Finocchio was supported in part by ‘‘The Italian Factory of
Micromagnetic Modeling and Spintronics’’ funded by the Italian Ministry of University and Research (MUR) under Project PRIN
2020LWPKH7, and in part by the Petaspin Association (www.petaspin.com).

ABSTRACT The transistor celebrated its 75th birthday in 2022. The continued scaling of the transistor
defined by Moore’s law continues, albeit at a slower pace. Meanwhile, computing demands and energy
consumption required by modern artificial intelligence (AI) algorithms have skyrocketed. As an alternative
to scaling transistors for general-purpose computing, the integration of transistors with unconventional
technologies has emerged as a promising path for domain-specific computing. In this article, we provide
a full-stack review of probabilistic computing with p-bits as a representative example of the energy-efficient
and domain-specific computing movement. We argue that p-bits could be used to build energy-efficient
probabilistic systems, tailored for probabilistic algorithms and applications. From hardware, architecture,
and algorithmic perspectives, we outline the main applications of probabilistic computers ranging from prob-
abilistic machine learning (ML) and AI to combinatorial optimization and quantum simulation. Combining
emerging nanodevices with the existing CMOS ecosystem will lead to probabilistic computers with orders of
magnitude improvements in energy efficiency and probabilistic sampling, potentially unlocking previously
unexplored regimes for powerful probabilistic algorithms.

INDEX TERMS Artificial intelligence (AI), combinatorial optimization, domain-specific hardware,

machine learning (ML), p-bits, p-computers, quantum simulation, sampling, spintronics, stochastic magnetic
tunnel junctions (sMTJs).

I. INTRODUCTION The widespread implementation of AI, particularly in indus-

T HE slowing down of the Moore era of electronics has

coincided with the recent revolution in machine-learning
(ML) and artificial intelligence (AI) algorithms. In the
tries such as autonomous vehicles [2], is an indication that
the energy crisis caused by large-scale ML models is not just
a data center problem, but a global concern.
absence of steady transistor scaling and energy improve- Efforts of extending the Moore era of electron-
ments, training and maintaining large-scale ML models in ics by improving conventional transistor technology
data centers have become a significant energy concern [1]. continue vigorously. Examples of this approach include

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 IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

3-D heterogeneous integration, 2-D materials for transis- III. FUNDAMENTALS OF p-COMPUTING
tors and interconnects [3], new transistor physics via neg- A large family of problems (see Fig. 2) can be encoded
ative capacitance [4], [5], or entirely new approaches to coupled p-bits evolving according to the following
using spintronic and magnetoelectric phenomena to build equations [12]:
energy-efficient switches [6], [7]. mi = sign tanh(β Ii ) − r[−1,+1]
 
(1)
A complementary approach to extending Moore’s law is X
to augment the existing CMOS ecosystem with emerging, Ii = Wij mj + hi (2)
nonsilicon nanotechnologies [8], [9]. One way to achieve j
this goal is through heterogeneous CMOS + X architectures,
where mi is defined as a bipolar variable (mi ∈ {−1, +1}),
where X stands for a CMOS-compatible nanotechnology.
r is a uniform random number drawn from the interval
For example, X can be magnetic, ferroelectric, memristive,
[−1, 1], [W ] is the coupling matrix between the p-bits, β is
or photonic systems. We also discuss an example of this
the inverse temperature, and {h} is the bias vector. In physical
complementary approach, the combination of CMOS with
implementations, it is often more convenient to represent
magnetic memory technology, purposefully modified to build
p-bits as binary variables, si ∈ {0, 1}. A straightforward
probabilistic computers.
conversion of (1) and (2) is possible using the standard trans-
formation, m → 2 s − 1 [18].
As stated, (1) and (2) do not place any restrictions on
[W ], which may be a symmetric or asymmetric matrix. If an
updated order of p-bits is specified, these equations take the
coupled p-bit system to a well-defined steady-state distri-
bution defined by the eigenvector (with eigenvalue +1) of
the corresponding Markov matrix [12]. Indeed, in the case
of Bayesian (belief) networks defined by a directed graph,
updating the p-bits from parent nodes to child nodes takes
FIGURE 1. Bit, p-bit, and qubit. Each column shows a schematic the system to a steady-state distribution corresponding to that
representation of the basic computational units of classical obtained from Bayes’ theorem [19].
computing (left), probabilistic computing (middle), and quantum
If the [W ] matrix is symmetric, one can define an energy,
computing (right). These are, respectively, the bit, the p-bit, and
the qubit.
E, whose negated partial derivative with respect to p-bit mi
gives rise to (2)
II. FULL-STACK VIEW AND ORGANIZATION  
Research on probabilistic computing with p-bits originated X X
E(m1 , m2 , . . . , ) = −  Wij mi mj + hi mi  . (3)
at the device and physics level, first with stable nanomag-
i<j i
nets [10], followed by low-barrier nanomagnets [11], [12].
In [12], the p-bit was formally defined as a binary stochastic In this case, the steady-state distribution of the network is
neuron realized in hardware. In both approaches with sta- described by [20]
ble and unstable nanomagnets, the basic idea is to exploit
the natural mapping between the intrinsically noisy physics 1
pi = exp (−βEi ) (4)
of nanomagnets to the mathematics of general probabilistic Z
algorithms [e.g., Monte Carlo, Markov Chain Monte Carlo also known as the Boltzmann law. As such, iterating a net-
(MCMC)]. Such a notion of natural computing where physics work of p-bits described by (1) and (2) eventually approx-
is matched to computation was clearly laid out by Feynman imates the Boltzmann distribution which can be useful for
[13] in his celebrated Simulating Physics with Computers probabilistic sampling and optimization. The approximate
talk. Subsequent work on p-bits defined it as an abstrac- sampling avoids the intractable problem of exactly calcu-
tion between bits and qubits (see Fig. 1) with the possi- lating Z . Remarkably, for such undirected networks, the
bility of different physical implementations. In addition to steady-state distribution is invariant with respect to the update
searching for energy-efficient realizations of single devices, order of p-bits, as long as connected p-bits are not updated
p-bit research has extended to finding efficient architec- at the same time (more on this later). This feature is highly
tures (through massive parallelization, sparsification [14], reminiscent of natural systems where asynchronous dynam-
and pipelining [15]) along with the identification of promis- ics make parallel updates highly unlikely and the update
ing application domains. This full-stack research program order does not change the equilibrium distribution. Indeed,
covering hardware, architecture, algorithms, and applications this gives the hardware implementation of asynchronous net-
is similar to the related field of quantum computation where works of p-bits massive parallelism and flexibility in design.
a large degree of interdisciplinary expertise is required to The energy functional defined by (3) is often the starting
move the field forward (see the related reviews [16], [17]). point of discussions in the related field of Ising machines [21],
The purpose of this article is to serve as a consolidated sum- [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32],
mary of recent developments with new results in hardware, [33], [34], [35], [36], [37], [38], [39], [40], [41], [42], [43]
architectures, and algorithms. We provide concrete and pre- with different implementations (see [44] for a comprehensive
viously unpublished examples of ML and AI, combinatorial review). In the case of p-bits, however, we view (1) and (2)
optimization, and quantum simulation with p-bits (see Fig. 2). more fundamental than (3) because the former can also be

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Chowdhury et al.: Full-Stack View of Probabilistic Computing With p-Bits: Devices, Architectures, and Algorithms

FIGURE 2. Applications of probabilistic computing. Potential applications of p-bits are illustrated. The list broadly includes problems
in combinatorial optimization, probabilistic ML, and quantum simulation.

used to approximate hard inference on directed networks, They also serve a useful purpose to illustrate why analog
while the latter always relies on undirected networks. Com- or mixed-signal implementations of p-bits with nanodevices
pared to undirected networks using Ising machines, work on are necessary. Even using some of the most advanced field
directed neural networks for Bayesian inference has been programmable gate arrays (FPGAs), the footprint of a digi-
relatively scarce, although there are exciting developments tal p-bit is very large: Synthesizing such digital p-bits with
[19], [45], [46], [47], [48], [49], [50]. PRNGs of varying quality of randomness results in tens of
Finally, the form of (3) restricts the type of interac- thousands of individual transistors. In single FPGAs that do
tions between p-bits to a linear one since the energy is not use time-division multiplexing of p-bits or off-chip mem-
quadratic. Even though higher-order interactions (k-local) ory, only about 10 000–20 000 p-bits with 100 000 weights
between p-bits are possible [18] (also discussed in the (sparse graphs with degree 5–10) fit, even within high-end
context of Ising machines [51], [52]), such higher-order devices [14].
interactions can always be constructed by combining a stan- On the other hand, using nanodevices such as CMOS-
dard probabilistic gate set at the cost of extra p-bits. In our compatible stochastic magnetic tunnel junctions (sMTJs),
view, in the case of electronic implementation with scalable millions of p-bits can be accommodated in single cores
p-bits, trading an increased number of p-bits for simplified due to the scalability achieved by the magnetoresistive
interconnect complexity is almost always favorable. That random access memory (MRAM) technology, exceeding
being said, algorithmic advantages and the better represen- 1-Gb MRAM chips [56], [57]. However, before the stable
tative capabilities of higher-order interactions are actively MTJs can be controllably made stochastic, challenges at
being explored [51], [53]. the material and device level must be addressed [58], [59]
with careful magnet designs [60], [61], [62]. Different fla-
IV. HARDWARE: PHYSICAL IMPLEMENTATION OF vors of magnetic p-bits exist [63], [64], [65], [66], for a
p-BITS recent review (see [67]). Unlike synchronous or trial-based
A. p-BITS stochasticity (see [68]) that requires continuous resetting,
The p-bit defined in (1) describes a tunable and discrete ran- the temporal noise of low-barrier nanomagnets makes them
dom number generator. Its physical implementation includes ideally suited to build autonomous, physics-inspired prob-
a broad range of options from noisy materials to ana- abilistic computers, providing a constant stream of tunably
log and digital CMOS (see Fig. 3). The digital CMOS random bits [69]. Following earlier theoretical predictions
implementations of p-bits often consist of a pseudoran- [70], [71], [72], recent breakthroughs in low-barrier mag-
dom number generator (PRNG) (r), a lookup table for the nets have shown great promise, using stochastic MTJs with
activation function (tanh), and a threshold to generate a one- in-plane anisotropy where fluctuations can be of the order
bit output. Digital input with a specified fixed point precision of nanoseconds [73], [74], [75]. Such near-zero barrier nano-
(e.g., ten bits with one sign, six integers, and three fractional) magnets should be more tolerant to device variations because
provides tunability through the activation function. Digital when the energy-barrier 1 is low, the usual exponential
p-bits have been very useful in prototyping probabilistic dependence of fluctuations is much less pronounced. These
computers up to tens of thousands of p-bits [14], [54], [55]. stochastic MTJs may be used in electrical circuits with a few
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B. SYNAPSE
The second central part of the p-computer architecture is the
synapse, denoted by (2). Much like the hardware p-bit, there
are several different implementations of synapses ranging
from digital CMOS, analog/mixed-signal CMOS, as well as
resistive [85] or capacitors crossbars [86], [87]. The synap-
tic equation looks like the traditional matrix–vector prod-
uct (MVP) commonly used in ML models today, however,
there is a crucial difference, thanks to the discrete p-bit
output (0 or 1), the MVP operation is simply an addi-
tion over the active neighbors of a given p-bit. This makes
the synaptic operation simpler than continuous multiplica-
tion and significantly simplifies digital synapses. In ana-
log implementations, the use of in-memory computing
techniques through charge accumulation could be useful
with the added simplification of digital outputs of p-bits
[88], [89].
It is important to note how the p-bit and the neuron for
eventually integrated p-bit applications can be mixed and
FIGURE 3. Different hardware options for building a probabilistic matched, as an example of creatively combining these pieces
computer. Top: Various magnetic implementations of a p-bit. (see the FPGA-stochastic MTJ combination reported in [77]).
These include both digital (CMOS) and mixed-signal The best combination of scalable p-bits and synapses may
implementations (based on, e.g., sMTJ with low-barrier lead to energy-efficient and large-scale p-computers. At this
magnets). Bottom: Hybrid of classical and probabilistic
time, various possibilities exist with different technological
computing schemes is shown where the classical computer
generates weights and programs the probabilistic computer.
maturity.
The probabilistic computer then generates samples accordingly
with high throughput and sends them back to the classical V. ARCHITECTURE CONSIDERATIONS
computer for further processing. Like the building blocks of A. GIBBS SAMPLING WITH p-BITS
p-bits, the synapse of the probabilistic computer can be
The dynamical evolution of (1) and (2) relies on an iterated
designed in several ways, including digital, analog, and a mix of
both techniques. updating scheme where each p-bit is updated one after the
other based on a predefined (or random) update order. This
iterative scheme is called Gibbs sampling [90], [91]. Virtually
all applications discussed in Fig. 2 benefit from accelerating
additional transistors (see Fig. 3) to build hardware p-bits. Gibbs sampling, attesting to its generality.
Two flavors of stochastic MTJ-based p-bits were proposed In a standard implementation of Gibbs sampling in a syn-
in [12] (spin orbit torque (SOT)-based) and in [70] (spin chronous system, p-bits will be updated one by one at every
transfer torque (STT)-based). Both these p-bits have now clock cycle as shown in Fig. 4(a). It is crucial to ensure that
been experimentally demonstrated in [18], [76], and [77] the effective input each p-bit receives through (2) is computed
(STT) and in [78] (SOT). While many other implementations before the p-bit updates. As such, Tclk has to be longer than
of p-bits are possible, from molecular nanomagnets [79] to the time it takes to compute (2). In this setting, a graph with
diffusive memristors [80], resistive random access memory N p-bits will require N clock cycles (NTclk ) to perform a
(RRAM) [81], perovskite nickelates [82], and others, two complete sweep, where Tclk is the clock period. This require-
additional advantages of the MRAM-based p-bits are the ment makes Gibbs sampling a fundamentally serial and slow
proven manufacturability (up to billion-bit densities) and process.
the amplification of room-temperature noise. Even with the A much more effective approach is possible by the fol-
thermal energy of kT in the environment, magnetic switching lowing observation: even though updates between connected
causes large resistance fluctuations in MTJs, creating hun- p-bits need to be sequential, if two p-bits are not directly
dreds of millivolts of change in resistive dividers [70]. Typical connected, updating one of them does not directly change the
noise on resistors (or memristors) is limited by the (kT /C)1/2 input of the other through (2). Such p-bits can be updated
limit which is far lower (millivolts) even at extremely low in parallel without any approximation. Indeed, one motiva-
capacitances (C). This feature of stochastic MTJs ensures tion of designing restricted Boltzmann machines (RBMs;
that they do not require explicit amplifiers [83] at each p-bit, see [92]) over unrestricted BMs is to exploit this paral-
which can become prohibitively expensive in terms of area lelism: RBMs consist of separate layers (bipartite) that can be
and power consumption. Estimates of sMTJs-based p-bits updated in parallel. However, this idea can be taken further.
suggest that they can create a random bit using 2 fJ per If the underlying graph is sparse, it is often easy to split it into
operation [18]. Recently, a CMOS-compatible single-photon disconnected chunks by coloring the graph using a few colors.
avalanche diode-based implementation of p-bits showed sim- Even though finding the minimum number of colors is an
ilar, amplifier-free operation [84] and the search for the most NP-hard problem [93], heuristic coloring algorithms (such as
scalable, energy-efficient hardware p-bit using alternative Dsatur [94]) with polynomial complexity can color the graph
phenomena continues. very quickly, without necessarily finding a minimum. In this

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FIGURE 4. Architectures of p-computer. (a) Synchronous Gibbs: all p-bits are updated sequentially. N p-bits need N clock cycles
(NTclk ) to perform a complete sweep, Tclk being the clock period. (b) Pseudo-asynchronous Gibbs: a sparse network can be colored
into a few disjoint blocks where connected p-bits are assigned a different color. Phase-shifted clocks update the color blocks one
after the other. N p-bits need ≈ one clock cycle Tclk to perform a complete sweep, reducing O(N) complexity of a sweep to O(1), where
we assume the number of colors c ≪ N. (c) Truly asynchronous Gibbs: a hardware p-bit (e.g., a stochastic MTJ-based p-bit) provides
an asynchronous and random clock with period ⟨Tp-bit ⟩. N p-bits need approximately one clock to perform a complete sweep, as long
as synapse time is less than the clock on average. No graph coloring or engineered phase shifting is required.

context, obtaining the minimum coloring is not critical, and avoided with careful phase-shifting [98]. The main appeal
sparse graphs typically require a few colors. of the truly asynchronous Gibbs sampling is the lack of any
Such an approach was taken on sparse graphs (with no graph coloring and phase shift engineering while retaining
regular structure) to design a massively parallel implemen- the same massive parallelism as N p-bits requires approx-
tation of Gibbs sampling in [14] [see Fig. 4(b)]. Connected imately a single ⟨Tp-bit ⟩ to complete a sweep. Given that
p-bits are assigned a different color, and unconnected p-bits the FPGA-based p-computers already provide about a 10×
are assigned the same color. Equally phase-shifted and same- improvement in sampling throughput to optimized TPU and
frequency clocks update the p-bits in each color block one GPUs [14], such asynchronous systems are promising in
by one. In this approach, a graph with N p-bits requires terms of scalability. Stochastic MTJ-based p-bits should be
only one clock cycle (Tclk ) to perform a complete sweep, able to reach high densities on a single chip. Around 20 W
reducing O(N ) complexity for a full sweep to O(1), assuming of projected power consumption can be reached considering
the number of colors is much less than N . Therefore, the key 20-µW p-bit/synapse combinations at 1M p-bit density [54],
advantage of this approach is that the p-computer becomes [60], [99]. The ultimate scalability of magnetic p-bits is a
faster with larger graphs since probabilistic ‘‘flips per sec- significant advantage over alternative approaches based on
ond,’’ a key metric measured by tensor processing unit (TPU) electronic or photonic devices.
and GPU implementations [95], [96] linearly increases with
the number of p-bits. It is important to note that these TPU
and GPU implementations also solve Ising problems in sparse B. SPARSIFICATION
graphs, however, their graph degrees are usually restricted Both the pseudo-asynchronous and the truly asynchronous
to 4 or 6, unlike more irregular and higher degree graphs parallelisms require sparse graphs to work well. The first
implemented in [14]. problem is the number of colors: if the graph is dense,
We term this graph-colored architecture the pseudo- it requires a lot of colors, making the architecture very similar
asynchronous Gibbs because while it is technically syn- to the standard serial Gibbs sampling.
chronized to out-of-phase clocks, it embodies elements of The second problem with a dense graph is the synapse time
the truly asynchronous architecture we discuss next. While tsynapse . If many p-bits have a lot of neighbors, the synapse
graph coloring algorithmically increases sampling rates by unit needs to compute a large sum before the next update.
a factor of N , it still requires a careful design of out-of- If the time between two consecutive updates is ⟨Tp-bit ⟩,
phase clocks. A much more radical approach is to design it requires tsynapse ≪ ⟨Tp-bit ⟩ to avoid information loss and
a truly asynchronous Gibbs sampler as shown in Fig. 4(c). reach the correct steady-state distribution [54], [101].
Here, the idea is to have hardware building blocks with However, if the graph is sparse, each p-bit has fewer con-
naturally asynchronous dynamics, such as an sMTJ-based nections, and the updates can be faster without any dropped
p-bit. In such a p-bit, there exists a natural ‘‘clock,’’ ⟨Tp-bit ⟩, messages. Any graph can be sparsified using the tech-
defined by the average lifetime of a Poisson process [97]. nique proposed in [14], similar in spirit to the minor-graph
As long as ⟨Tp-bit ⟩ is not faster than the average synapse time embedding (MGE) approach pioneered by D-Wave [102],
(tsynapse ) to calculate (2), the network still updates N spins in even though the objective here is to not find an embedding
a single ⟨Tp-bit ⟩ timescale. This is because the probability of but to sparsify an existing graph. The key idea is to split p-bits
simultaneous updates is extremely low in a Poisson process into different copies, using ferromagnetic COPY gates. These
and further reduced in highly sparse graphs. p-bits distribute the original connections among them, result-
In fact, preliminary experiments implementing such truly ing in identical copies with fewer connections. An important
asynchronous p-bits with ring-oscillator activated clocks point is that the ground state of the original graph remains
show that despite making occasional parallel updates, the unchanged [14], so the method does not involve approxi-
asynchronous p-computer performs similarly compared to mations, unlike other sparsification techniques, for example,
the pseudo-asynchronous system where incorrect updates are based on low-rank approximations [103].

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Fig. 6. In Fig. 6, the steps of the invertible logic encoding of

three combinatorial optimization problems, maximum satis-
fiability (left column), number partitioning (middle column),
and knapsack (right column), are shown. First, each problem
is formalized into a tight mathematical formulation (top row).
Next, the problem is mapped into an invertible Boolean logic
circuit (central row), meaning that each logic gate can be
operated using any terminals as input–output nodes (similar
to those discussed in the context of quantum annealing [105],
[106] and memcomputing [107], [108]). Finally, the proba-
bilistic circuit is algorithmically encoded into an Ising model
(bottom row). Each logic gate has several Ising encodings
that map the energy landscape of its logic operator. After
the Boolean logic formulation of a problem, this step can
be automated in standardized synthesis tools. The overall
approach results in relatively sparse circuits, as illustrated
in the bottom row of Fig. 6, where all three problems show
FIGURE 5. (a) Original graph of a 3SAT instance uf20-01.cnf [100] similarly sparse matrices [W ], with bias vectors {h} shown
having 112 p-bits and a graph density of 6.99%. (Graph density, under.
ρ = 2|E|/(|V |2 − |V |), where |E| is the number of edges and |V | The key advantage of this approach, compared to heuristic
is the number of vertices in the graph.) Some of the p-bits have and dense formulations of [104], is due to the generality of
many local neighbors up to 101 neighbors as shown in the Boolean logic, quite similar to how present-day digital VLSI
histogram that slows down the synapse and the p-bits need to
circuits are constructed in sparse, hardware-aware networks
update slowly. (b) Sparsified graph of the same instance having
410 p-bits. COPY gates are inserted between each pair of copies
using billions of transistors. As such, much of the existing
of the same p-bits (COPY edges are highlighted in orange). The ecosystem of high-level synthesis can be directly used to
graph has a density of 0.95% and the maximum number of find invertible logic-based encodings for general optimiza-
neighbors is limited to 4. The synapse operations are now tion problems.
faster and hence the p-bits can be updated faster. Even though
the example shown here starts from a low-density graph, the B. MACHINE LEARNING: ENERGY-BASED MODELS
sparsification algorithm we give is general and applicable to Energy-efficient ML with BMs is a promising application for
any graph. probabilistic computers with a recent experimental demon-
stration in [76]. Mainstream ML algorithms are designed and
Fig. 5(a) shows an example of this process where the chosen with CPU implementation in mind and hence some
original graph of a satisfiability (3SAT) instance has been models are heavily preferred over others even though they are
sparsified as shown in Fig. 5(b). Irrespective of the input often less powerful. For example, the use of RBMs over the
graph size, a sparsified graph has fewer connections locally more powerful unrestricted or deep BMs is motivated by the
and thus the neurons hardly ever need to be slowed down. former’s efficient software implementation in synchronous
One disadvantage of this technique is the increased number of systems. However, by exploiting the technique of sparsity
p-bits; however, the reduced synapse complexity and the pos- and massively parallel architecture described earlier, fast
sibility of massive parallelization outweigh the costs incurred Gibbs sampling with deep Boltzmann machines (DBMs) can
by additional p-bits, which we consider to be cheap in scaled, dramatically improve state-of-the-art ML applications like
nanodevice-based implementations. visual object recognition and generation, speech recognition,
autonomous driving, and many more [109]. Here, we present
VI. ALGORITHMS AND APPLICATIONS an example where a sparse DBM is trained with MNIST
A. COMBINATORIAL OPTIMIZATION VIA INVERTIBLE handwritten digits (see Fig. 7). We randomly distribute the
LOGIC visible and hidden units on the sparse DBM with massively
When using the Ising model to solve an optimization prob- parallel pseudo-asynchronous architecture that yields multi-
lem, the first step is to provide a mapping between the Ising ple hidden layers as shown in Fig. 7(c).
model and the problem to be solved. Early work on quantum Contrasting with earlier unconventional computing
annealing stimulated by D-Wave’s quantum annealers gen- approaches where the MNIST dataset is reduced to much
erated a significant amount of useful research in this area smaller sizes [110], [111], we show how the full MNIST
[104], some of which are being adopted by quantum-inspired dataset (60 000 images and no downsampling) can be trained
classical annealers. There are usually many different ways to using p-computers in FPGAs. We use 1200 mini-batches
find a mapping, for example, some strategies may employ having 50 images in each batch to train the network using
more nodes than others to encode the same instance, while the contrastive divergence (CD) algorithm. The process
others might result in graphs with topology unsuited to the of learning is accomplished using a hybrid probabilistic
computational architecture of choice. In this context, the and classical computer setup. The classical computer com-
invertible logic approach introduced in [12] stands out for its putes the gradients and generates new weights, while the
flexibility and sparse encodings. p-computer generates samples according to those weights
The process of mapping an instance into an Ising model [see Fig. 7(b)]. During the positive phase of sampling, the
can be broadly summarized into three steps, as illustrated by p-computer operates in its clamped condition under the direct

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FIGURE 6. Invertible logic encoding. The encoding process of three optimization problems—(a) maximum satisfiability problem, (b)
number partitioning, and (c) knapsack problem—is streamlined and visually summarized into three steps: (1) problem first has to be
condensed into a concise mathematical formulation; then, (2) invertible Boolean circuit that topologically maps the problem is
conceived; finally, (3) invertible Boolean circuit is converted into an Ising model using probabilistic and/or/not gates [14].

influence of the training samples. In the negative phase, the

p-computer is allowed to run freely without any environ-
mental input. After training, the deep network not only can
classify images, but also generate images. For any given
label, the network can create a new sample (not present in
the training set) [see Fig. 7(d)]. This is an important feature
of energy-based models and is commonly demonstrated with
diffusion models [112].

C. QUANTUM SIMULATION
One primary motivation for building quantum computers is
to simulate large quantum many-body systems and under-
stand the exotic physics offered by them [113]. Two major
challenges with quantum computers are the necessity of
using cryogenic operating temperatures and the vulnera-
bility to noise, rendering quantum computers impractical,
especially considering practical overheads [114]. Simu-
lating these systems with classical computers is often
extremely time-consuming and mostly limited to small sys-
tems. One potential application of p-bits is to provide a
room-temperature solution to boost the simulation speed and
potentially enable the simulation of large-scale quantum sys-
tems. Significant progress has been made toward this end in
recent years.

1) SIMULATING QUANTUM SYSTEMS WITH

TROTTERIZATION
One approach is to build a p-computer enabling the scal-
FIGURE 7. Generative neural networks with p-bits. (a) Hybrid
able simulation of sign-problem-free quantum systems by computing scheme with a probabilistic computer and a
accelerating standard Quantum Monte Carlo (QMC) tech- classical computer is demonstrated where the probabilistic
niques [115]. The basic idea is to replace the qubits in the computer generates samples according to the weights given by
original lattice with hardware p-bits and replicate the new the CPU with a sampling speed of around 100 flips/ns.
lattice according to the Suzuki–Trotter transformation [116]. (b) Overview of the learning procedure for the hybrid setup.
Receiving the samples from the probabilistic computer, the
Recently, the convergence time of a 2-D square-octagonal
CPU computes the gradient, updates the weights and biases,
qubit lattice initially prepared in a topologically obstructed and sends them back to the probabilistic computer until
state was compared among a CPU, a physical quantum converged. (c) Sparse DBM is utilized here as a hardware-aware
annealer [117], and a p-computer (both digital and analog) graph that can be represented with multiple hidden layers of
[118]. For this particular problem, it was shown that an p-bits. Both interlayer and intralayer connections are allowed
between visible and hidden units. (d) Images shown here are
FPGA-based p-computer emulator can be around 1000 times
generated with a sparse DBM of 4264 p-bits after training the
faster than an optimized C++ (CPU) program. Based on network with full MNIST. The label p-bits are clamped to a
SPICE simulations of a small p-computer, we project that specific image and the network evolves to that image by
significant further acceleration should be possible with a annealing the system from β = 0 to β = 5 with a step size
truly asynchronous implementation. Probabilistic computers of 0.125.

VOLUME 9, NO. 1, JUNE 2023 7

 IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

FIGURE 8. ML quantum systems with p-bits. (a) Heisenberg Hamiltonian with a transverse field (0 = + 1) is applied to an FM coupled
(JZ = + 1 and Jxy = + 0.5) linear chain of 12 qubits with periodic boundary. (b) To obtain the ground state of this quantum system,
an RBM is employed with 12 visible and 48 hidden nodes, where all nodes in the visible layer are connected to all nodes in the hidden
layer. (c) This ML model is then embedded into a hardware-amenable sparse p-bit network arranged in a chimera graph using MGE.
We use a coupling strength of 1.0 among the replicated visible and hidden nodes in the embedded p-bit network. (d) Overview of the
ML algorithm and the division of workload between the probabilistic and classical computers in a hybrid setting is shown. (e) FPGA
emulation of this probabilistic computer performs variational ML in tandem with a classical computer, converging to the
quantum (exact) result as shown.

can be used for quantum Hamiltonians beyond the usual Hamiltonian. Emulating this variational ML approach with
Transverse Field Ising Model, such as the antiferromagnetic p-bits requires a few more steps. An RBM network contains
Heisenberg Hamiltonian [119] and even for the emulation of all-to-all connections between the visible and hidden layers
gate-based quantum computers [120]. However, for generic which are not conducive for scalable p-computers because
Hamiltonians (e.g., random circuit sampling), the number of of the large fan-out demanded by the all-to-all connectivity.
samples required in naive implementations seems to grow An alternative is to map the RBM onto a sparse graph through
exponentially [120] due to the notorious sign-problem [121]. MGE [102]. Using a hybrid setup with fast sampling in a
However, clever basis transformations [122] might mitigate probabilistic computer coupled with a classical computer, the
iterative process of sampling and weight updating can then be
or cure the sign problem [123] in the future.
performed. The key advantage of having a massively parallel
and fast sampler is the selection of higher-quality states of
2) MACHINE-LEARNING QUANTUM MANY-BODY the wave function to update the variational guess. Fig. 8
SYSTEMS shows an example simulation of how a p-computer learns the
With the great success of ML and AI algorithms, training ground state of a 1-D FM Heisenberg model. The scaling of
stochastic neural networks (such as BMs) to approximately p-computers using magnetic p-bits may allow much larger
solve the quantum many-body problem starting from a vari- implementations of quantum systems in the future.
ational guess has generated great excitement [124], [125],
[126] and is considered to be a fruitful combination of quan-
D. OUTLOOK: ALGORITHMS AND APPLICATIONS
tum physics and ML [127]. These algorithms are typically
BEYOND
implemented in high-level software programs, allowing users
to choose from various network models and sizes according Despite the large range of applications we discussed in the
to their needs. However, as with classical ML, the difficulty context of p-bits, much of the sampling algorithms have been
of training strongly hinders the use of deeper and more either standard MCMC or generic simulated annealing-based
general models. With scaled p-computers using millions of approaches. Future possibilities involve more sophisticated
magnetic p-bits, massively parallel and energy-efficient hard- sampling and annealing algorithms such as parallel tempering
ware implementations of the more general unrestricted/deep (PT) (see [128], [129] for some initial investigations). Further
BMs may become feasible, paving the way to simulate prac- improvements to hardware implementation include adaptive
tical quantum systems. versions of PT [130] as well as sophisticated nonequilibrium
To demonstrate one such example of this approach, Monte Carlo (NMC) algorithms [131]. Ideas involving over-
we show how p-bits laid out in sparse, hardware-aware graphs clocking p-bits such that they violate the tsynapse ≪ ⟨Tp-bit ⟩
can be used for ML quantum systems (see Fig. 8). The objec- requirement for further improvement [14] or sharing synaptic
tive of this problem is to find the ground state of a many-body operations between p-bits [82] could also be useful. A com-
quantum system, in this case, a 1-D FM Heisenberg Hamil- bination of these ideas with algorithm-architecture-device
tonian with an external transverse field. We start with an codesigns may lead to orders of magnitude improvement
RBM, which is one of the simplest neural network models, in sampling speeds and quality. In this context, as a sam-
and use its functional form as the variational guess for the pling throughput metric, increasing flips/ns is an important
ground state probabilities (the wave function is obtained by goal. In addition, solution quality, the possibility of cluster
taking the square root of probabilities according to the Born updates or algorithmic techniques also need to be considered
rule). A combination of probabilistic sampling and weight carefully. Given the plethora of approaches from multiple
updates gradually adjusts the variational guess such that communities, we also hope that model problems, benchmark-
the final guess points to the ground state of the quantum ing studies comparing different Ising machines, probabilistic

8 VOLUME 9, NO. 1, JUNE 2023

Chowdhury et al.: Full-Stack View of Probabilistic Computing With p-Bits: Devices, Architectures, and Algorithms

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