2.

1 Features of 8085 GTU: Summer

8085A is an 8-bit microprocessor suitable for a wide range of applications. It is a
single-chip, NMOS device implemented with approximately 6200 transistors on a
164 x 222 mil chip contained in a 40-pin dual-in-line package.
The features of 8085 include
1. It is an 8-bit microprocessor i.e. it can accept, process, or provide &-bit data

simultaneously.
2. It operates on a single + 5V power supply connected at Vcc power supply ground
is connected to Vss
3. It operates on clock cycle with 50 % duty cycle.
4. It has on chip clock generator. This intermal clock generator requires tuned circuit
like LC, RC or crystal. The internal clock generator divides oscillator frequency by
2 and generates clock signal, which can be used for synchronizing external devices.
5. It can operate with a 3 MHz clock frequency. The 8085A-2 version can operate at
the maximum frequency of 5 MHz.
6. It has 16 address lines, hence it can access (26) 64 kbytes of memory.
7. It provides 8-bit I/O addresses to access (2° ) 256 I/O ports.
8. In 8085, the lower 8-bit address bus (Ao -A7) and data bus (Do-D) are
multiplexed to reduce number of external pins. But due to this, external hardware
(latch) is required to separate address lines and data lines.
9. It supports 74 instructions with the following addressing modes
a) Immediate b) Register c)Direct d) Indirect e) Implied.
10. The Arithmetic Logic Unit (ALU) of 8085 performs
a) 8-bit binary addition with or without carry.
b) 16-bit binary addition. c) 2 digit BCD addition.
d) 8-bit binary subtraction with or without borrow.
e) 8-bit logical AND, OR, EX-OR, complement (NOT), and bit shift operations.
11. It has 8-bit accumulator, flag register, instruction register, six 8-bit general purpose
registers (B, C, D, E, H and L) and two 16-bit registers (SP and PC). Getting the
operand from the general purpose registers is more faster than from memory.
Hence skilled programmers always prefer general purpose registers to store
program variables than memory.
 12. It provides five hardware interrupts TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.
13. It has serial I/O control which allows serial communication.
14. It provides control
signals (IO/M, RD, WR) to control the bus cycles and hence
external bus controller is not required.
15. The external hardware (another
microprocessor or equivalent master) can detect
which machine cycle
microprocessor is executing using status signals
signals
(IO/M, So, S1). This feature is very useful when more than one are processors
using common system resources (memory and I/O devices).
16. It has a mechanism by which it is possible to increase its interrupt handling
capacity
17. The 8085 has an ability
share system bus with direct memory access controller.
to
This feature allows to transfer large amount of data from I/O device to
memory or
from memory to I/O device with high speeds.
18. It can be used to implement three chip microcomputer with supporting I/O
devices like IC 8155 and IC 8355.

Review Questions

1. Explain architectural features of 8085.

2. Justify the statement : 8085 is 8 bit microprocessor. GTU Summer-08, Marks 2,
a :
CE
2.2 Architecture of 8085
GTU: Summer-03,04,06,08,13,14,15,16,19, Winter-12,15,17,19
Fig. 2.2.1 shows the architecture of 8085. (See Fig. 2.2.1 on next page)
Itconsists of various functional blocks as listed below:
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Registers Incrementer/Decrementer address latch

Arithmetic and logic unit Interrupt control

Instruction decoder and machine Serial I/Ocontrol

cycle encoder

Address buffer Timing and control circuitry

Address/Data buffer
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 TRAP
INTA RST 6.5

INTR RST 5.5 RST 7.5 SID SOD

Interrupt control Serial /O control

8-bit internal data bus

J
Temporary Instruction W Reg Z Reg
Accumulator Flag register register
register BReg C Reg
D Reg E Reg
H RegL Reg
Stack pointer
Arithmetic Instruction
Logic decoder Program
Unit counter
and
(ALU) machine
Incrementer
cycle Decrementer
encoder
+ 5 VV address latch
POWER
SUPPLY GND

CLK A1 Timing and control

IN X21 Address/Data
CLK Address
CONTROL STATUS DMA RESE buffer buffer
GEN

CLK OUT RD ALE S HOLD RESET IN

RESET OUT A15-As AD, AD
READY WR So IO/M HLDA
Address bus Data / Address
bus
Fig. 2.2.1 Architecture of 8085

2.2.1 Register Structure Temporary

register
.The Fig. 2.2.2 shows the register structure of W Reg Z Reg
8085. (See Fig. 2.2.2 on next page) A Reg Flag Reg
The shaded portion of this register model is
BReg CReg
called programmer's model of 8085. It includes
D Reg EReg
six 8-bit registers (B, C, D, E, H and L) one
accumulator, one flag register and two 16-bit H Reg LReg
All these
registers (SP and PC). registers are Stack Pointer (SP)
accessible to programmer and hence they are
Program Counter (PC)
included in the programmer's model.
Fig. 2.2.2 Register structure of
The remaining registers Temporary, W and Z 8085
are not accessible to the programmers; they are
used by microprocessor for internal, intermediate operations.
Use of W and Z registers

The CALL instruction is used to transfer

program control to a subprogram or
subroutine. This instruction pushes the current PC contents onto the stack and loads the
given address into the PC. The given address is temporarily stored in the W and Z
registers and placed on the bus for the fetch cycle. Thus the program control is
transferred to the address given in the instruction. XCHG instruction exchanges the
contents of H with D and L with E. At the time of exchange W and Z registers are used
for temporary storage of data.

1. General purpose registers

B, C, D, E, H andL are 8-bit general purpose registers can be used as a separate 8-bit
registers or as 16-bit register pairs BC, DE and HL. HL pair also functions as a data
pointer or memory pointer.

2.Special purpose registers

a) Register A (Accumulator): It is a tri-state eight bit register. It is extensively used in
arithmetic, logic, load and store operations, as well as in, input/output (1/0)
operations. Most of the times the result of arithmetic and logical operations is stored in
the register A. Hence it is also identified as accumulator.

b) Flag Register (Program status word) It is an 8-bit register, in which five of the
bits carry significant information in the form of flags : S (Sign flag), Z (Zero flag), AC
(Auxiliary Carry flag), P (Parity flag), and CY (Carry flag), as shown in Fig. 2.2.3.
Dz D D5 D4 Da D2 D Do
AC wowwwww.
X CY
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Fig. 2.2.3 Flag register

S-Sign flag: After the execution of arithmetic or logical operations, if bit D, of the
result is 1, the sign flag is set. In a given byte if D, is 1, the number will be viewed as
negative number. If D, is 0, the number will be considered as positive number.
Z-Zero flag The zero flag sets if the result of operation in ALU is zero and flag
resets if result is non zero. The zero flag is also set if a certain register content becomes
zero following an increment or decrement operation of that register.
AC-Auxiliary Carry flag: This flag is set if there is an overflow out of bit 3 i.e. ,
carry from lower r.ibble to higher nibble (D3 bit to D, bit). This flag is used for BCD
operations and it is not available for the programmer.
is defined by the number of ones present in the accumulator.
P-Parity flag : Parity
After an arithmetic or logical operation if the result has an even number of ones,
1e. even parity, the flag is set. If the parity is odd, fag is reset.
 is set if there is overflow out of bit 7. The carry
flag also
CY-Carry flag : This flag an
serves as a borrow flag for subtraction. In both the examples shown below, the carr
rry
flag is set.
ADDITION SUBTRACTION

9B H 1001 1011 89 H 1000 1001

+75H +0111 0101 AB H 1010 1011

Borrow 1 DE H 11101 1110
Cary 10H 0001 0000
c)Instruction Reglster: In a typical processor operation, the processor first fetches the
opcode of instruction from memory (i.e. it places an address on the address bus and
memory responds by placing the data stored at the specified address on the data bus).
The CPU stores this opcode in a register called the instruction register. This opcode is
further sent to the instruction decoder to select one of the 256 alternatives.

d) Program Counter (PC) Program is a sequence of instructions. As mentioned

earlier, microprocessor fetches these instructions from the memory and executes them
sequentially. The program counter is a special purpose register which, at a given time,
stores the address of the next instruction to be fetched. Since address of 8085 is 16-bit,
the PC is 16-bit. Program Counter acts as a pointer to the next instruction. How
processor increments program counter depends on the nature of the instruction; for one
byte instruction it increments program counter by one, for two byte instruction it
increments program counter by two and for three byte instruction it increments
program
counter by three such that program counter always points to the address of the next
instruction.
e) Stack Pointer (SP): The stack is a reserved area of the memory in the RAM where
temporary information may be stored. A 16-bit stack pointer is used to hold the address
of the most recent stack entry.

2.2.2 Aithmetic Logic Unit (ALU)

The 8085's ALU performs arithmetic and
logical functions on eight bit variables. The
arithmetic unit performs bitwise fundamental arithmetic operations such as addition and
subtraction. The logic unit performs logical operations such as
complement, AND, OR
and EX-OR, as well as rotate and clear. The ALU also looks after the
decisions.
branching

2.2.3 Instruction Decoder and Machine Cycle Encoder

The instruction decoder decodes the opcode and accordingly gives information to the
timing and control circuit.
The 8085 executes seven different types of machine cycles. It gives the information
about which machine cycle is currently executing in the encoded form on the So, S and
I0/M lines. This task is done by machine cycle encoder.
2.2.4 Address Buffer

This is an 8-bit unidirectional tristate buffer. It is used to drive external high order
address bus (Ais-Ag).

2.2.5 Address/ Data Buffer

This is an 8-bit bi-directional buffer. It is used to drive multiplexed address/data bus,
ie. low order address bus (Ay - Ag) and data bus (D - Do).

2.2.6 Incrementer Decrementer Address Latch

This 16-bit register is used to increment or decrement the contents of program
counter or stack pointer.

2.2.7 Interrupt Control

The interrupt control block has five interrupt inputs RST 5.5, RST 6.5, RST 7.5, TRAP
and INTR and one acknowledge signal INTA. It controls the interrupt activity of 8085
microprocessor.

2.2.8 Serial 1/O Control

The 8085's serial I/O control provides two lines, SOD and SID for serial
communication. The Serial Output Data (SOD) line is used to send data serially and
Serial Input Data (SID) line is used to receive data serially.

2.2.9 Timing and Control Circuitry

The control circuitry in the processor 8085 is responsible for all the operations. The
control circuitry and hence the operations in 8085 are synchronized with the help of
clock signal. Along with the control of fetching and decoding operations and generating
control circuitry also generates signals
appropriate signals for instruction execution,
required to interface external devices to the processor, 8085.

2.2.10 Instruction Execution and Data Flow in 8085

I n order to execute program, the starting address of the program is loaded into

the Program Counter (PC).

address the address bus and activates
The 8085 sends the contents of PC as an on

RD control signal.
contents of addressed
Upon receiving the address and RD signal memory puts the
of an instruction.
location on the data bus which is an opcode
memory in the program
PC is incremented to point the next memory location
Meanwhile,
sequence.
 RD signal is deactivated and opcode is loaded into the instruction register via
internal bus of microprocessor.
The instruction decoding unit decodes the instruction and provides informationto
the timing and control unit to generate necessary signals for instruction execution.

Review Questions

1. Why are the program counter and the stack pointer 16-bit registers ?
GTU : Summer-03,.04, 15, Marks 2, CE
2. Write a short note on : Flags in 8085 GTU : Summer-03, Marks 8, CE
3. Show the of auxiliary carry flag with example.
use GTU : Summer-04, Marks 2
4. Give the functions of instruction register and instruction decoder

GTU : Summer-04, Marks 2, CE

5. Draw and Explain the functional block diagram of 8085 Microprocessor.
GTU: Summer-08, 14, Winter-12, Marks 8, CE; Summer-06, Marks 8 IT
6. 8085
Explain Register Organizations. GTU Summer-06, Marks 5, IT
7. Draw the internal block
diagram of microprocessor 8085 and explain the working of (i) Program
Counter register (i) Flag register with Bit significance.
GTU : Summer-13, Winter-15, Marks 7
8. What is the purpose of temporary registers W and Z in 8085
microprocessor ?
GTU : Summer-14, Mark
1
9. Draw and explain programming model of 8085 microprocessor. Explain working of 16 bit registers.
GTU: Summer-14, Marks 7
10. Writea note status flag
on
register. Also write the condition under which
the flag bits affected.
GTU Winter-12, Marks 7
11. Explain architecture of 8085 microprocessor with help of block
diagram. Explain function of each
block.
GTU : Summer-14, 15, Marks 7
12. Write a note
general purpose and special purpose registers of 8085.
on a

GTU: Winter-12, Marks 7

13. Draw programming model of 8085
microprocessor and explain flag register in brief.
14. Explain the programming model of 8085.
GTU :Winter-17, Marks 3
GTU Summer-16, Winter-19, Marks4
15. What is the function of temporary registers W and Z in 8085.

GTU: Suimmer-16, 19, Marks 3

16. Explain the architecture of B085 microprocessor with functional block diagram.
GTU: Winter-19, Marks
7
17. Explain:ALU. GTU Winter-19, Marks 3
2.3 8085 Pin Functions
GTU: Summer-03,04,05,06,08,13,14,16,17,18,19, Winter-13,15.18, 19
8085
Fig. 2.3.1 (a) and (b) shows 8085 pin configuration and functional pin diagram of
their
respectively. The signals of 8085 can be classified into seven groups according to
functions.

40Vcc Serial SID

VO 1 SOD
X2 39HOLD ports
RESET OUT3 38HLDA A15 High-order
address bus
SOD4 37cLK(OUT) TRAP
SID 5 36RESETIN RST 7.5
RST 6.5
TRAAP 6 3sREADY RST 5.5 ADO/ Mutip exed
data
RST 7.57 340/M INTR address / data
AD bus
RST 6.5 8 33s, READY
RST 5.5 9 32RD HOLD
INTR 1 0 31WR RESETIN 8085A
-ALE
INTA 1 1
8085A 30ALE
So
AD 12 29So INTA -S Control
and
AD,13 28 A1s HLDA I0/M status
RD signals
AD14 27A4 -WR
AD,15 26A3 Resetout
AD16 25A2 Power
Vccl+ 5 V)supply
AD17 24A CLKOUT GND
AD18 23A10
AD19 22A
Vss 20 21PA
Fig. 2.3.1 (a) Pin configuration Fig. 2.3.1 (b) Functional pin diagram
a) Power supply and frequency signals. b) Data bus and address bus
c) Control bus d) Interrupt signals
e)Serial I/0 signals ) DMA signals

8) Reset signals

2.3.1 Power Supply and Frequency Signals

i) Vcc: It requires a single +5 V power supply.

) Vss Ground reference.

ii) X4 and X2 (Input) : A +tuned circuit like LC, RC or crystal is connected at these
two pins. The internal clock generator divides oscillator frequency by 2, therefore, to
operate a system at 3 MHz, the crystal of tuned circuit must have a frequency of
6 MHz.
 v) CLK OUT (Output): This signal is used as a system clock for other devices. Its
frequency is half the oscillator frequency.

2.3.2 Data Bus and Address Bus

A) AD to AD, (Input/Output) : The 8-bit data bus (D - D,) is multiplexed with the

lower half (A A7) of the 16-bit address bus. During first part of the machineDuring cycle
T). lower 8 bits of memory address or 1/0 address appear on the bus. During
remaining part of the machine cycle (T2 and T3) these lines are used as a bi-directional
data bus.
B) A to As (Output) The upper half of the 16-bit address appears on the address lines
Ag to A 15. These lines are exclusively used for the most significant 8 bits of the 16-bit
address lines.

2.3.3 Cotrol and Status Signals

A) ALE (Address Latch Enable) (Output): We know that AD) to AD, lines are
multiplexed and the lower half of address (A A,) is available only during Ty of the
machine cyele. This lower half of address is also necessary during T2 and T of machine
cycle to access specific location in memory or 1/O port. This means that the lower half
of an address must be latched in T of the machine cycle, so that it is available
throughout the machine cycle. The latching of lower half of an address bus is done by
using external latch and ALE signal from 8085.
B) RD and WR (Output) : A low on RD indicates that the data must be read from
the selected memory location or 1/0
port via data bus. A low on WR indicates that the
data must be written into the selected memory location or I/O via data bus.
port
C)IO/ M, So and S, (Output) : 10/M indicates whether I/0 operation or memory
operation being
is carried out. S1 and So indicate the type of machine cycle in progress.
D) READY (Input): It is used by the microprocessor to sense whether a
ready not for data transfer. If
peripheral is
or not, the processor waits. It is thus used to
slower peripherals to the microprocessor.
synchronize

2.3.4 Interrupt Signals

Hardware Interrupts (Input): The 8085 has five hardware interrupt
signals:
RST 6.5, RST 7.5, TRAP and INTR. The microprocessor recognizes interrupt requests on
RST 5.5,
these lines at the end of the current instruction execution.
INTA (Output) : The INTA (Interrupt Acknowledge) signal is used to indicate that
the processor has acknowledged an INTR interrupt.
2.3.5 Serial l/O Signals

A) SID (Serial I/P Data) (Input): This input signal is used to accept serial data bit
by bit from the external device.
B) SOD (Serial O/P Data) (Output) : This is an output signal which enables the
transmission of serial data bit by bit to the external device.

2.3.6 DMA Signal

A) HOLD Input): This

signal indicates
of address bus, data bus and control bus.
that another master is requesting for the use

B) HLDA (Output): This active high signal is used to acknowledge HOLD request.

2.3.7 Reset Signals

A) RESET IN (Input): A low on this pin
1) Sets the program counter to zero (0000H) and clears the INTE flag.
2) Resets the interrupt enable and HLDA flip-flops.
3) Tri-states the data bus, address bus and control bus.
(Note: Only during RESET is active).
4) Affects the contents of processor's internal registers randomly.
B) RESET oUT (Output): This active high signal indicates that processor is being
reset. This signal is synchronized to the processor clock and it can be used to reset other
devices connected in the system.

Review Questions

1. Write about the pin configuration of 8085 processor and explain them in detail.
2. Explain the signals used in DMA operation in 8085.
3. Drw thepin diagram of 8085 microprocessor.
4 Drau the pin diagram of 8085 microprocessor and list the classification of siguals.
5. Explain the functions ofthe follorwing pins: i) ALE )READY ii) WR iv) HOLD and HLDA
6. Explain the functions of the following pins of 8085: i 10/M ii) So and S
7. Discuss the function of following pins: i) READY ii) RESET ii) HOLD iv) INTR
8. Draw and explain the pinout diagram of the 8085 microprocessor.
GTU : Summer-06, Marks 8, IT
9. Explain the need of X and X, pins of the 8085
microprocessor?
GTU: Summer-03, Marks 2, CE
10. Why does ALE
11. What is
go high in start of every Machine cycle? GTU Summer-04, Marks 2, CE
importance of READY signal? GTU: Summer-04, Marks 2, CE
12. Explain the functions of SID and SOD pins. GTU: Summer-04, Marks 4, CE
 13. Describe the meaning of following 8085 pins.
READY, HOLD and HLDA, ALE, INTA GTU: Summer-05, Marks CE 6,

14. Explain following pins : 1) ALE 2) READY GTU: Summer-08, Marks 2, CE

15. Explain the functions of the following pins of microprocessor 8085
() ALE i) s0, s1 iüi) INTR, INTA V) SID, SOD GTU: Summer-13, 16 Marks 7
16. Some of the pins of 8035 are listed beloo. For each pin show whether it is an input ine or an
output line and mention its function.
1) ALE 2) sOD 3) 10/ M 4)READY 5) HOLD 6) RD GTU:Winter-13, 15, Marks 7
17. What is the purpose of HOLD and HLDA pin in 8085 microprocessor?
GTU: Summer-14, Mark 1
18. Explain the operations of following pins of 8085: Rendy, Sh amd So HOLD, HLDA, TRPA, ALE.
GTU: Summer-17, Marks 7
19. State the function of ALE and TRAP pins in 8085. GTU: Summer-18, Marks 4
20. Explain function of following pins: a) TRAP b) HOLD c) READY
GTU: Summer-16, Winter-18, Marks 3
21. What is the function offollowing pins in 8085: TRAP and HLDA.
GTU Summer-16, 19, Marks 4
22. Only draw pin diagram of 8085 microprocessor. GTU: Winter-19, Marks 4
2.4 Bus Organization
GTU Summer-03,05,06,08,14,16,17,18, 19, Winter-12,14,15,18,19
In this section we are going to see how we can use various buses of 8085, how to
demultiplex address and data bus, how to generate control signals, how to provide clock
and reset signals to 8085 and so on.

2.4.1 Clock Circuits

The 8085 has on chip clock
Vcc (+5 V) - Clk Out
generator. Fig. 2.4.1 shows the
internal block diagram of the on
chip clock generator. The a
internal clock generator requires
tuned circuit like LC, RC or
X CIk
02
crystal, or external clock source
as an input to generate the
clock. The internal T-flip flop
Fig. 2.4.1 Block diagram of built-in clock generator
divides the frequency by 2.
Hence the operating frequency of the 8085 is always half of the oscillator frequency.
Crystal oscillator circuit: Fig. 2.4.2 shows the crystal oscillator circuit. It is the most
stable circuit. The 20 pF capacitor in the circuit is connected to assure oscillator start-up
at the correct frequency.

Crystal

CT 20 pF

Fig. 2.4.2 Crystal clock circuit

the
Example 2.4.1 Specify crystal frequency required for an
8085 system to operate at
1.1 MHz.
Solution: 2.2 MHz.

2.4.2 Demultiplexing AD,-AD

The latching of lower half of an address is done by using external latch and ALE
signal from 8085. The Fig. 2.4.3 shows the hardware connection for latching the lower
half of an address. The IC 74LS373 is an 8-bit latch, having 8 D flip-flops. The inputis
transferred to the output only when clock is high. This clock signal is driven by ALE
signal from 8085. The ALE signal is activated only during Tr. so input is transferred to
the output only during T1 ie. address (Ap A7) on the AD, to AD, multiplexed bus. In
the remaining part of the machine cycle, ALE signal is disabled so output of the latch
(Ap Ay) remains unchanged. To latch lower half of an address, in each machine cycle,
the 8085 gives ALE signal high during T1 of every machine cycle. With this circuit, we
can use output of latch as lower half address bus and input of latch (ADg-AD,) as data
bus.

ADo
8 bit PO
latch
AD7 M
CLK OE
ALE

Flg. 2.4.3 Latching circult

2.4.3 Reset Circult
On reset, the PC sets to 0000H which causes the 8085 to execute the first instruction
Om address 0000H. For proper reset operation reset signal must be held low for at
 be +5V
least 3 clock cycles. The power-on reset circuit can
used to ensure execution of first instruction from
address 0000H. Fig. 2.4.4 shows the power-on reset
circuit with typical R, C values. (Note: R, C values IN 4148 A 275 K

may vary due to power supply ramp up time). To 8085

Reset
100 2
Upon power up or key press, the RESET IN goes
low and slowly rises to +5 V, providing sufficient time
for the processor to reset the system. The diode is contact NO
when
connected to discharge the capacitor immediately
power supply is switched OFF.
Fig. 2.4.4 Power on reset

2.4.4 Generation of Control Signals

The 8085 microprocessor provides RD and WR sigmals to initiate read or write cycle.
Because these signals are used both for reading/writing memory and for

input device, it is necessary to generate separate read and write

reading/writing an

signals for memory and I/O devices.

The 8085 provides IO/M signal to indicate whether the initiated cycle is for 1/0
device or for memory device. Using 10/M signal along with RD and WR, it is possible
to generate separate four control signals
MEMR (Memory Read): To read data from memory.
MEMW (Memory Write): To write data in memory.
IOR (VO Read) To read data from I/O device.
IOW (VO Write) :To write data in I/O device.
Fig. 24.5 and 2.4.6 show the circuit which generates MEMR, MEMW, IOR and IOW
signals.
1O/M
M
RD E M R = RD D- MEMR

IO/M IO/M
WR D - MEMW
WR
MEMW

1M-
RD
OR IO/M
RD
-TOR

AM- -IOW 1O/M

WR
-IOW
WR
Fig. 2.4.5
 IO/M RD WR

D MEMR

D- -MEMW

D IOR

D IOW

Fig. 2.4.6

We know that for OR gate, when both

the inputs are low then only output is low.
MEMR, MEMW, IOR and 1OW
Table 2.4.1 shows the truth table used to generate ORed
IO/M low for memory operation. This signal is logically
signals. The signal goes
MEMW signals. When both RD and IO/M signals
with RD and WR to get MEMR and
low. Similarly, when both WR and I0/M signals go low
go low, MEMR signal goes
and IOW signals for 1/O operation, 10/M
MEMW signal goes low. To generate IOR
and then ORed with RD and WR sigmals.
logically
signal is first inverted www wwwwwwwwww.w w
wwwwwwwwwwww wwwww wwwswwwwwwww

WR MEMR MEMW IOR IOW

I0/M RD
RD+10/M WR +10/M RD +10/M WR+I0/M
* * ********** *******

exists, because RD and WR signals does

not go
Condition never
low simultaneousBy

1
0

Condition never exists, because RD and WR signals does not go

0 low simultaneously

********* ** ede

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1
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Table 2.4.1
 Same truth table can be implemented using 3 : 8 decoder as shown in Fig. 2.4.7.
+5V

G Voc
Y MEMR
3:8 Y MEMW
WR Decoder
RD Y4
IO/M (74LS138))
IOR
Y IOW
Y7

Fig.2.4.7 Generation of control signals using 3 :8 decoder

2.4.5 Bus Drivers
Typically, the 8085 buses can source 400 uA and sink 2 mA of current, i.e. it can
drive only one TTL load. Therefore, it is necessary to increase driving capacity of the
8085 buses. Bus drivers, buffers are used to increase the driving capacity of the buses.

Unidirectional Buffers A Vcc 18

As we know, the address bus is
unidirectional, 8-bit unidirectional |1A2 12 6

buffer, 74LS244 is used to buffer higher 1A

address bus. The Fig. 2.4.8 shows the
logic diagram of 74LS244. It consists of 1A 1Y4
12

eight non-inverting buffers with 115

tri-state outputs. Each one can sink

13 2A6
24 mA and source 15 mA of current.
These buffers are divided into two 154
2s
groups. The enabling and disabling of 17 2
these groups are controlled by 1G and
2G lines. GND26
0
19
Bi-directional Buffer Fig. 2.4.8 Logic diagram of the 74LS244

To increase the driving capacity of data bus, bi-directional buffer is used. Fig. 2.49
shows the logic diagram of the bi-directional buffer 74LS245, also called an octal bus
transceivers. It consists of sixteen non-inverting buffers, eight for each direction, with
 74LS245 10
20
Vcc GND
2 A B 18 Function table
3 A2 B217 Directionn
4 B3 16 Enable control Operation
G DIR
5 A B 15 B Data to A Bus
6 As Bs 14 H A Data to B Bus
H X Isolation
7 Ag Bs 13
H High level,L = Low level,X=Irrelevant
8 A B7 12
Bs 11
DIR
19
Direction Enable
control

Fig. 2.4.9 Logic diagram of the 74L$245

tri-state output. The direction of data flow is controlled by the pin DIR. When DIR is
high, data flows from the A bus to the B bus; when it is low, data flows from B to A.
The active low enable signal and the DIR signal are ANDed to activate the bus lines.
Each buffer in this device can sink 24 mA and source 15 mA of current.

2.4.6 Typical Configuration

Fig. 2.4.10 shows schematic of the 8085 microprocessor demultiplexed address bus
and control signals.(See Fig. 2.4.10 on next page)
It also shows clock and reset circuits. Interrupt lines which are not in use are

grounded. This is necessary because may cause false triggering of

floating interrupt line
interrupt. Similarly, since the DMA controller is not used, HOLD line is also grounded.
As we know READY signal is used to synchronize slow peripherals with the
microprocessor. When it is low, microprocessor enters in the wait state and when it is
high, it indicates that the memory or peripheral is ready to send or receive data. Here,
the READY signal is tied high to prevent the microprocessor from entering the wait
state. ALE signal is connected to the clock input of the latch, to latch the low order
address in T of the machine cycle. To control the direction of the bi-directional buffer
74LS245, RD signal from 8085 is connected to DIR input of the bi-directional buffer.
Thus, when RD signal is low, DIR is low and data flows from memory or 1/0 device to

edatamucroprocessor, performing read operation. When RD signal is high, DIR is high and
flows from microprocessor to memory or 1/0 device performing write operation.
 9+5 V

20
A16 17 [Vcc A15
15 5
A14
131174LS244 Octal A13 High-
Bus order
A12 Address
3. 12 A1
Driver14 A4o bus
16 Ag
18

10

9+5 V 9+5 V

40 135 AD7 20
VcC READY 18| Vcc 19
2 MHz
28 16As
15 Low
crystal 74LS373
12 A4
20 pF
As21 order
dress
bus
19
ADT
4SOD A
5SID
33 s
ADo12 11
OC GND
10
Ao
30
8085 A
NC29 S ALE
OM34 +5 V
37
CLK OUT RD2

38
100 K HLDA
WR 31 11-D7
11
INTA
74LS245
12-De
13 Ds
1 uF
6 RESETIN
Bl-directlonal 14 D Data
TRAP 15
1K Bus D3 bus

RST7.5 Driver 16D2

B
RST6.5 17D
RST5.5
RESET DII GGND 18 Do
OUT
10 NTR
From 39HOLD 1 10 20
Interrupt
sOurce 9+5V
6 16
G3
O IOW Control
IO/M 3A2 74LS138
RD 2 3-to-8
decoder O
,10-OR
MEMW
bus

WR
14-MEMR
GND

Fig. 2.4.10 Typlcal 8086 configuration

 Review Questions

1. How would you determine at what speed 8085 works ?

GTU: Summer-08, Marks 2, CE
2. Define thefollowing 1) Bufer 2) Linedriver.
GTU: Summer-03, Marks 4, CE
3. What control signals ? How they generated?
are are
GTU: Summer-05, Marks 3, CE
4. Generate control signal using NAND gates.
GTU: Summer:08, Marks 5, CE
5. Explain the need to demultiplex the bus AD AD,-

GTU: Summer-06, Marks 2, IT

6. Ansuver the question in brief. 8085 -

Demuitiplexing of the bus AD, -

AD
GTU: Summer-03,06, Marks 5, IT, Winter-12, May-13
Explain how address/data lines ADO-AD7 are de-multiplexed. Draw logic diagram to generate
control signals MEMW, MEMR, IOW and 1OR from 10/M, WR and RD.
GTU: Summer-14, Marks 7
D r a w schematic to generate readfurite control signals for memory and input/output of 8085
microprocessor. GTU: Winter-14, Marks 4
W h a t multplexing ? How it is done in microprocessor 8085 for address and data bus ? Explain
with neat diagram.
GTU: Winter-15, 19, Marks 7
With the help of diagram shorw how de-multiplexing of addressdata lines ADO-AD7 can be
achieved ? Also explain the generation of control signals MEMW, MEMR, IOR and 1OW.

GTU: Summer-16, Marks 7

D r a w logic diagram to generate control signals necessaryfor interfacing with memory chip.
GTU: Summer-17, Marks 3
12/Explain how address/data lines ADO-AD7 are de-multiplexed in 8085 ?
GTU: Summer-17, Marks 4
tlustrate control signal generation and de-multiplering of ADg-AD, withsuitablediagran
GTU: Winter-17, Marks 4
AExplain demultiplexing of address/data lines in 8085. GTU: Summer-18, Marks 4
J Dru logic dingram to generate control signal necessary for interfacing with memory chip
GTU: Winter-18, Marks 3
Explain demultiplexing of Address/data lines in 8085. GTU : Winter-18, Marks 3
How demultiplexing of address/data lines (ADO-AD7) can be achieved ? Also explain the
generation of all the control signals.
GTU: Summer-19, Marks 7
2.5 Short Questions and Answers
Q.1 List the 16 blt registers of 8085 microprocessor.
Ans.: Stack pointer (SP) and
Q.2
Program counter (PC).
List the allowed
reglster pairs of 8085.
Ans.:B-C register pair, D-E
register pair, H-L register pair
Q.3 Mention the purpose of SID and SOD lInes.
Ans.: SID (Serial input data line) I t is an input line through which the microprocessor
It is an output line through which
accepts serial data. SOD (Serial output data line) :
the

microprocessor sends output serial data.

a4What ls the functlon of lOM slgnal In the 80851
Ans.: It is a status signal. It is used to differentiate between memory locations and I/0

is low (IO/M 0) it denotes the memory related

operations. When this signal
=

1) it denotes an I/O operation.

operations. When this signal is high (10/M
=

Q.5 What is the signal classification of 8085 ?

Ans.: All the signals of 8085 can be classified into six groups

i) Address bus i) Data bus

ii) Control and status signals iv) Power supply and frequeney signals
v)Externally initiated signals vi) Serial I/0 ports.
Q.6 What is the use of bi-directional buffer ?
Ans.: It is used to increase the driving capacity of the data bus. The data bus of a
microcomputer system is bi-directional, so it requires a bi-directional buffer that allows
the data to flow in both directions.
Q.7 Explain the signals HOLD, READY and SID.
Ane. : HOLD indicates that a peripheral such as DMA controller is requesting the use
of address bus, data bus and control bus. READY is used to delay the microprocessor
read or write cycles until a slow responding peripheral is ready to send or accept data
SID is used to accept serial data bit by bit.
Q.8 What is the need for ALE signal in 8085 mlcroprocessor ?
Ans.: The ALE signal is used to demultiplex (separate) AD AD, lines to Ag A
(address lines) and D - D, (data lines). The separation of address lines and data lines is

achieved by connecting a external latch to AD% - AD, lines and enabling the latch when
ALE signal is active.
Q.9 How perfomance of a microprocessor ls measured Interms of MIPS ?
Ans. The performance of a
microprocessor is measured interms of MIPS
(Million
Instructions per Second). It is given as,

MIPS rate = 1
Average time required for the execution of instruction x 10°

Q.10 A microprocessor takes n ys for executing an instructlon. What design change

wll make the microprocessor to execute the same instruction In n/2 ?
Ans. By replacing the crystal of double frequency than that of existing one we can
execute the same instruction in half time.
 *************

Q.11 If a 5 MHz crystal is connected wlth 8085; what ls the value of system clock
frequency and one T-state ?

Ans. System clock frequency = Crystal frequency 5 MHz 2.5 MHz,

1
one T-state = = 0.4 usec.
2.5x 106
Q.12 To obtain a 320 ns clock, what should be the Input clock frequency ? What is
the frequency of clock signal at CLK oUT ?
Ans. T = 320 nsec.
1
System cdock frequency =

320x10
3.125
9
3.125 MHz.

Crystal frequency (i.e. input frequency) = 2 x System clock frequency

2x3.125x10 = 6.25 MHz

The frequency of clock signal at CLK OUT -rystalfrequency 6.25 MHz

2 2

3.125 MHz.
a.13 What are the important control signals in 8085 microprocessor ?
Ans.: The important control signals in 8085 microprocessor are ALE, IO/M, RD
and WR
Q.14 What is tri-state logic ?
Ans. Logic outputs have two normal states, LOW and HIGH, corresponding to logic
values 0 and 1. However, some outputs have a third electrical state that is not logic
state at all, called the high-impedance or floating state. In this state the output behaves as
if it isn't even connected to the circuit, except for a small leakage current that may flow
into or out of the output pin. The circuit having such three states is called tri-state logic.
a15 What is the function of the Ready signal of 8085 ?
Ans.: It is used by the microprocessor to sense whether a peripheral is ready or not for
data transfer. If not, the processor waits. It is thus used to synchronize slower
peripherals to the microprocessor.
Q.16 List the five Interrupt pins avallable In 8085.
Ans. The five interrupt pins available in 8085 are: TRAP, RST 7.5, RST 6.5, RST 5.5,
and INTR
of 8085
Q.17 8pecify the size of data, address, memory word and memory capacity
microprocessor.
Ans. Size of data bus = 8-bits Size of address bus = 16-bits
Size of memory word = 8-bits Memory capacity = 64 kbytes
Q.18 List the specilal purpose registers of 8085.
Ans. The special purpose registers of 8085 are:
1. A (Accumulator) 2. Flag register ****************************************************************************************

********************. ................ .... .... . **ssrntoonnsersesosensss******************

 ** ***** *aa*************************d***************
*********************************************.***seiesnasesu......

3. Instruction register 4. Program counter 5. Stack pointer.

a.19 List the signals provided for DMA operation by 8085 and explaln thelr use.
Ans.: HOLD This signal indicates that another master is requesting for the use of
address bus, data bus and control bus.
HLDA This active high signal is used to acknowledge HOLD request.

Q.20 What are the content of PC and INTE flag after reset ?
Ans.: After reset, PC is loaded with 0000H and INTE flag is cleared.

a.21 What is the need of bus drlvers?

Ane.: Typically, the 8085 buses can source 400 uA and sink 2 mA of current, i.e. it can
drive only one TTL load. Therefore, it is necessary to increase driving capacity of the
8085 buses. Bus drivers, buffers are used to increase the driving capacity of the buses.

a.22 What areflags used in 8085 ?

the various
Ans. Various flags in 8085 are S (Sign flag), z (Zero flag), AC (Auxiliary carry flag)
P (Parity flag), and CY (Carry flag).
~** wwwwwwwww. voou ~************ ***********************

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