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Booth Encodng

The document discusses techniques for encoding binary numbers into Canonical Signed Digit (CSD) vectors and radix-4 signed digits, which help reduce the number of partial products in multiplication. It explains Booth encoding and its benefits for speeding up multiplication processes, particularly in array multipliers. Additionally, it compares Wallace-tree and Dadda multipliers, highlighting their efficiency in terms of speed and area reduction in digital circuits.

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R INI BHANDARI
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13 views2 pages

Booth Encodng

The document discusses techniques for encoding binary numbers into Canonical Signed Digit (CSD) vectors and radix-4 signed digits, which help reduce the number of partial products in multiplication. It explains Booth encoding and its benefits for speeding up multiplication processes, particularly in array multipliers. Additionally, it compares Wallace-tree and Dadda multipliers, highlighting their efficiency in terms of speed and area reduction in digital circuits.

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R INI BHANDARI
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© © All Rights Reserved
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26 DATAPATHLOGIC CELLS traction is as easy as an addition). We say B has a weight of 4 and D has a weight of 3. By using D instead of B we have reduced the number of partial products by 1 (4-3). We can recode (or encode) any binary number, B, as a CSD vector, D, as fol- ows (canonical means there is only one CSD vector for any number): D=Bi+C)-2Cis1. (2.58) where C,, is the carry from the sum of B,,,, +B, +C; (we start with Cp =0). As another example, if B=011 (By=0, B,=1, By=1; decimal 3), then, using Bg. 2.58, +0 Do =By+Cp~2C Dy=By+C)-20=1 41-2 D,=By+C,-2C)=0+ 1-01, 2359) so that D= 107 (decimal 4~ 1 =3). CSD vectors ate useful to represent fixed coefi- cients in digital filters, for example We can recode using a radix other than 2. Suppose B is an (n+ 1)-digit two's ‘complement number, BaBy+B,2+B:2"+... +B 24+... +B,_(2"-!-B,2", 2.60) ‘We can rewrite the expression for B using the following sleight-of-hand: 2B-B =B=-By+ (By-By)2+...+(B,_;-B)2!+... +B,_.2"-!-B,2" = (2B )+By)2+ (2B; +By+B))2? +. +0284 B,_ +By_2)2!+ 2B; 24 By #B2! + +(2B,+B;_| +B;_2)2”" ‘This is very useful. Consider B= 101001 (decimal 9-32 =-23, n=5), B= 10100) (2B + B)2° + (-2B3 + By + By)2* + (-2Bs+ By + By)2* ((-2x0)+ 129+ (2x +0402 + (2x +04 24 2.62) Equation 2.61 tells us how to encode B as a radix-4 signed digit, E= 131 (decimal =16-8+1=-23), To multiply by B encoded as E we only have to perform a ‘multiplication by 2 (a shift) and three addjsubtract operations, 89 20 (CHAPTER 2 (eMOS LOGIC Using Eq. 2.61 we can encode any number by taking groups of three bits at a time and calculating Ej=-2B/+Bj_)+Bj2, Eye 5 Biot Big + Bie on 2.63) where each 3-bit group overlaps by one bit. We pad B with a zer0, By...B)By0, 10 ‘match the first term in Eq. 2.61. If B has an odd number of bits, then we extend the sign: B,B,,..ByBg0. For example, B=01011 (eleven), encodes to E=1iT (164-1)! and B= 101 is E= 11. This is called Booth encoding and reduces the ‘numberof partial products by a factor of two and thus considerably reduces the area 8 Well as increasing the speed of our multiplier [Booth, 1951] [Next we turn our attention to improving the speed of addition in the CSA array. Figure 2.28(a) shows a section ofthe 6-bit array multiplier from Figure 2.27. We ean collapse the chain of adders a0-f5 (5 adder delays) to the Wallace tree consisting of adders 5.1-5.4 (4 adder delays) shown in Figure 2.28(). Figure 228(0) pitorally represents multiplication as a sort of golf course. Each link corresponds to an adder. The holes or dots are the outputs of one stage (and the inputs of the next). At each stage we have the following three choices: (1) sum three outputs using a full adder denoted by a box enclosing three dots; (2) sum two out- puts using a half adder (a box with two dots); (3) pass the outputs directly to the next stage. The two outputs of an adder are joined by a diagonal line (ull adders use black dots, half adders white dots). The object of the game is to choose (I), (2), oF (3) at cach stage to maximize the performance of the multiplier. In tree-based multipliers there are two ways to do this—working forward and working backward {In a Wallace-tree multiplier we work forward from the mtipler inputs, com- pressing the number of signals to be added at each stage (Wallace, 1960]. We ean view an FA as a 3:2 compressor or (3, 2) eounter—it counts the number of I's on the inputs. Thus, for example, an input of "1O1' (two ''s) results in an output "10° @) half adder is a (2, 2) counter. To form Ps in Figure 2.29 we must add 6 summands, (Sos, Sia Sans Soa, Sat nd So) and 4 carries from the Py column. We add these in stages 1=7, compressing from 6:3:2:2:3:1:1. Notice that we wait until stage S to add the last cary from column Py, and this means we expand (rather than compress) the number of signals (fiom 2 10 3) between stages 3 and 5. The maximum delay through the CSA array of Figure 2.29 is 6 adder delays. To this we must add the delay of the 4bit (9 inputs) CPA (Stage 7) Tere are 26 adders (6 half adders) plus the 4 adders in the CPA. Ina Dadda multiplier (Figure 2.30) we work backward from the final product [Dadda, 1965]. Each stage has a maximum of 2, 3, 4, 6,9, 13, 19, ... outputs (each suceessive stage is 3/2 times larger—rounded down 10 an integer). Thus, for example, in Figure 2.28(@) we require 3 stages (with 3 adder delays—plus the delay of a 10-bit output CPA) for a 6-bit Dadda multiplier. There are 19 adders (4 half audders) in the CSA plus the 10 adders (2 half adders) in the CPA. A Dada multiplier is usually faster and smaller than a Wallace-tree multiplier

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