MSBTE Polytechnic- 4th Sem CO

Microprocessor Programming
Unit 1-8086- 16 Bit Microprocessor
Akhil M. Jaiswal
9028637523

Microprocessor : A Microprocessor is an Integrated Circuit with all the functions

of a CPU. It is the most vital component of a computer system and is considered be its'
brain and heart. However, it cannot be used stand-alone since unlike a microcontroller
it has no memory or peripherals.

1.1 8086 Microprocessor:

 Intel 8086 microprocessor is the enhanced version of Intel 8085 microprocessor

designed by Intel in 1976.
 It is the first member of the x86 family of microprocessors, which includes many
popular CPUs used in personal computers.
 The 8086 microprocessor is a 16-bit, N-channel, HMOS microprocessor. Where the
HMOS is used for "High-speed Metal Oxide Semiconductor".
 Intel 8086 is built on a single semiconductor chip and packaged in a 40-pin IC
package. The type of package is DIP (Dual Inline Package).
 It consists of powerful instruction set, which provides operations like multiplication &
division.
 It uses 20 address lines & 16 data- lines that can directly address up to 220 = 1 MB of
memory.
 8086 microprocessor has two main execution units: the execution unit (EU) and the
bus interface unit (BIU).

Intel 8086 Microprocessor Chip

Akhil M. Jaiswal 9028637523
Salient Features of 8086:
1. 16-bit Microprocessor: Operates on 16-bit data at a time.
2. Clock Speed: Operates at 5, 8, or 10 MHz.
3. Registers: 14 registers, each 16-bit wide.
4. Address Bus: 20-bit address bus, capable of addressing 1 MB of memory.
5. Data Bus: 16-bit data bus, allowing faster data transfer.
6. Flags: It has nine flags.
7. Instruction Set: Supports arithmetic, logic, control, and data transfer instructions.
8. Pipelining: Uses instruction pipelining to improve efficiency.
9. Modes of Operation: Works in Two modes—Minimum Mode (single processor)
and Maximum Mode (multiprocessor).
10. Transistors: It consists of 29,000 transistors.
11. Segmentation: Supports memory segmentation. (divides memory into 4
segments)
12. Input/ Output Operations: 8086 can access 2^16 = 65,536 I/O's.

8086 Pin Descriptions: Following is the pin diagram of 8086

microprocessor-

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8086 Pin Description in detail −

1. Vcc,/GND: Power supply and frequency signals : It uses 5V DC supply at VCC pin 40,
and uses ground at VSS pin 1 and 20 for its operation.
2. Clock signal: Clock signal is provided through Pin-19. It provides timing to the
processor for operations. Its frequency is different for different versions, i.e. 5MHz,
8MHz and 10MHz.
3. Address/data bus- AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low
order byte data and AD8AD15 carries higher order byte data. During the first clock
cycle, it carries 16-bit address and after that it carries 16-bit data.
4. Address/status bus- A16-A19/S3-S6. These are the 4 address/status buses. During
the first clock cycle, it carries 4-bit address and later it carries status signals.
5. S7/BHE- BHE stands for Bus High Enable. It is available at pin 34 and used to indicate
the transfer of data using data bus D8-D15. This signal is low during the first clock
cycle, thereafter it is active.
6. Read- It is available at pin 32 and is used to read signal for Read operation.
7. Ready- It is available at pin 22. It is an acknowledgement signal from I/O devices that
data is transferred. It is an active high signal. When it is high, it indicates that the
device is ready to transfer data. When it is low, it indicates wait state.
8. RESET- It is available at pin 21 and is used to restart the execution. It causes the
processor to immediately terminate its present activity. This signal is active high for
the first 4 clock cycles to RESET the microprocessor.
9. INTR- It is available at pin 18. It is an interrupt request signal, which is sampled
during the last clock cycle of each instruction to determine if the processor
considered this as an interrupt or not.
10. NMI- It stands for non-maskable interrupt and is available at pin 17. It is an edge
triggered input, which causes an interrupt request to the microprocessor.
11. TEST: This signal is like wait state and is available at pin 23. When this signal is high,
then the processor has to wait for IDLE state, else the execution continues.
12. MN/MX- It stands for Minimum/Maximum and is available at pin 33. It indicates what
mode the processor is to operate in; when it is high, it works in the minimum mode
and vice-aversa.
13. INTA- It is an interrupt acknowledgement signal and id available at pin 24. When the
microprocessor receives this signal, it acknowledges the interrupt.
14. ALE- It stands for address enable latch and is available at pin 25. A positive pulse is
generated each time the processor begins any operation. This signal indicates the
availability of a valid address on the address/data lines.
15. DEN- It stands for Data Enable and is available at pin 26. It is used to enable
Transreceiver 8286. The transreceiver is a device used to separate data from the
address/data bus.
16. DT/R- It stands for Data Transmit/Receive signal and is available at pin 27. It decides
the direction of data flow through the transreceiver. When it is high, data is
transmitted out and vice-a-versa.
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17. M/IO- This signal is used to distinguish between memory and I/O operations. When it
is high, it indicates I/O operation and when it is low indicates the memory operation. It
is available at pin 28.
18. WR- It stands for write signal and is available at pin 29. It is used to write the data
into the memory or the output device depending on the status of M/IO signal.
19. HLDA- It stands for Hold Acknowledgement signal and is available at pin 30. This
signal acknowledges the HOLD signal.
20. HOLD- This signal indicates to the processor that external devices are requesting to
access the address/data buses. It is available at pin 31.
21. QS1 and QS0 :-These are queue status signals and are available at pin 24 and 25.
These signals provide the status of instruction queue. Their conditions are shown in
the following table −

QS0 QS1 Status

0 0 No operation
0 1 First byte of opcode from the queue
1 0 Empty the queue
1 1 Subsequent byte from the queue

22. S0, S1, S2: These are the status signals that provide the status of operation, which is
used by the Bus Controller 8288 to generate memory & I/O control signals. These are
available at pin 26, 27, and 28. Following is the table showing their status −

S2 S1 S0 Status
0 0 0 Interrupt acknowledgement
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive

23. LOCK:- When this signal is active, it indicates to the other processors not to ask the
CPU to leave the system bus. It is activated using the LOCK prefix on any instruction
and is available at pin 29.
24. RQ/GT1 and RQ/GT0 :-These are the Request/Grant signals used by the other
processors requesting the CPU to release the system bus. When the signal is received
by CPU, then it sends acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.

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1.2 Architecture of 8086
Functional Block Diagram of 8086: The following diagram depicts the
architecture of a 8086 Microprocessor

8086 architecture is divided into two main units: Bus Interface Unit (BIU) &
Execution Unit (EU)

I. Bus Interface Unit (BIU): It contains Address Generation Circuit,

Segment Registers, Instruction Pointer (IP), 6-byte instruction queue & 16 bit
Address-cum-Data bus.

The BIU:

o Handles transfer of data, address generation and bus control.

o Fetches instruction codes, stores fetched instruction codes in first-in-first-out
register set called a queue,
o Reads data from memory and I/O devices,
o Writes data to memory and I/O devices,
o It relocates addresses of operands since it gets un-relocated operand addresses
from EU. The EU tells the BIU from where to fetch instructions or where to read
data.

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BIU has the following 4 functional parts:

1. Address Generation Circuit:
 The BIU has a Physical Address Generation Circuit.
 It generates the 20-bit physical address using Segment and Offset
addresses using the formula:
 In Bus Interface Unit (BIU) the circuit shown by the Σ symbol is
responsible for the calculation unit which is used to calculate the
physical address of an instruction in memory.
Physical Address = Segment Address x 10H + Offset Address
2. Instruction Queue: When EU executes instructions, the BIU gets 6-bytes of the next
instruction and stores them in the instruction queue and this process is known as
instruction pre fetch. This process increases the speed of the processor.
3. Segment Registers: A segment register contains the addresses of instructions and
data in memory which are used by the processor to access memory locations. It
points to the starting address of a memory segment currently being used.
There are 4 segment registers in 8086 as given below:
a. Code Segment Register (CS): Code segment of the memory holds instruction
codes of a program.
b. Data Segment Register (DS): The data, variables and constants given in the
program are held in the data segment of the memory.
c. Stack Segment Register (SS): Stack segment holds addresses and data of
subroutines. It also holds the contents of registers and memory locations given
in PUSH instruction.
d. Extra Segment Register (ES): Extra segment holds the destination addresses
of some data of certain string instructions.
4. Instruction Pointer (IP): The instruction pointer in the 8086 microprocessor acts as
a program counter. It indicates to the address of the next instruction to be executed.

II. Execution Unit (EU)

o The EU receives opcode of an instruction from the queue, decodes it and then
executes it. While Execution, unit decodes or executes an instruction, then the BIU
fetches instruction codes from the memory and stores them in the queue.
o The BIU and EU operate in parallel independently. This makes processing faster.
o Execution Unit Contains: General purpose registers, stack pointer, base pointer and
index registers, ALU, flag registers (FLAGS), instruction decoder and timing and
control unit.
o Let’s see each block in detail:

1. General Purpose Registers: There are four 16-bit general purpose registers Used
for arithmetic, logic, and data operations: AX (Accumulator Register), BX (Base
Register), CX (Counter) and DX. Each of these 16-bit registers are further
subdivided into 8-bit registers as shown below:
16-bit registers 8-bit high-order registers 8-bit low-order registers

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AX AH AL
BX BH BL
CX CH CL
DX DH DL
2. Index Register: The following four registers are in the group of pointer and index
registers:
o Stack Pointer (SP): Used to point to the top of the stack
o Base Pointer (BP): Used to point to the base of the stack
o Source Index (SI): Used for source indexed addressing for string
operations.
o Destination Index (DI): Used for destination indexed addressing for string
operations.
3. ALU: It handles all arithmetic and logical operations. Such as addition, subtraction,
multiplication, division, AND, OR, NOT operations.
4. Flag Register: It is a 16-bit register which exactly behaves like a flip-flop, means it
changes states according to the result stored in the accumulator. It has 9 flags and
they are divided into 2 groups i.e. conditional and control flags.
5. Conditional Flags: This flag represents the result of the last arithmetic or logical
instruction executed. Conditional flags are:
o Carry Flag
o Auxiliary Flag
o Parity Flag
o Zero Flag
o Sign Flag
o Overflow Flag
6. Control Flags: It controls the operations of the execution unit. Control flags are:
o Trap Flag
o Interrupt Flag
o Direction Flag

Register Organization:
1. General Purpose Registers: There are four 16-bit general purpose: AX
(Accumulator Register), BX (Base Register), CX (Counter) and DX. Each of
these 16-bit registers are further subdivided into 8-bit registers
2. AX, BX, CX, DX: Used for arithmetic, logic, and data operations
3. Segment Registers:
o CS, DS, SS, ES: Hold base addresses of code, data, stack, and extra
segments.
4. Pointer and Index Registers:
o SP, BP: Stack-related operations.
o SI, DI: Used for indexed addressing and string operations.
5. Flag Register:
o Status flags (e.g., Zero Flag, Sign Flag) and control flags (e.g., Interrupt Flag).

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1.3 Concept of Pipelining

 Definition: Technique where multiple instruction phases (fetch, decode, execute)

are overlapped to increase throughput.
 Working in 8086:
o BIU fetches instructions and queues them in a 6-byte instruction queue.
o EU decodes and executes instructions from the queue.
 Advantages:
o Faster execution and better utilization of processor resources.
 Limitation:
o Dependent instructions may cause pipeline stalls.

1.4 Memory Segmentation and Physical Memory Address Generation

Memory Segmentation:

 Definition: Divides memory into segments for better organization and protection.
 Segment Types:
o Code Segment (CS): Stores program instructions.
o Data Segment (DS): Stores data variables.
o Stack Segment (SS): Holds stack-related data.
o Extra Segment (ES): Additional data storage.
 Advantages:
o Easier program and data management.
o Supports modular programming.

Physical Memory Address Generation:

 Calculation: Physical Address = (Segment Address × 16) + Offset.

 Example:
o CS = 1234H, IP = 5678H
o Physical Address = (1234H × 10H) + 5678H = 179B8H.
 Allows addressing up to 1 MB of memory using 20-bit addressing.

1.1 Intel 8086 Microprocessor:

 Intel 8086 microprocessor is the enhanced version of Intel 8085 microprocessor. It
was designed by Intel in 1976.
 The 8086 microprocessor is a16-bit, N-channel, HMOS microprocessor. Where the
HMOS is used for "High-speed Metal Oxide Semiconductor".
 Intel 8086 is built on a single semiconductor chip and packaged in a 40-pin IC
package. The type of package is DIP (Dual Inline Package).
 Intel 8086 uses 20 address lines and 16 data- lines. It can directly address up to 2 20 =
1 Mbyte of memory.

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 It consists of a powerful instruction set, which provides operation like division and
multiplication very quickly.
 8086 is designed to operate in two modes, i.e., Minimum and Maximum mode.

 8086 does not have a RAM or ROM inside it. However, it has internal
registers for storing intermediate and final results and interfaces with
memory located outside it through the System Bus.
 In the case of 8086, it is a 16-bit Integer processor in a 40-pin, Dual
Inline Packaged IC.
 The size of the internal registers(present within the chip) indicates how
much information the processor can operate on at a time (in this case 16-
bit registers) and how it moves data around internally within the chip,
sometimes also referred to as the internal data bus.
 8086 provides the programmer with 14 internal registers, each of 16 bits or
2 bytes wide. The main advantage of the 8086 microprocessor is
that it supports Pipelining.

Architecture of 8086: The following diagram depicts the architecture of a 8086 Microprocessor –

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8086 Microprocessor Components:

It is a 16-bit microprocessor.

It has a 20-bit address line.

It has a 16-bit data bus.

The memory capacity is 1 MB.

The Clock speed of this microprocessor varies between 5, 8 and 10 MHz for different versions.

It has nine flags.

8086 microprocessor supports memory segmentation.

It supports pipelining.

It is general purpose register based processor.

It has minimum and maximum modes.

In 8086, more than one processor is used. An additional external processor can also be employed.

It contains more number of transistors compare to 8085 microprocessor. It contains about 29000 in size.

The cost of 8086 is high.

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Architecture of Intel 8086 is divided into 2 units: The Bus Interface
Unit (BIU), and The Execution Unit (EU). These are explained as following
below.

1. The Bus Interface Unit (BIU):

It provides the interface of 8086 to external memory and I/O devices via the
System Bus. It performs various machine cycles such as memory read, I/O
read, etc. to transfer data between memory and I/O devices.
BIU performs the following functions are as follows:
It generates the 20-bit physical address for memory access.

 It fetches instructions from the memory.
 It transfers data to and from the memory and I/O.
 Maintains the 6-byte pre-fetch instruction queue(supports
pipelining).
BIU mainly contains the 4 Segment registers, the Instruction Pointer, a
pre-fetch queue, and an Address Generation Circuit.
Instruction Pointer (IP):
 It is a 16-bit register. It holds offset of the next instructions in
the Code Segment.
 IP is incremented after every instruction byte is fetched.
 IP gets a new value whenever a branch instruction occurs.
 CS is multiplied by 10H to give the 20-bit physical address of the Code
Segment.
 The address of the next instruction is calculated by using the formula
CS x 10H + IP.
Example:
CS = 4321H IP = 1000H
then CS x 10H = 43210H + offset = 44210H
Here Offset = Instruction Pointer(IP)
This is the address of the next instruction.
Code Segment register: (16 Bit register): CS holds the base address for
the Code Segment. All programs are stored in the Code Segment and
accessed via the IP.
Data Segment register: (16 Bit register): DS holds the base address for
the Data Segment.
Stack Segment register: (16 Bit register): SS holds the base address for
the Stack Segment.
Extra Segment register: (16 Bit register): ES holds the base address for
the Extra Segment.

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Segment registers store starting address of each segments in memory.
Address Generation Circuit:

 The BIU has a Physical Address Generation Circuit.

 It generates the 20-bit physical address using Segment and Offset
addresses using the formula:
 In Bus Interface Unit (BIU) the circuit shown by the Σ symbol is responsible
for the calculation unit which is used to calculate the physical address of
an instruction in memory.
Physical Address = Segment Address x 10H + Offset Address
6 Byte Pre-fetch Queue:
 It is a 6-byte queue (FIFO).
 Fetching the next instruction (by BIU from CS) while executing the
current instruction is called pipelining.
 Gets flushed whenever a branch instruction occurs.
 The pre-Fetch queue is of 6-Bytes only because the maximum size of
instruction that can have in 8086 is 6 bytes. Hence to cover up all
operands and data fields of maximum size instruction in 8086
Microprocessor there is a Pre-Fetch queue is 6 Bytes.
 The pre-Fetch queue is connected with the control unit which is
responsible for decoding op-code and operands and telling the
execution unit what to do with the help of timing and control signals.
 The pre-Fetch queue is responsible for pipelining and because of that
8086 microprocessor is called fetch, decode, execute type
microprocessor. Since there are always instructions present for
decoding and execution in this queue the speed of execution in the
microprocessor is gradually increased.
 When there is a 2-byte space in the instruction pre-fetch queue
then only the next instruction will be pushed into the
queue otherwise if only a 1-byte space is vacant then there will not be
any allocation in the queue. It will wait for a spacing of 2 bytes in
subsequent queue decoding operations.
 Instruction pre-fetch queue works in a sequential manner so if there is
any branch condition then in that situation pre-fetch queue fails. Hence
to avoid chaos instruction queue is flushed out when any branch or
conditional jumps occur.

2.prefetch unit:

The Prefetch Unit in the 8086 microprocessor is a component responsible for

fetching instructions from memory and storing them in a queue. The prefetch
unit allows the 8086 to perform multiple instruction fetches in parallel,
improving the overall performance of the microprocessor.
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The prefetch unit consists of a buffer and a program counter that are used to
fetch instructions from memory. The buffer stores the instructions that have
been fetched and the program counter keeps track of the memory location of
the next instruction to be fetched. The prefetch unit fetches several
instructions ahead of the current instruction, allowing the 8086 to execute
instructions from the buffer rather than from memory.
This parallel processing of instruction fetches helps to reduce the wait time
for memory access, as the 8086 can continue to execute instructions from the
buffer while it waits for memory access to complete. This results in improved
overall performance, as the 8086 is able to execute more instructions in a
given amount of time.
The prefetch unit is an important component of the 8086 microprocessor, as
it allows the microprocessor to work more efficiently and perform more
instructions in a given amount of time. This improved performance helps to
ensure that the 8086 remains competitive in its performance and capabilities,
even as technology continues to advance.

3. The Execution Unit (EU):

The main components of the EU are General purpose registers, the ALU,
Special purpose registers, the Instruction Register and Instruction Decoder,
and the Flag/Status Register.
1. Fetches instructions from the Queue in BIU, decodes, and executes
arithmetic and logic operations using the ALU.
2. Sends control signals for internal data transfer operations within the
microprocessor.(Control Unit)
3. Sends request signals to the BIU to access the external module.
4. It operates with respect to T-states (clock cycles) and not machine
cycles.
8086 has four 16-bit general purpose registers AX, BX, CX, and DX which
store intermediate values during execution. Each of these has two 8-bit parts
(higher and lower).
 AX register: (Combination of A L and AH Registers)
It holds operands and results during multiplication and division
operations. Also an accumulator during String operations.

 BX register: (Combination of BL and BH Registers)

It holds the memory address (offset address) in indirect addressing
modes.

 CX register: (Combination of CL and CH Registers)

It holds the count for instructions like a loop, rotates, shifts and string
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operations.

 DX register: (Combination of DL and DH Registers)

It is used with AX to hold 32-bit values during multiplication and
division.

Arithmetic Logic Unit (16-bit): Performs 8 and 16-bit arithmetic and logic
operations.
Special purpose registers (16-bit): Special purpose registers are called
Offset registers also. Which points to specific memory locations under each
segment.
We can understand the concept of segments as Textbook pages. Suppose
there are 10 chapters in one textbook and each chapter takes exactly 100
pages. So the book will contain 1000 pages. Now suppose we want to access
page number 575 from the book then 500 will be the segment base address
which can be anything in the context of microprocessors like Code, Data,
Stack, and Extra Segment. So 500 will be segment registers that are present
in Bus Interface Unit (BIU). And 500 + 75 is called an offset register through
which we can reach on specific page number under a specific segment.
Hence 500 is the segment base address and 75 is an offset address or
(Instruction Pointer, Stack Pointer, Base Pointer, Source Index, Destination
Index) any of the above according to their segment implementation.
 Stack Pointer: Points to Stack top. Stack is in Stack Segment, used
during instructions like PUSH, POP, CALL, RET etc.
 Base Pointer: BP can hold the offset addresses of any location in the
stack segment. It is used to access random locations of the stack.
 Source Index: It holds offset address in Data Segment during string
operations.
 Destination Index: It holds offset address in Extra Segment during
string operations.
Instruction Register and Instruction Decoder:
The EU fetches an opcode from the queue into the instruction register. The
instruction decoder decodes it and sends the information to the control circuit
for execution.

Flag/Status register (16 bits) : It has 9 flags that help change or recognize
the state of the microprocessor.

6 Status flags:
1. Carry flag(CF)
2. Parity flag(PF)
3. Auxiliary carry flag(AF)
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4. Zero flag(Z)
5. Sign flag(S)
6. Overflow flag (O)
Status flags are updated after every arithmetic and logic operation.
3 Control flags:
1. Trap flag(TF)
2. Interrupt flag(IF)
3. Direction flag(DF)
These flags can be set or reset using control instructions like CLC, STC, CLD,
STD, CLI, STI, etc. The Control flags are used to control certain operations.
4.Decode unit:
The Decode Unit in the 8086 microprocessor is a component that decodes the
instructions that have been fetched from memory. The decode unit takes the
machine code instructions and translates them into micro-operations that can
be executed by the microprocessor’s execution unit.
The Decode Unit works in parallel with the Prefetch Unit, which fetches
instructions from memory and stores them in a queue. The Decode Unit reads
the instructions from the queue and translates them into micro-operations
that can be executed by the microprocessor.
The Decode Unit is an important component of the 8086 microprocessor, as it
allows the microprocessor to execute instructions efficiently and accurately.
The decode unit ensures that the microprocessor can execute complex
instructions, such as jump instructions and loop instructions, by translating
them into a series of simple micro-operations.
The Decode Unit is responsible for decoding instructions, performing register-
to-register operations, and performing memory-to-register operations. It also
decodes conditional jumps, calls, and returns, and performs data transfers
between memory and registers.
The Decode Unit helps to improve the performance of the 8086
microprocessor by allowing it to execute instructions quickly and accurately.
This improved performance helps to ensure that the 8086 remains
competitive in its performance and capabilities, even as technology continues
to advance.

5.control unit :

The Control Unit in the 8086 microprocessor is a component that manages

the overall operation of the microprocessor. The control unit is responsible for
controlling the flow of instructions through the microprocessor and

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coordinating the activities of the other components, including the Decode
Unit, Execution Unit, and Prefetch Unit.
The Control Unit acts as the central coordinator for the microprocessor,
directing the flow of data and instructions and ensuring that the
microprocessor operates correctly. It also monitors the state of the
microprocessor, ensuring that the correct sequence of operations is followed.
The Control Unit is responsible for fetching instructions from memory,
decoding them, executing them, and updating the microprocessor’s state. It
also handles interrupt requests and performs system management tasks,
such as power management and error handling.
The Control Unit is an essential component of the 8086 microprocessor, as it
allows the microprocessor to operate efficiently and accurately. The control
unit ensures that the microprocessor can execute complex instructions, such
as jump instructions and loop instructions, by coordinating the activities of
the other components.
The Control Unit helps to improve the performance of the 8086
microprocessor by managing the flow of instructions and data through the
microprocessor, ensuring that the microprocessor operates correctly and
efficiently. This improved performance helps to ensure that the 8086 remains
competitive in its performance and capabilities, even as technology continues
to advance.

The 8086 microprocessor uses three different buses to transfer data

and instructions between the microprocessor and other components
in a computer system. These buses are:

1.Address Bus: The address bus is used to send the memory address of the
instruction or data being read or written. The address bus is 16 bits wide,
allowing the 8086 to address up to 64 kilobytes of memory.
2.Data Bus: The data bus is used to transfer data between the
microprocessor and memory. The data bus is 16 bits wide, allowing the 8086
to transfer 16-bit data words at a time.
3.Control Bus: The control bus is used to transfer control signals between
the microprocessor and other components in the computer system. The
control bus is used to send signals such as read, write, and interrupt requests,
and to transfer status information between the microprocessor and other
components.
The buses in the 8086 microprocessor play a crucial role in allowing the
microprocessor to access and transfer data from memory, as well as to
interact with other components in the computer system. The 8086’s ability to
use these buses efficiently and effectively helps to ensure that it remains
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competitive in its performance and capabilities, even as technology continues
to advance.
Execution of whole 8086 Architecture:
1. All instructions are stored in memory hence to fetch any instruction
first task is to obtain the Physical address of the instruction is to be
fetched. Hence this task is done by Bus Interface Unit (BIU) and by
Segment Registers. Suppose the Code segment has a Segment
address and the Instruction pointer has some offset address then the
physical address calculator circuit calculates the physical address in
which our instruction is to be fetched.
2. After the address calculation instruction is fetched from memory and
it passes through C-Bus (Data bus) as shown in the figure, and
according to the size of the instruction, the instruction pre-fetch
queue fills up. For example MOV AX, BX is 1 Byte instruction so it will
take only the 1st block of the queue, and MOV BX,4050H is 3 Byte
instruction so it will take 3 blocks of the pre-fetch queue.
3. When our instruction is ready for execution, according to the FIFO
property of the queue instruction comes into the control system or
control circuit which resides in the Execution unit. Here instruction
decoding takes place. The decoding control system generates an
opcode that tells the microprocessor unit which operation is to be
performed. So the control system sends signals all over the
microprocessor about what to perform and what to extract from
General and Special Purpose Registers.
4. Hence after decoding microprocessor fetches data from GPR and
according to instructions like ADD, SUB, MUL, and DIV data residing in
GPRs are fetched and put as ALU’s input. and after that addition,
multiplication, division, or subtraction whichever calculation is to be
carried out.
5. According to arithmetic, flag register values change dynamically.
6. While Instruction was decoding and executing from step-3 of
our algorithm, the Bus interface Unit doesn’t remain idle. it
continuously fetches an instruction from memory and put it in
a pre-fetch queue and gets ready for execution in a FIFO
manner whenever the time arrives.
7. So in this way, unlike the 8085 microprocessor, here the fetch,
decode, and execution process happens in parallel and not
sequentially. This is called pipelining, and because of the instruction
pre-fetch queue, all fetching, decoding, and execution process happen
side-by-side. Hence there is partitioning in 8086 architecture like Bus
Interface Unit and Execution Unit to support Pipelining phenomena.

Advantages of Architecture of 8086:

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Akhil M. Jaiswal 9028637523
The architecture of the 8086 microprocessor provides several advantages,
including:
1. Wide range of instructions: The 8086 microprocessor supports a wide
range of instructions, allowing programmers to write complex
programs that can perform many different operations.
2. Segmented memory architecture: The segmented memory
architecture allows the 8086 microprocessor to address large
amounts of memory, up to 1 MB, while still using a 16-bit data bus.
3. Powerful instruction set: The instruction set of the 8086
microprocessor includes many powerful instructions that can perform
multiple operations in a single instruction, reducing the number of
instructions needed to perform a given task.
4. Multiple execution units: The 8086 microprocessor has two main
execution units, the execution unit and the bus interface unit, which
work together to efficiently execute instructions and manage data
transfer.
5. Rich set of registers: The 8086 microprocessor has a rich set of
registers, including general-purpose registers, segment registers, and
special registers, allowing programmers to efficiently manipulate data
and control program flow.
6. Backward compatibility: The architecture of the 8086 microprocessor
is backward compatible with earlier 8-bit microprocessors, allowing
programs written for these earlier microprocessors to be easily ported
to the 8086 microprocessor.

Dis-advantages of Architecture of 8086:

The architecture of the 8086 microprocessor has some disadvantages,
including:
1. Complex programming: The architecture of the 8086 microprocessor
is complex and can be difficult to program, especially for novice
programmers who may not be familiar with the assembly language
programming required for the 8086 microprocessor.
2. Segmented memory architecture: While the segmented memory
architecture allows the 8086 microprocessor to address a large
amount of memory, it can be difficult to program and manage, as it
requires programmers to use both segment registers and offsets to
address memory.
3. Limited performance: The 8086 microprocessor has a limited
performance compared to modern microprocessors, as it has a slower
clock speed and a limited number of execution units.
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Akhil M. Jaiswal 9028637523
4. Limited instruction set: While the 8086 microprocessor has a wide
range of instructions, it has a limited instruction set compared to
modern microprocessors, which can limit its functionality and
performance in certain applications.
5. Limited memory addressing: The 8086 microprocessor can only
address up to 1 MB of memory, which can be limiting in applications
that require large amounts of memory.
6. Lack of built-in features: The 8086 microprocessor lacks some built-in
features that are commonly found in modern microprocessors, such
as hardware floating-point support and virtual memory management.

What is Pipelining?
To grasp the concept of pipelining let us look at the root level of how the program is
executed. Instruction is the smallest execution packet of a program. Each instruction
contains one or more operations. Simple scalar processors execute one or more
instruction per clock cycle, with each instruction containing only one operation.
Instructions are executed as a sequence of phases, to produce the expected results. This
sequence is given below

Instruction Execution Sequence

 IF: Fetches the instruction into the instruction register.

 ID: Instruction Decode, decodes the instruction for the opcode.
 AG: Address Generator, generates the address.
 DF: Data Fetch, fetches the operands into the data register.
 EX: Execution, executes the specified operation.
 WB: Write back, writes back the result to the register.
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Akhil M. Jaiswal 9028637523

Not all instructions require all the above steps but most do. These steps use different
hardware functions. In pipelining these different phases are performed concurrently. In
pipelining these phases are considered independent between different operations and can
be overlapped. Thus, multiple operations can be performed simultaneously with each
operation being in its own independent phase.

Instruction Pipelining
Let us look the way instructions are processed in pipelining. This can be easily understood
by the diagram below.

Instruction Pipelining

Assume that the instructions are independent. In simple pipelining processor, at a given
time, there is only one operation in each phase. The initial phase is the IF phase. So, at
the first clock cycle, one operation is fetched. When the next clock pulse arrives, the first
operation goes into the ID phase leaving the IF phase empty. Now, this empty phase is
allocated to the next operation. So, during the second clock pulse first operation is in the
ID phase and the second operation is in the IF phase.

For the third cycle, the first operation will be in AG phase, the second operation will be in
the ID phase and the third operation will be in the IF phase. In this way, instructions are
executed concurrently and after six cycles the processor will output a completely executed
instruction per clock cycle.

Has this instruction executed sequentially, initially the first instruction has to go through all
the phases then the next instruction would be fetched? So, for execution of each
instruction, the processor would require six clock cycles. But in a pipelined processor as
the execution of instructions takes place concurrently, only the initial instruction requires
six cycles and all the remaining instructions are executed as one per each cycle thereby
reducing the time of execution and increasing the speed of the processor.

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Akhil M. Jaiswal 9028637523
Advantages of Pipelining
 Instruction throughput increases.
 Increase in the number of pipeline stages increases the number of instructions
executed simultaneously.
 Faster ALU can be designed when pipelining is used.
 Pipelined CPU’s works at higher clock frequencies than the RAM.
 Pipelining increases the overall performance of the CPU.
Disadvantages of Pipelining
 Designing of the pipelined processor is complex.
 Instruction latency increases in pipelined processors.
 The throughput of a pipelined processor is difficult to predict.
 The longer the pipeline, worse the problem of hazard for branch instructions.

8086 pins configuration

The description of the pins of 8086 is as follows:

Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip.

It uses a 5V DC supply for its operation. The 8086 uses a 20-line address bus.
It has a 16-line data bus. The 20 lines of the address bus operate in
multiplexed mode. The 16-low order address bus lines have been multiplexed
with data and 4 high-order address bus lines have been multiplexed with
status signals.
AD0-AD15: Address/Data bus. These are low order address bus. They are
multiplexed with data. When AD lines are used to transmit memory address
the symbol A is used instead of AD, for example A0-A15. When data are
transmitted over AD lines the symbol D is used in place of AD, for example
D0-D7, D8-D15 or D0-D15.

A16-A19: High order address bus. These are multiplexed with status signals.

S2, S1, S0: Status pins. These pins are active during T4, T1 and T2 states
and is returned to passive state (1,1,1 during T3 or Tw (when ready is
inactive). These are used by the 8288 bus controller for generating all the
memory and I/O operation) access control signals. Any change in S2, S1, S0
during T4 indicates the beginning of a bus cycle.

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Akhil M. Jaiswal 9028637523

S S S Characteristic
2 1 0 s

Interrupt
0 0 0
acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory

1 1 1 Passive state

A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are

multiplexed with corresponding status signals.
A17/ A16/
S4 S3 Function

Extra segment
0 0
access

Stack segment
0 1
access

Code segment
1 0
access

1 1 Data segment

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Akhil M. Jaiswal 9028637523

A17/ A16/
S4 S3 Function

access

BHE’/S7: Bus High Enable/Status. During T1 it is low. It is used to enable data

onto the most significant half of data bus, D8-D15. 8-bit device connected to
upper half of the data bus use BHE (Active Low) signal. It is multiplexed with
status signal S7. S7 signal is available during T2, T3 and T4.
RD’: This is used for read operation. It is an output signal. It is active when
low.
READY : This is the acknowledgement from the memory or slow device that
they have completed the data transfer. The signal made available by the
devices is synchronized by the 8284A clock generator to provide ready input
to the microprocessor. The signal is active high(1).
INTR : Interrupt Request. This is triggered input. This is sampled during the
last clock cycles of each instruction for determining the availability of the
request. If any interrupt request is found pending, the processor enters the
interrupt acknowledge cycle. This can be internally masked after resulting the
interrupt enable flag. This signal is active high(1) and has been synchronized
internally.
NMI : Non maskable interrupt. This is an edge triggered input which results in
a type II interrupt. A subroutine is then vectored through an interrupt vector
lookup table which is located in the system memory. NMI is non-maskable
internally by software. A transition made from low(0) to high(1) initiates the
interrupt at the end of the current instruction. This input has been
synchronized internally.
INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each
interrupt acknowledge cycle.
MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the
processor will operate in.
RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by local bus
masters used to force the microprocessor to release the local bus at the end
of the microprocessor’s current bus cycle. Each of the pin is bi-directional.
RQ’/GT0′ have higher priority than RQ’/GT1′.
LOCK’ : Its an active low pin. It indicates that other system bus masters have
not been allowed to gain control of the system bus while LOCK’ is active
low(0). The LOCK signal will be active until the completion of the next
instruction.
TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0),
execution will continue, else the processor remains in an idle state. The input

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Akhil M. Jaiswal 9028637523
is internally synchronized during each of the clock cycle on leading edge of
the clock.
CLK : Clock Input. The clock input provides the basic timing for processing
operation and bus control activity. Its an asymmetric square wave with a 33%
duty cycle.
RESET : This pin requires the microprocessor to terminate its present activity
immediately. The signal must be active high(1) for at least four clock cycles.
Vcc : Power Supply( +5V D.C.)
GND : Ground
QS1,QS0 : Queue Status. These signals indicate the status of the internal
8086 instruction queue according to the table shown below:
QS QS
1 0 Status

0 0 No operation

First byte of op code from

0 1
queue

1 0 Empty the queue

Subsequent byte from

1 1
queue

M/IO’: This signal is used to distinguish between memory and I/O operations.
The M Signal is Active high whereas the IO’ Signal is Active Low. When this Pin
is High, the memory operations takes place. On the other hand, when the Pin
is low, the Input/Output operations from the peripheral devices takes place.
=DT/R : Data Transmit/Receive. This pin is required in minimum systems,
that want to use an 8286 or 8287 data bus transceiver. The direction of data
flow is controlled through the transceiver.
DEN: Data enable. This pin is provided as an output enable for the 8286/8287
in a minimum system which uses transceiver. DEN is active low(0) during
each memory and input-output access and for INTA cycles.
HOLD/HOLDA: HOLD indicates that another master has been requesting a
local bus .This is an active high(1). The microprocessor receiving the HOLD
request will issue HLDA (high) as an acknowledgement in the middle of a T4
or T1 clock cycle.

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Akhil M. Jaiswal 9028637523
ALE : Address Latch Enable. ALE is provided by the microprocessor to latch
the address into the 8282 or 8283 address latch. It is an active high(1) pulse
during T1 of any bus cycle. ALE signal is never floated, is always integer.

Conclusion
The 8086 chip addresses a milestone in the development of PC innovation,
presenting a 16-bit design that laid the foundation for future progressions. Its
capacity to address up to 1 MB of memory and its fragmented memory model
gave huge enhancements in figuring power and effectiveness. Understanding
its pin outline and inward construction is fundamental for both authentic
setting and viable applications in framework plan and investigating. The
tradition of the 8086 is apparent in its impact on resulting processors and its
part in forming the advancement of current registering frameworks.
The description of the pins of 8086 is as follows:

AD0-AD15 (Address Data Bus): Bidirectional address/data lines. These are low order
address bus. They are multiplexed with data.

When these lines are used to transmit memory address, the symbol A is used instead of AD,
for example, A0- A15.

A16 - A19 (Output): High order address lines. These are multiplexed with status signals.

A16/S3, A17/S4: A16 and A17 are multiplexed with segment identifier signals S3 and S4.

A18/S5: A18 is multiplexed with interrupt status S5.

A19/S6: A19 is multiplexed with status signal S6.

BHE/S7 (Output): Bus High Enable/Status. During T1, it is low. It enables the data onto the
most significant half of data bus, D8-D15. 8-bit device connected to upper half of the data
bus use BHE signal. It is multiplexed with status signal S7. S7 signal is available during T3
and T4.

RD (Read): For read operation. It is an output signal. It is active when LOW.

Ready (Input): The addressed memory or I/O sends acknowledgment through this pin.
When HIGH, it denotes that the peripheral is ready to transfer data.

RESET (Input): System reset. The signal is active HIGH.

CLK (input): Clock 5, 8 or 10 MHz.

INTR: Interrupt Request.

NMI (Input): Non-maskable interrupt request.

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 Akhil M. Jaiswal 9028637523
TEST (Input): Wait for test control. When LOW the microprocessor continues execution
otherwise waits.

VCC: Power supply +5V dc.

GND: Ground.

General purpose registers in 8086

microprocessor




It is one of the most important chips ever created due

to its part in the development of x86-based
architecture. One significant aspect of this
microprocessor is that it contains general registers.
Efficiency and speed of computations in the processor
are influenced by these registers since they determine
arithmetic operations execution and data
manipulations. Understanding such registers is
important for code optimization as well as assembly
language programming and system design.
The 8086 microprocessor contains a set of 16-bit
general-purpose registers which are used for
performing various arithmetic, logical, and data
movement operations. Since these registers are
flexible and can assume different combinations to
perform various functions, they form the basic
operation units of the processor itself.

26
Akhil M. Jaiswal 9028637523

General-purpose registers are used to store

temporary data within the microprocessor
There are 8 general-purpose registers in the 8086
microprocessor.
1. AX: This is the accumulator. It is of 16 bits and is
divided into two 8-bit registers AH and AL to also
perform 8-bit instructions. It is generally used for
arithmetical and logical instructions but in 8086
27
Akhil M. Jaiswal 9028637523
microprocessor it is not mandatory to have an
accumulator as the destination operand. Example:
ADD AX, AX (AX = AX + AX)
2. BX: This is the base register. It is of 16 bits and is
divided into two 8-bit registers BH and BL to also
perform 8-bit instructions. It is used to store the value
of the offset. Example:
MOV BL, [500] (BL = 500H)
3. CX: This is the counter register. It is of 16 bits and
is divided into two 8-bit registers CH and CL to also
perform 8-bit instructions. It is used in looping and
rotation. Example:
MOV CX, 0005
LOOP
4. DX: This is the data register. It is of 16 bits and is
divided into two 8-bit registers DH and DL to also
perform 8-bit instructions. It is used in the
multiplication and input/output port addressing.
Example:
MUL BX (DX, AX = AX * BX)
5. SP: This is the stack pointer. It is of 16 bits. It
points to the topmost item of the stack. If the stack is
empty the stack pointer will be (FFFE)H. Its offset
address is relative to the stack segment.
It is AB and manage the present position of the top of
the stack.
Example: To push or pop data from the stack in a
function call, the SP is altered.
PUSH R1 ; Decrement the SP and then store the value
of R1 that is at SP.
R1 = POP; R1 = increment SP; R1 = get value in SP
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Akhil M. Jaiswal 9028637523
6. BP – This is the base pointer. It is of 16 bits. It is
primarily used in accessing parameters passed by the
stack. Its offset address is relative to the stack
segment.
MOV AX, [BP+4] ; Access a parameter passed to the
function
(4 bytes above BP in the Stack)
7. SI – This is the source index register. It is of 16 bits.
It is used in the pointer addressing of data and as a
source in some string-related operations. Its offset is
relative to the data segment.
MOV AL, [SI] ; Move the byte at the address pointed
to by SI into the AL register
(used as a pointer to source data).
8.DI – This is the destination index register. It is of 16
bits. It is used in the pointer addressing of data and as
a destination in some string-related operations. Its
offset is relative to the extra segment.
MOV [DI], AL; Move the byte in AL to the address
pointed to by DI
(serves as the destination for the data).
Advantages
 Versatility: The general-purpose registers are
usually useful in arithmetic processing, data
movement and memory addressing making them
quite flexible.
 Efficiency: Data manipulation that is done on
registers is quicker than one that involves memory
and thus more efficient code is created.
 Ease of Use: Registers help to ease programming
operations since they allow direct handling on
29
 Akhil M. Jaiswal 9028637523
operands and result as opposed to requiring the
programmer to deal with memory storage.
Disadvantages
 Limited Number: The 8086 microprocessor for
example has fewer number of general purpose
registers that are suitable for organizational use
hence word usage can be restricted by the
limitation of the available registers in the
microprocessor.
 Size Constraints: Both registers are of 16 bits,
and thus not suitable for applications that involve
large data or high precision values in registers.
 Complexity in Management: There is usually a
challenge in managing and optimizing the use of
the available registers in the assembly languages
due to profound knowledge of the processor’s
architecture and available instruction set.

General purpose registers in 8086

microprocessor
Last Updated : 12 Aug, 2024




It is one of the most important chips ever created due

to its part in the development of x86-based
architecture. One significant aspect of this
30
Akhil M. Jaiswal 9028637523
microprocessor is that it contains general registers.
Efficiency and speed of computations in the processor
are influenced by these registers since they determine
arithmetic operations execution and data
manipulations. Understanding such registers is
important for code optimization as well as assembly
language programming and system design.
The 8086 microprocessor contains a set of 16-bit
general-purpose registers which are used for
performing various arithmetic, logical, and data
movement operations. Since these registers are
flexible and can assume different combinations to
perform various functions, they form the basic
operation units of the processor itself.

31
Akhil M. Jaiswal 9028637523

General-purpose registers are used to store

temporary data within the microprocessor
There are 8 general-purpose registers in the 8086
microprocessor.
1. AX: This is the accumulator. It is of 16 bits and is
divided into two 8-bit registers AH and AL to also
perform 8-bit instructions. It is generally used for
arithmetical and logical instructions but in 8086
32
Akhil M. Jaiswal 9028637523
microprocessor it is not mandatory to have an
accumulator as the destination operand. Example:
ADD AX, AX (AX = AX + AX)
2. BX: This is the base register. It is of 16 bits and is
divided into two 8-bit registers BH and BL to also
perform 8-bit instructions. It is used to store the value
of the offset. Example:
MOV BL, [500] (BL = 500H)
3. CX: This is the counter register. It is of 16 bits and
is divided into two 8-bit registers CH and CL to also
perform 8-bit instructions. It is used in looping and
rotation. Example:
MOV CX, 0005
LOOP
4. DX: This is the data register. It is of 16 bits and is
divided into two 8-bit registers DH and DL to also
perform 8-bit instructions. It is used in the
multiplication and input/output port addressing.
Example:
MUL BX (DX, AX = AX * BX)
5. SP: This is the stack pointer. It is of 16 bits. It
points to the topmost item of the stack. If the stack is
empty the stack pointer will be (FFFE)H. Its offset
address is relative to the stack segment.
It is AB and manage the present position of the top of
the stack.
Example: To push or pop data from the stack in a
function call, the SP is altered.
PUSH R1 ; Decrement the SP and then store the value
of R1 that is at SP.
R1 = POP; R1 = increment SP; R1 = get value in SP
33
Akhil M. Jaiswal 9028637523
6. BP – This is the base pointer. It is of 16 bits. It is
primarily used in accessing parameters passed by the
stack. Its offset address is relative to the stack
segment.
MOV AX, [BP+4] ; Access a parameter passed to the
function
(4 bytes above BP in the Stack)
7. SI – This is the source index register. It is of 16 bits.
It is used in the pointer addressing of data and as a
source in some string-related operations. Its offset is
relative to the data segment.
MOV AL, [SI] ; Move the byte at the address pointed
to by SI into the AL register
(used as a pointer to source data).
8.DI – This is the destination index register. It is of 16
bits. It is used in the pointer addressing of data and as
a destination in some string-related operations. Its
offset is relative to the extra segment.
MOV [DI], AL; Move the byte in AL to the address
pointed to by DI
(serves as the destination for the data).
Advantages
 Versatility: The general-purpose registers are
usually useful in arithmetic processing, data
movement and memory addressing making them
quite flexible.
 Efficiency: Data manipulation that is done on
registers is quicker than one that involves memory
and thus more efficient code is created.
 Ease of Use: Registers help to ease programming
operations since they allow direct handling on
34
Akhil M. Jaiswal 9028637523
operands and result as opposed to requiring the
programmer to deal with memory storage.
Disadvantages
 Limited Number: The 8086 microprocessor for
example has fewer number of general purpose
registers that are suitable for organizational use
hence word usage can be restricted by the
limitation of the available registers in the
microprocessor.
 Size Constraints: Both registers are of 16 bits,
and thus not suitable for applications that involve
large data or high precision values in registers.
 Complexity in Management: There is usually a
challenge in managing and optimizing the use of
the available registers in the assembly languages
due to profound knowledge of the processor’s
architecture and available instruction set.

35
Akhil M. Jaiswal 9028637523

Types of Registers in 8086

Microprocessor
Registers are storage blocks for temporary storage
in microprocessors. They hold important information
temporarily while the microprocessor works on it.
Think of registers as tiny boxes where the
microprocessor keeps things it needs to use right
away.
In other words, one may also say that registers are
like the memory of a computer's brain, storing tiny
bits of information that the microprocessor needs to
work with quickly.
In 8086 microprocessor, the registers are categorized
under following four types:
 General Purpose Registers

 Segment Registers

 Special Purpose Registers

 Flag Registers

These different types of registers of 8086

microprocessor are briefly discussed below.
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Akhil M. Jaiswal 9028637523

General Purpose Registers

The general purpose registers are present in
execution unit of 8086 microprocessor. These are
versatile registers that can be used for various tasks,
such as storing numbers for calculations or holding
memory addresses for data access. Each register
serves a specific purpose, aiding the microprocessor
in different types of tasks.
A general purpose register contains eight registers
namely, AH,AL,BH,BL,CH,CL,DH,DL in which each
register carries 8-bit data. It is used for temporary
storage. When there is requirement to store data is
which greater than 8-bit then these registers are used
in pairs as AX,BX,CX,DX thus it effectively double
their storage capacity. These register pairs can hold a
maximum of 16-bit data.

General Purpose Registers

37
Akhil M. Jaiswal 9028637523
The functions of each general purpose registers are
stated below:
 Accumulator Register(AX):When ALU performs

arithmetic and logical operations then accumulator

register stores the operands of such operations.
 Base Register(BX): The base register is used to

hold the base address of memory location for

reading and writing data into the memory.
 Counter Register(CX): The counter register is

used to hold 8-bit data during the rotate and shift

instructions. It is also used to store loop counter
during loop instructions.
 Data Register(DX): During the multiplication and

division operations, if the result is of 32-bits, then

16 bits from MSB is stored in DX register and bits
from LSB is stored in AX register. This register is
also used to hold the address and instruction for
I/O

Segment Registers
The Bus Interface Unit (BIU) of 8086 microprocessor.
The segment registers are responsible for managing
memory access. As the computer memory is
segmented, the segment registers tracks the memory
location of each and every segment. The segment
registers contains four 16-bit registers namely, Code
Segment(CS), Data Segment(DS), Stack segment(SS)
and Extra Segment(ES). These registers are used to
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Akhil M. Jaiswal 9028637523
hold the 16 bits of starting address. Each segment
register holds the starting address of its respective
memory segment, allowing the microprocessor to
quickly locate and access the data it needs during
program execution.

Segment Registers

The function of each segment registers are stated

below:
 Code Segment(CS): This register is used to store

the address of the memory in which the program

which is to be executed is stored.
 Data Segment(DS): It is used to data which is

used by the program frequently. It also stores the

offset address or the data of the register that holds
the offset address.

39
Akhil M. Jaiswal 9028637523
 Stack Segment(SS): It is used to store the
address as well as data in the memory while the
subprogram is executing.
 Extra Segment(ES): This register is used to hold
the extra data by providing additional data
segment in the memory.

Special Purpose Registers

The index and pointer registers are collectively called
as special purpose registers. These are 16-bit
registers used as memory pointers and These
registers generates 20- bit physical address. There
are five 16-bit special purpose registers namely,
Stack Pointer(SP), Base Pointer(BP), Source Index(SI),
Destination Index(DI) and Instruction Pointer(IP).

Special Purpose Registers

40
Akhil M. Jaiswal 9028637523
The function of each general purpose registers are
stated below:
 Stack Pointer(SP): Stack Pointer register is used

to hold the topmost address of the stack memory,

i.e., it stores the address of the memory location in
which data was recently stored.
 Base Pointer(BP): It is used to store the base

address of the memory.

 Source Index(SI): It is a memory pointer which is

used to store the offset address of the source.

 Destination Index(DI): It is a memory pointer

which is used to store the offset address of the

destination.
 Instruction Pointer(IP): This register is used to

hold the address of the next instruction which is to

be executed.

Flag Register
The flag register is also called as status register. It is
a 16-bit register which is a set of flip-flops. There are
nine flags in this register.

Flag
Register

The flag register is classified into two categories:

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Akhil M. Jaiswal 9028637523

Conditional Flags
These flags are used to hold the result obtained by
ALU i.e., by arithmetical and logical operations. There
are six conditional flags:
 Carry Flag(CF): If any arithmetic operation results

in the production of carry in the MSB position then

this extra bit is stored in the carry flag. The carry
flag is set i.e. 1 when the carry is generated,
otherwise is reset, i.e. 0.
 Auxiliary Carry Flag(AF): If the carry is

generated in the 4th bit from the LSB then that

carry is called as auxiliary carry. The auxiliary carry
flag is set i.e. 1 when the auxiliary carry carry is
generated, otherwise is reset, i.e. 0.
 Parity Flag(PF): This flag is used to store the

parity of the result of any arithmetic and logical

operation. The value of parity flag is 1 (i.e., set)
when the result is of even parity(the number of 1's
in result is odd) whereas the value of parity flag is
0(i.e., reset) when the result is of odd parity(the
number of 1's in result is even).
 Zero Flag(ZF): If the result of any arithmetic and

logical operations results in zero, then this flag is

set otherwise reset.
 Sign Flag(SF): The value of sign flag is 1 (i.e., set)

when the result of any operation performed by ALU

results in a negative number, whereas its value is 0
(i.e., reset) when the result is a positive number.
 Overflow Flag(OF): If the result is within the

capacity of the register then overflow flag is reset,

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whereas if the result exceeds the value of the
register then the flag is set.
Control Flags
These flags are used to control some specific
operations of the processor with the help of some
specific instructions. The 8086 microprocessor
provides three control flags:
 Trap Flag(TF): When the trap flag is set then the

processor will execute the whole program at once,

whereas the trap flag is reset the program will be
executed in step-by-step sequence.
 Interrupt Flag(IF): This flag is set when the

maskable interrupt is enabled, whereas it is reset

when the the maskable interrupt is disabled.
 Direction Flag(DF): This flag is reset when the

bits are accessed from higher memory address to

lower memory address, whereas the direction flag
is reset when the bits are accessed from lower
memory address to higher memory address.

Conclusion
In this article we have gone through the types of
registers in 8086,we have gone through different
types of flags and gone their working in brief. As we
have already seen there are four types of registers in
8086 microprocessor named as General Purpose
Registers, Segment Registers, Special Purpose
Registers and Flag Register.

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