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Processing Unit

• A processor is responsible for reading program instructions

from the computer’s memory and executing them.
• It fetches one instruction at a time.
Chapter 5
• It decodes (interprets) the instruction.
Basic Processing Unit
• Then, it carries out the actions specified.

Processor’s building blocks A digital processing system

• PC provides instruction
Contents of register A are processed and deposited in register B.
address.
• Instruction is fetched
into IR
• Instruction address
generator updates PC
• Control circuitry
interprets instruction
and generates control
signals to perform the
actions needed.

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A multi-stage digital processing system Why multi-stage?

• Processing moves from one stage to the next in each clock

cycle.
• Such a multi-stage system is known as a pipeline.
• High-performance processors have a pipelined organization.
• Pipelining enables the execution of successive instructions to
be overlapped.
• Pipelining will be discussed later.

Instruction execution A memory access instruction: Load R5, X(R7)

• Pipelined organization is most effective if all instructions can
be executed in the same number of steps.
1. Fetch the instruction and increment the program counter.
• Each step is carried out in a separate hardware stage.
2. Decode the instruction and read the contents of register R7
• Processor design will be illustrated using five hardware stages. in the register file.
• How can instruction execution be divided into five steps? 3. Compute the effective address.
4. Read the memory source operand.
5. Load the operand into the destination register, R5.

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A computational instruction: Add R3, R4, R5 Summary – Actions to implement an instruction

1. Fetch an instruction and increment the program counter.

1. Fetch the instruction and increment the program counter.
2. Decode the instruction and read registers from the register
2. Decode the instruction and read registers R4 and R5. file.
3. Compute the sum [R4]  [R5]. 3. Perform an ALU operation.
4. No action. 4. Read or write memory data if the instruction involves a
memory operand.
5. Load the result into the destination register, R3.
5. Write the result into the destination register.

• Stage 4 (memory access) is not involved in this instruction.

• This sequence determines the hardware stages needed.

Alternative implementation of 2-port register file

Hardware components: Register file

• A 2-port register file is • Using two single-

needed to read the two ported memory
source registers at the blocks.
same time.
• It may be implemented
using a 2-port memory.

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A conceptual view – computational instructions A conceptual view – immediate instructions

• Both source operands
and the destination
• One of the source
location are in the
operands is the
register file.
immediate value in
the IR.
[RA] and [RB] denote
values of registers [RB]
that are identified by new [RC]
addresses A and B new [RC]
[RA] [RA]

new [RC] denotes the

result that is stored to
the register identified
by address C

A 5-stage implementation of a RISC processor A 5-stage implementation of a RISC processor

• Instruction processing moves

from stage to stage in every
clock cycle, starting with fetch.

• The instruction is decoded and • If a memory operation is

the source registers are read in involved, it takes place in stage
stage 2. 4.

• Computation takes place in • The result of the instruction is

the ALU in stage 3. stored in the destination
register in stage 5.

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The datapath – Stages 2 to 5 Register file – Stages 2 & 5

• Register file, • Address inputs are

used in stages 2 and 5 connected to the
corresponding fields
(Inter-stage registers RA, RB,
in IR.
RZ, RY needed to carry data
from one stage to the next.) • Source registers are read
in stage 2; their contents
• ALU stage
are stored in RA and RB.
• In stage 5, the result of
• Memory stage the instruction is stored
in the destination register
selected by address C.
• Final stage to store result
to the register file

ALU stage Memory stage

• For a memory
• ALU performs
instruction, RZ provides
calculation specified
memory address, and
by the instruction.
MuxY selects read data
• Multiplexer MuxB to be placed in RY.
selects either RB or
• RM provides data for a
the Immediate field
memory write operation.
of IR.
• For a calculation
• Results stored in RZ.
instruction, MuxY selects
• Data to be written in [RZ] to be placed in RY.
the memory are
• Input 2 of MuxY is used
transferred from RB
in subroutine calls.
to RM.

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Memory address generation Processor control section

• MuxMA selects the PC when • When an instruction is

fetching instructions. read, it is placed in IR.
• The Instruction address • The control circuitry
generator increments the PC decodes the instruction.
after fetching an instruction.
• It generates the control
• It also generates branch and signals that drive all units.
subroutine addresses.
• The Immediate block
• MuxMA selects RZ when extends the immediate
reading/writing data operands. operand to 32 bits,
according to the type of
instruction.

Instruction address generator Example: Add R3, R4, R5

• Connections to 1. Memory address  [PC],

registers RY and RA Read memory, IR Memory
are used to support data, PC  [PC]  4
subroutine call and
2. Decode instruction,
return instructions.
RA  [R4], RB  [R5]
3. RZ  [RA]  [RB]
4. RY  [RZ]
5. R3  [RY]

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Example: Load R5, X(R7) Example: Store R6, X(R8)

1. Memory address  [PC], 1. Memory address [PC], Read

Read memory, IR  Memory memory, IR  Memory data,
data, PC [PC]  4 PC  [PC]  4
2. Decode instruction, RA [R7] 2. Decode instruction,
RA [R8], RB [R6]
3. RZ [RA]  Immediate value X
3. RZ [RA]  Immediate value X,
4. Memory address [RZ], Read
RM [RB]
memory, RY  Memory data
4. Memory address [RZ],
5. R5 [RY]
Memory data [RM], Write
memory
5. No action

Unconditional branch Conditional branch: Branch_if_[R5]=[R6] LOOP

1. Memory address [PC], Read memory, IR  Memory data, 1. Memory address [PC], Read memory, IR  Memory data,
PC [PC]  4 PC [PC]  4
2. Decode instruction 2. Decode instruction, RA [R5], RB [R6]
3. PC [PC]  Branch offset 3. Compare [RA] to [RB],
If [RA] = [RB], then PC [PC]  Branch offset
4. No action
4. No action
5. No action
5. No action

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Subroutine call with indirection: Call_register R9 Control signals

1. Memory address [PC], Read memory, IR  Memory data, • Select multiplexer inputs to guide the flow of data.
PC [PC]  4
• Set the function performed by the ALU.
2. Decode instruction, RA [R9]
• Determine when data are written into the PC, the IR,
3. PC-Temp [PC], PC [RA] the register file, and the memory.
4. RY  [PC-Temp] • Inter-stage registers are always enabled because
their contents are only relevant in the cycles for which
5. Register LINK  [RY]
the stages connected to the register outputs are active.

Register file control signals ALU control signals

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Result selection Memory access

• Cache memory described earlier as faster and smaller storage

that is an adjunct to the larger and slower main memory.
• When data are found in the cache, access to memory can be
completed in one clock cycle.
• Otherwise, read and write operations may require several
clock cycles to load data from main memory into the cache.
• A control signal is needed to indicate that memory function
has been completed (MFC). E.g., for step 1:
1. Memory address  [PC], Read memory, Wait for MFC,
IR  Memory data, PC [PC]  4

Memory and IR control signals Control signals of instruction address generator

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Control signal generation Hardwired generation of control signals

• Actions to fetch & execute instructions have been described.

• The necessary control signals have also been described.
• Circuitry must be implemented to generate control signals
so actions take place in correct sequence and at correct time.
• There are two basic approaches:
hardwired control and microprogramming
• Hardwired control involves implementing circuitry that
considers step counter, IR, ALU result, and external inputs.
• Step counter keeps track of execution progress,
one clock cycle for each of the five steps described earlier
(unless a memory access takes longer than one cycle).

CISC processors Hardware organization for a CISC computer

• CISC-style processors have more complex instructions.

• The full collection of instructions cannot all be implemented
in a fixed number of steps.
• Execution steps for different instructions do not all follow
a prescribed sequence of actions.
• Hardware organization should therefore enable
a flexible flow of data and actions to accommodate CISC.

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Bus A 3-bus interconnection network

• An example of an interconnection network.

• When functional units are connected to a common bus,
tri-state drivers are needed.

A 3-bus interconnection network Example: Add R5, R6

1. Memory address [PC], Read memory, Wait for MFC,

IR  Memory data, PC [PC]  4
2. Decode instruction
3. R5 [R5]  [R6]

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Example: And X(R7), R9 Microprogramming

1. Memory address [PC], Read memory, Wait for MFC, • Microprogramming is a software-based approach
IR  Memory data, PC [PC]  4 for the generation of control signals.
2. Decode instruction • The values of the control signals for each clock period are
3. Memory address [PC], Read memory, Wait for MFC, stored in a microinstruction (control word).
Temp1  Memory data, PC [PC]  4
• A processor instruction is implemented by a sequence of
4. Temp2 [Temp1]  [R7] microinstructions that are placed in a control store.
5. Memory address [Temp2], Read memory, Wait for MFC, • From decoding of an instruction in IR, the control circuitry
Temp1  Memory data executes the corresponding sequence of microinstructions.
6. Temp1 [Temp1] AND [R9] • PC maintains the location of the current microinstruction.
7. Memory address [Temp2], Memory data [Temp1],
Write memory, Wait for MFC

Control signals generated from a microprogram Microprogramming

• Microprogramming provides the flexibility needed

to implement more complex instructions in CISC processors.
• However, reading and executing microinstructions incurs
undesirably long delays in high-performance processors.

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