FEATURE ARTICLE by Enoch Hwang

Build a VGA Monitor Controller

Enoch built a VGA monitor controller with just two 10-bit binary up counters, four SR flip-flops,
and 11 AND gates. The result is an impressive solution for displays.

U nderstanding video signals and

building video controller circuits is
why old monitors with slow
scan rates flicker. Row 0
Column 0 Column 639

always a challenge. But things are getting Figure 1 shows that the scan-
easier. I recently took another look at the ning starts from row 0, column 0
Horizontal
VGA video signal and realized that I in the top left corner of the retrace
could build a VGA monitor controller screen and moves to the right VGA Monitor 480 pixels
screen Horizontal per column
with just two binary counters, four flip- until it reaches the last column. scan

flops, and 11 AND gates. Yes, that’s When the scan reaches the end Vertical
retrace
right, just two 10-bit binary up counters, of a row, it retraces to the begin-
four SR flip-flops, and 11 AND gates! ning of the next row. When it
Now, of course, this isn’t a replacement reaches the last pixel in the bot- Row 479

for your high-end graphics card in your tom right corner of the screen,
Figure 1—Scanning starts from row 0, column 0 and moves to the
PC, nor is it even a low-end video card, it retraces back to the top left right and down until reaching row 479, column 639.
but it’s capable of displaying images on a corner and repeats the scanning
standard VGA monitor. Most important- process. In order to reduce flick-
ly, this simple VGA monitor controller er on the screen, the entire screen must chronization, and vertical synchroniza-
circuit allows you to easily understand be scanned 60 times per second (or more). tion. The three color signals, collectively
how the VGA monitor works and how to During the horizontal and the vertical referred to as the RGB signal, control the
control it. When I presented this to my retraces, all the pixels are turned off. color of a pixel at a given location on
introductory digital logic design class, the screen. They are analog signals with
the students were totally amazed that it FIVE CONTROL SIGNALS voltages ranging from 0 to 0.7 V.
could be this simple. The VGA monitor is controlled by five Different color intensities are obtained
signals: red, green, blue, horizontal syn- by varying the voltage. For simplicity,
PIXELS ON SCREEN your circuit could treat these
To begin, you need to under- a) b)
three color signals as digital
stand how a VGA monitor signals, so you could just turn
works. The monitor screen for each one on or off. As Figure
a standard VGA format con- 2a demonstrates, such a cir-
tains 640 columns by 480 rows cuit would be capable of dis-
of picture elements called pix- playing only eight colors (23 =
els (see Figure 1). An image is 8). Figure 2b shows a slightly
displayed on the screen by enhanced digital-to-analog
turning on and off individual converter circuit that can
pixels. Turning on one pixel display up to 64 colors (26).
doesn’t represent much, but The horizontal and verti-
combining numerous pixels cal synchronization signals
generates an image. The moni- are used to control the tim-
tor continuously scans through ing of the scan rate. Unlike
the entire screen, rapidly turn- the three analog RGB sig-
ing individual pixels on and nals, these two sync signals
off. Although pixels are turned are digital signals. In other
on one at a time, you get the words, they take on either a
impression that all the pix- logic 0 or a logic 1 value.
Figure 2—D/A converter circuits drive the RGB signals.You can use them to produce
els are on because the moni- eight colors (a) or 64 colors (b). The VGA monitor controller controls the digital signals. The horizontal synchro-
tor scans so quickly. This is The analog signals are connected to the VGA monitor via a 15-pin D-Sub connector. nization signal determines

38 Issue 172 November 2004 CIRCUIT CELLAR® www.circuitcellar.com

 horizontal and vertical sync signals
correctly based on the timing dia-
Red, green, blue
640 column pixels
grams shown in Figure 3. You also
Horizontal sync
must keep track of the current row
D
25.42 µs and column counts so that you
B C 640 cycles E
Time and number of 3.77 µs 1.79 µs 0.79 µs know where the scan is. It turns out
25.175-MHz clock cycles 95 cycles 45 cycles 20 cycles that you can do both of these things
31.77 µs
800 cycles
using the same component, which is
the binary up counter. You need two
counters. One is for generating the
Red, green, blue
horizontal sync and keeping tract of
480 horizontal cycles
the column count. The second is for
Vertical sync
generating the vertical sync and
R keeping track of the row count.
15,250 µs
480 cycles
P Q S
Time and number of
64 µs
2 cycles
1,020 µs
32 cycles
450 µs
14 cycles
COUNTING CLOCK CYCLES
horizontal cycles Getting the correct timing for
16,784 µs
528 cycles the two synchronization signals
Figure 3—The horizontal and vertical synchronization signal timing diagram uses a 25.175-MHz clock. Each of the two sig- is simple if you use the correct
nals has four regions: B, C, D, and E for the horizontal sync, and P, Q, R, and S for the vertical sync. Controlling the VGA clock frequency. To obtain the
monitor involves getting the correct timing for the regions. 480 × 640 screen resolution, use a
clock with a 25.175-MHz fre-
the time it takes to scan a row, while the next row scan. The total time to quency. A higher clock frequency is
the vertical synchronization signal complete one row scan is 31.77 µs. needed for a higher screen resolution.
determines the time it takes to scan The timing for the vertical sync signal is For the 25.175-MHz clock, the period
the entire screen. Understanding how analogous to the horizontal one. The 64-µs is the following:
to control a VGA monitor simply boils active low vertical sync signal resets the
1
down to understanding the timings for scan to the top-left corner of the screen
25.175 × 106
these two synchronization signals. By (region P). A 1,020-µs high follows this on
manipulating these two sync signals the signal. Next, there are the 480 31.77-µs or approximately 0.0397 µs per clock
and the three RGB signals, images are row scans, giving a total of 15,250 µs cycle. For region B of the horizontal syn-
formed on the monitor screen. (480 × 31.77), as shown in region R. chronization signal, you need 3.77 µs,
Finally, after the last row scan, there is which is approximately 95 clock cycles
SYNC TIMINGS another 450 µs before the vertical sync (3.77/0.0397). For region C , you need
The horizontal and vertical synchro- signal goes low again to start another 1.79 µs, which is approximately 45 clock
nization signal-timing diagram is shown complete screen scan in the top left cor- cycles. Similarly, you need 640 clock
in Figure 3. When inactive, both synchro- ner. It takes a total of 16,784 µs to com- cycles (region D) for the 640 columns of
nization signals are at a logic 1 value. A plete one full screen scan. pixels and 20 clock cycles for region E.
row scan begins with the horizontal sync To get the monitor operating properly, The total number of clock cycles needed
signal going low for 3.77 µs (region B). A simply get the timing correct for the hori- for each row scan is 800 clock cycles (95 +
1.79-µs high on the signal follows this zontal and vertical sync signals and then 45 + 640 + 20). Notice that with a 25.175-
(region C). Next, the data for the three send out the RGB data for each pixel at MHz clock, region D requires exactly
color signals is sent, one pixel at a time, the right column and row position. For 640 cycles, generating the 640 columns
for the 640 columns for 25.42 µs. Finally, example, if you want to turn on the red per row. If you use a different clock speed,
after the last column pixel, there is anoth- pixel at row 13 and column 48, wait for you will get a different screen resolution.
er 0.79 µs of inactivity on the RGB signal the scan to reach row 13 and column 48 The number of clock cycles required by
lines for the horizontal retrace before the and then set the red signal to logic 1. To the four regions in the horizontal sync
horizontal sync signal goes low again for accomplish this, you need to generate the signal is summarized in Table 1.
Because the vertical sync signal is
analogous to the horizontal sync signal,
B C D E Total
you can perform the same calculations
Time 3.77 µs 1.79 µs 25.42 µs 0.79 µs 31.77 µs
as with the horizontal sync regions to
Number of 25.175-MHz 95 cycles 45 cycles 640 cycles 20 cycles 800 cycles
clock cycles obtain the number of cycles needed for
each vertical region. However, instead of
P Q R S Total
using the number of periods of a 25.175-
Time 64 µs 1,020 µs 15,250 µs 450 µs 16,784 µs
MHz clock, the times for each vertical
Number of horizontal cycles 2 cycles 32 cycles 480 cycles 14 cycles 528 cycles
region are multiples of the horizontal
Table 1—Take a look at the number of cycles needed for the different regions of the horizontal and vertical sync signals. cycle. For example, the time for a hori-

www.circuitcellar.com CIRCUIT CELLAR® Issue 172 November 2004 39

zontal cycle is 31.77 µs, and region P VGA CONTROLLER CIRCUIT
requires 64 µs, which is approximately Two 10-bit binary up counters are
LSB (= 95)
two horizontal cycles (2 × 31.77). Region needed for the horizontal and vertical
Q requires 1,020 µs, which equals 32 hor- sync signals. A 9-bit counter can only
izontal cycles (1,020/31.77). The calcula- count up to 512 (29), but you need to
Figure 4—A 10-input AND gate is connected to test
tion for region R is 480 horizontal cycles count up to 528 and 800 for the verti-
whether or not a number is equal to 95 (0001011111 in
(15,250 µs/31.77 µs). Of course, it has to binary). If the input is 95, the AND gate outputs a one; oth- cal and horizontal sync signals respec-
be exactly 480 times, because you need erwise, it outputs a zero. tively. A 10-bit counter can count up
to have 480 rows per screen. The num- to 1,024 (210). A 10-input AND gate is
ber of horizontal cycles required by the keep H_SYNC_OUT at one. When the used for comparing the count with a
four regions in the vertical sync signal is count reaches 780 (95 + 45 + 640), con- constant. Figure 4 shows the connec-
also summarized in Table 1. tinue to keep H_SYNC_OUT at one. tion of a 10-input AND gate for com-
If you use a 25.175-MHz clock to drive Finally, when the count reaches 800 paring with the constant 95. Because
a counter so that it increments at every (95 + 45 + 640 + 20 ), set H_SYNC_OUT 95 equals 0001011111 in binary, bits
clock cycle, all you have to do to get the to zero, and reset the counter to 6, 8, 9, and 10 (starting from the LSB)
correct horizontal sync signal is count zero. This completes one period of the of the 10-input AND gate are invert-
the correct number of cycles for each H_SYNC_OUT signal. ed. Four such comparators are used for
region. Starting the count at zero, set the Similarly, you can use another counter the four horizontal regions, each con-
horizontal sync signal (H_SYNC_OUT) for the vertical sync signal. The clock for nected according to the ending count
to zero (for low). When the count reaches this counter is derived from the horizon- value that is to be tested.
95, set H_SYNC_OUT to one (for high). tal counter so that the vertical counter Within each region, you need to main-
When the count reaches 140 (95 + 45), counts once for each horizontal cycle. tain the value of the horizontal sync sig-

a) “0000000000” b)
“0000000000”
1 COUNT D9–0
LOAD 10-bit Up counter 1
Clear CLEAR COUNT D9–0
25.175-MHz Clock CLOCK with load LOAD 10-bit Up counter
Q9–0 CLEAR CLEAR
ROLL_OVER CLOCK with load
10 640 = 1010000000 Q9–0
(H_CNT = D)
10 480 = 0111100000
(V_CNT = R)
660 = 1010010100
(H_CNT = D+E)
494 = 0111101110
(V_CNT = R+S)
755 = 1011110011
(H_CNT= D+E+B)
496 = 0111110000
(V_CNT = R+S+P)
800 = 1100100000
(H_CNT= D+E+B+C)
528 = 1000010000
ROLL _OVER (V_CNT = R+S+P+Q)
COLUMN_OUT
10
ROW_OUT
10
c) d)
S Q H_SYNC_OUT
HCOUNT (H_CNT = D)
CLK
25.175-MHz Clock CLOCK (H_CNT = D+E) RESET V_SYNC_OUT
CLEAR (H_CNT = D+E+B) R
CLEAR 25.175-MHz CLOCK H_SYNC _OUT
(H_CNT = D+E+B=C) RED RED_OUT
H_DATA_ON
Q9–0 ROLL _OVER S Q GREEN VGS Monitor GREEN_OUT
CLK BLUE controller
BLUE_OUT
R
CLEAR COLUMN_OUT9–0
ROLL _OVER9–0
VCOUNT
(V_CNT = R) S Q V_SYNC_OUT
CLOCK
(V_CNT = R+S) CLK
CLEAR
(V_CNT = R+S+P) R
(V_CNT = R+S+P+Q) CLEAR
Q9–0
V_DATA_ON
S Q
CLK
R
CLEAR
RESET
RED_OUT
RED

GREEN GREEN_OUT

BLUE_OUT
BLUE
COLUMN_OUT
10
ROW_OUT
10

Figure 5—The VGA monitor controller circuit contains the following: a horizontal counter circuit for generating the horizontal sync and column count signals (a); a vertical count-
er circuit for generating the vertical sync and row count signals (b); a complete VGA controller circuit (c); and a logic symbol for the controller circuit (d).

40 Issue 172 November 2004 CIRCUIT CELLAR® www.circuitcellar.com

nal. For example, at count zero, set when the horizontal sync counter zero. At the end of region D, the count
H_SYNC_OUT to zero; but between reaches 140 (95 + 45), you will subtract will be at 639. This way, when the
counts zero and 95, H_SYNC_OUT must 140 to get a zero. Then, 141 minus 140 counter is counting in region D, the
be kept at zero. An SR flip-flop is used to will produce a one, 142 minus 140 will count will also represent the correct
keep the signal steady. Recall that the SR produce a two, and so on. This solu- column count. Hence, the counter will
flip-flop sets the output Q to a one when tion requires an extra subtraction unit. reach 800 at the end of region C.
the input set is asserted with a one. It The last solution is the best. Simply Putting everything together, you get
resets the output Q to a zero when the offset the horizontal sync counter so the circuits shown in Figure 5. Figure 5a
input reset is asserted with a one. If both that you start the count at the begin- shows the horizontal counter with the
set and reset inputs are deasserted with a ning of region D instead of starting it at four AND gates for testing for the four
zero, then the output Q will maintain its the beginning of region B. At the begin- horizontal region values D, D + E, D +
current value. Hence, to obtain the hori- ning of region D, the count is reset to E + B, and D + E + B + C. The output
zontal sync signal, you can assert the of the counter is the column count.
reset input when the count is zero (or The circuit also outputs a ROLL_OVER
800), and assert the set input when the signal, which is used to reset the hori-
count is 95. The Q output of the SR flip- zontal counter to zero and is also the
flop is now the H_SYNC_OUT signal. clock signal for the vertical counter.
You can do one of three things to keep This signal is asserted each time the
track of the column count from zero to counter reaches 800. When the signal
639 in the D region. The first solution is a one, it asserts the counter’s LOAD
is to use another counter that counts input. When this happens, the 10-bit
from zero to 639 using the same clock counter input value D[9-0], which is a
frequency as the horizontal sync counter, constant 0, is loaded into the counter.
but this counter counts only when the Note that this actually gives a total of
horizontal sync counter is in region D. 801 counts per line, which is one
Photo 1—The VGA monitor screen shows a red border,
This solution requires an extra counter. more than intended. Fortunately,
two blue letters, and a green square. The UP2 development
The second solution is to subtract the board, which contains the FPGA chip with the VGA monitor VGA monitors are forgiving enough
offset for the B and C regions, so that controller circuit, outputs the video signals to the monitor. to tolerate this tiny error. The

42 Issue 172 November 2004 CIRCUIT CELLAR® www.circuitcellar.com

 mented the controller on an FPGA chip
Reset button RESET V_SYNC_OUT VERT_SYNC (pin 14)
using Altera’s UP2 development board.
25.17-MHz Clock 25.17-MHz CLOCK H_SYNC_OUT HORIZ_SYNC (pin 13)
To The board has a built-in VGA connector
RED RED_OUT RED (pin 1) VGA monitor
VGA Monitor
GREEN controller GREEN_OUT GREEN (pin 2) connector with the five signal pins connected to the
‘0’
‘0’ BLUE BLUE_OUT BLUE (pin 3) FPGA chip. The VGA monitor controller,
COLUMN_OUT9–0 along with a demonstration test circuit
ROW_OUT9–0 for creating a screen image, is imple-
mented in the FPGA chip on the board.
Row = 0
Photo 1 shows the UP2 board having
the controller circuit and a demonstra-
Row = 479 tion test circuit implemented in the
= 0111011111
FPGA. The demonstration test circuit
generates a red border, two blue letters,
Column = 0
and a green square on the monitor screen.
Column = 639 Rather than manually connecting the
=1001111111
numerous AND and OR gates needed for
Figure 6—Use this circuit to display a red border around the VGA monitor using the VGA monitor controller. comparing with the various column and
row values to turn on the RGB signals, I
COUNT input is tied high for continu- controller is shown in Figure 5d. The have written a VHDL code for the test
ous counting, the CLEAR input is tied H_SYNC_OUT, V_SYNC_OUT, circuit. The complete test circuit code for
to a reset switch, and the clock input RED_OUT, GREEN_OUT, and generating the image is posted on the
is connected to the 27.175-MHz clock. BLUE_OUT signals connect directly Circuit Cellar ftp site. After synthesizing
Figure 5b shows the vertical counter. to pins 13, 14, 1, 2, and 3 of the VGA the code, the resulting netlist, along with
It is almost identical to the horizontal connector. You can optionally connect the monitor controller circuit, is down-
counter circuit, except for the clock and a switch to the Reset input. The clock loaded to the FPGA chip. The result is
the values tested for by the four AND source is a 25.175-MHz clock. To dis- shown on the monitor in Photo 1.
gates. The clock for this counter is the play something on the screen, you need In order to display more complex
ROLL_OVER signal from the horizontal to check the values of COLUMN_OUT images, memory is used to keep track of
counter. The values tested for by the and ROW_OUT, and set the RED, which pixel should be turned on or off
AND gates are the vertical region values GREEN, and BLUE signals accordingly. and for which color (instead of using
R, R + S, R + S + P, and R + S + P + Q. numerous AND gates as comparators to
The complete VGA monitor con- CONTROLLER TEST check for the current column and row
troller circuit is shown in Figure 5c. The To turn on a particular pixel, you need values). If you have one memory loca-
H_DATA_ON and V_DATA_ON signals to test the values of the column and row tion for each color of each pixel, you can
are generated in a similar fashion to the counts from the controller. If they are use the column and row counts from the
H_SYNC_OUT and V_SYNC_OUT sig- equal to the location of the pixel you controller as the address for the memory.
nals, except they’re set to a one when want to turn on, then you assert any of The content of the memory location
the counters are in the D and R regions. the color signals, and that pixel will be will be the value for the color signals. I
Outside these regions, they’re set to a zero. turned on with that color. For example,
The H_DATA_ON signal is set to a if you want the pixel at column 3, row 5
Enoch Hwang has a Ph.D. in comput-
one when the horizontal counter is at to be blue, then you need to check
er science. He is currently an associ-
zero (800). It’s reset to a zero when the the values of COLUMN_OUT and
ate professor of computer science at
counter is at 640. The V_DATA_ON ROW_OUT from the controller to see if
La Sierra University and a lecturer at
signal is set to a one when the vertical they are equal to three and five respec-
the University of California, Riverside.
counter is at zero (528). It’s reset to a tively. If they are, set the BLUE input sig-
He is interested in embedded micro-
zero when the counter is at 480. nal to a one; otherwise, set it to a zero.
processor systems, automation, and
These two DATA_ON signals are used Figure 6 shows the circuit for dis-
robotics. You may reach him at
to enable the output of the RBG sig- playing a red border around the moni-
[email protected].
nals. The RGB signals connected to tor using the VGA monitor controller.
the monitor must be turned on only Four AND gates are used to test for
PROJECT FILES
when the two sync signals are in the column and row border values.
regions D and R. Three AND gates, Because the screen resolution is 480 × To download the code, go to ftp.circuit-
one for each of the three color signals, 640, the four border values to test are cellar.com/pub/Circuit_Cellar/2004/172.
are used to enable the color signals. column = 0, column = 639, row = 0,
The H_DATA_ON and V_DATA_ON and row = 479. If one of these tests is SOURCE
signals are the enabler lines to the true, then set the red signal to a one. UP2 Development kit
AND gates. Instead of using discrete ICs for con- Altera Corp.
The logic symbol for the VGA structing the controller circuit, I imple- www.altera.com

www.circuitcellar.com CIRCUIT CELLAR® Issue 172 November 2004 43