Palestine Technical College

Engineering Professions Department

EEE14356 - Digital Logic Fundamentals

Experiment 9

Sequential Circuit
Student No Name Surname Group Lecturer Grade

2022-2023
EEE14356 Digital Logic Fundamentals Lab

Introduction:
The operation of up/down counter can be controlled by the up/down control input. This up/down
counter has two modes, including count up and count down. The up/Down counter is commonly
known as the bidirectional counter, which counts in either direction depends on the condition of the
control input. In up-counter, the counter counts up from zero and increments to some preset value to
provide an output condition change, while down-counter counts down from a predetermined value
to zero that activates when the zero count or some other pre-set value is reached.

Objectives:
1. To understand the concept of a synchronous sequential circuit.
2. To design, construct, and test a synchronous sequential circuit.
3. Using JK flip-flop in constructing an up-down counter with enable.
Note: Verify the IC's numbers and validity before using it in any circuit.

Equipment and materials:

o Digital trainer M21-5000
o Integrated circuits (ICs)
o 7408 Quadruple 2-input AND gate
o 7473A dual JK flip flop
o 7486 Quadruple 2-input XOR gate
o 74266 Quadruple 2-input XNOR gate

Part A – Up-Down counter

Given the state diagram in figure 9.1, design a synchronous sequential circuit using JK flip-flops.
x=1
00 11
x=0
x= 0

x= 1
x= 0

x= 1

x=1
01 10
x=0
Figure 9.1 Synchronous sequential circuit
1. Derive the state and characteristic equations.
2. Record your data in the state table 9.1.
3. Draw the sequential circuit.
4. Implement the sequential circuit with minimum number of gates; connect the input x to switch
and the output QA & QB to the indicator lamps to track the output states.
Table 9.1 State table of the up-down counter
Present state Next state
Flip-flop inputs
Q(t) Q(t+1)
x=0 x=1 x=0 x=1
QA QB QA QB QA QB JA KA JB KB JA KA JB KB
0 0
0 1
1 0
1 1

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EEE14356 Digital Logic Fundamentals Lab

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Part B – Up-Down counter with enable

Design, construct, and test a 2-bit counter that counts up or down using JK flip-flops. The counter
has 2-inputs (E and x). The enable input E determines whether the counter is on or off and the other
input x determines the count direction.
If E = 0, the counter is disabled and remains at the present state even though the clock pulse is
applied to the flip flops, while if E = 1, the counter is enabled and goes to the next state when
applying the clock pulse. If x = 1, the circuit count up with sequence 00, 01, 10, 11 and repeats its
sequence. However, if x = 0, the circuit count down with sequence 11, 10, 01, 00 and repeats its
sequence. Do not use E to disable the clock and record your data in state table 9.2.
Table 9.2 State table of the up-down counter with enable
Present state Next state
Inputs Flip-flop inputs
Q(t) Q(t + 1)
E x QA QB QA QB JA KA JB KB
0 x 0 0 0 0 0 x 0 x
Disable

0 x 0 1 0 1 0 x x 0
0 x 1 0 1 0 x 0 0 x
0 x 1 1 1 1 x 0 x 0
1 0 0 0
Counts
down

1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
Counts up

1 1 0 1
1 1 1 0
1 1 1 1

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EEE14356 Digital Logic Fundamentals Lab

1. Draw the state diagram.

2. Derive the state and characteristic equations.
3. Record your data in the state table 9.2.
4. Draw the sequential circuit.
5. Implement the sequential circuit with minimum number of gates; connect the inputs E & x to
switches and the output QA & QB to the indicator lamps to track the output states.
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EEE14356 Digital Logic Fundamentals Lab

Pin Configuration:

7408 2-input AND gate 7473A dual JK flip-flops

7486 2-input XOR gate 74266 2-input XNOR gate

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