Week 12

Microprocessor Circuitry

These lecture notes are based on the book by Muhammed Ali Mazidi,
Janice Gillispie Mazidi, Danny Causey; «The x86 PC assembly language,
design, ad interfacing», 5the Ed., Prentice Hall
 8086 and 8088 Microprocessors
u 8086 announced in 1978; 8086 is a 16 bit microprocessor with a 16 bit data bus
u 8088 announced in 1979; 8088 is a 16 bit microprocessor with an 8 bit data bus
u Both manufactured using High-performance Metal Oxide Semiconductor (HMOS)
technology
u Both contain about 29000 transistors
u Both are packaged in 40 pin dual-in-line package (DIP)
u Address lines A0-A7 and Data lines D0-D7 are multiplexed in 8088. These lines
are labelled as AD0-AD7.
u By multiplexed we mean that the same physical pin carries an address bit at one time
and the data bit another time
u Address lines A0-A15 and Data lines D0-D15 are multiplexed in 8086. These lines
are labelled as AD0-AD15.
8086 and 8088 Microprocessors
Minimum and maximum mode
u 8088 and 8086 microprocessors can be configured to work in
either of the two modes: the minimum mode and the maximum
mode
u Minimum mode:
u Pull MN/MX to logic 1
u Typically, smaller systems and contains a single microprocessor
u Cheaper since all control signals for memory and I/O are generated by
the microprocessor.
u Maximum mode
u Pull MN/MX logic 0
u Larger systems with more than one processor (designed to be used when
a coprocessor (8087) exists in the system)
Data Bus
u Due to chip packaging limitations
in the 1970s, there was great
effort to use the minimum
number of pins for external
connections.
u Intel multiplexed address & data
buses, using the same pins to
carry two sets of information:
address & data.
u Pins 9-16 (AD0–AD7) are used
for both data and addresses in
8088.
u AD stands for "address/data.”
u The ALE (address latch enable)
pin signals whether the
information on pins AD0–AD7 is
address or data.
Address Bus
u 8088 has 20 address pins (A0–A19),
allowing it to address a maximum of
one megabyte of memory (220 = 1M).
u To demultiplex address signals, a latch
must be used to grab the addresses.
u Widely used is the 74LS373 IC, also
74LS573, a 74LS373 variation.
u AD0 to AD7 go to the 74LS373 latch,
providing the 8-bit address A0–A7.
u A8–A15 come directly from the
microprocessor (pins 2–8 & pin 39).
u The last 4 bits of the address come
from A16–A19, pin numbers 35–38.
Address Bus
Address Bus
Control Bus
u 8088 can access both memory and I/O devices for
read and write operations, four operations, which
need four control signals:
u MEMR (memory read); MEMW (memory write).
u IOR (I/O read); IOW (I/O write).
u 8088 provides three pins for control signals:
u RD, WR, and IO/M.
u RD & WR pins are both active-low.
u IO/M is low for memory, high for I/O devices.
Control Bus
Control Bus
Control Bus
Minimum mode Interface
u Control Signals: (8088)
ü Address Latch Enable (ALE) is a pulse to logic 1 that signals
external circuitry when a valid address is on the bus. This address can
be latched in external circuitry on the 1-to-0 edge of the pulse at ALE.
ü IO/M line: memory or I/O transfer is selected (complement for 8086)
ü DT/R line: direction of data is selected
ü RD line: =0 when a read cycle is in progress
ü WR line: =0 when a write cycle is in progress
ü DEN line: (Data enable) Enables the external devices to supply
data to the processor. Used when sharing memory with another
processor.
Bus timing
u A bus cycle (machine cycle) defines the basic operation that a
microprocessor performs to communicate with external devices
u Examples of bus cycles are memory read, memory write, input/output
read, and input/output write.
u A bus cycle corresponds to a sequence of events that starts with an
address being output on the system bus followed by a read or write data
transfer
u During these operations, a series of control signals are also produced by
the MPU to control the direction and timing of the bus.
u Each bus cycle consists of at least four clock periods: T1, T2, T3, and T4.
u These clock periods are also called the T-States
 ALE timing, read operation

8088 uses 4 clocks for memory & I/O

bus activities.
• In read timing, ALE latches the
address in the first clock cycle.
• In the second and third cycles, the read
signal is provided.
• By the end of the fourth, data must be
at the CPU pins.
• The entire read or write cycle time is
only 4 clock cycles.

If reading/writing takes more than 4 clocks,

wait states (WS) can be requested from the
CPU.
Read cycle for 8086
Read cycle for 8086 explained
u Each BUS CYCLE (machine cycle) on the 8086 equals four system
clocking periods (T states).
u The clock rate is 5MHz, therefore one Bus Cycle is 800ns.
u Memory specs (memory access time) must match constraints of
system timing.
u For example, bus timing for a read operation shows almost 600ns
are needed to read data.
u However, memory must access faster due to setup times, e.g.
Address setup and data setup.
u This subtracts off about 150ns.
u Therefore, memory must access in at least 450ns minus another 30-
40ns guard band for buffers and decoders.
u 420ns DRAM required for the 8086.
Read and
write cycles
Write cycle for 8088/8086
8088 other pins

Pins 24–32 have different functions

depending on whether 8088 is in
minimum or maximum mode.

• In maximum mode, 8088 needs

supporting chips to generate the control
signals.
8088 other pins
8088 other pins
8088 other pins
 8088 other pins

u MN/MX (minimum/maximum) -
minimum mode is selected by
connecting MN/MX (pin number
33) directly to +5 V.
u Maximum mode is selected by
grounding this pin.
u CLOCK - an input signal,
connected to the 8284 clock
generator.
8088 other pins
8088 other pins
u TEST - in maximum mode, an input from the 8087 math coprocessor to
coordinate communications.
u Processor suspends operation when=1. Resumes operation when=0.
u Used to synchronize the processor to external events. (All 8087-capable
compilers and assemblers automatically generate a WAIT instruction before each
coprocessor instruction).
u The WAIT instruction tests the CPU's TEST pin and suspends execution until its
input becomes "LOW". When TEST=0, WAIT instruction is like NOP.
u In all 8086/8087 systems, the 8086 /TEST pin is connected to the 8087 BUSY
pin. If the EU executes a coprocessor instruction, it forces its BUSY pin
"HIGH"; thus, the WAIT opcode preceding the coprocessor instruction stops
the CPU until any still-executing coprocessor instruction has finished)
u – Not used In minimum mode.!
8088 other pins
u RESET - terminates present activities of the processor when a high is applied to the
RESET input pin.
u RESET : =0. Need at least 4 clock cycles. Issuing reset causes the processor to
fetch the first instruction from the memory FFFF:0000h.

A presence of high will

force the microprocessor
to stop all activity and set
the major registers to the
values shown at right.
8088 other pins
u NMI (Nonmaskable interrupt) : A leading edge transition causes the processor
go to the interrupt routine after the current instruction is executed.
u NMI (nonmaskable interrupt) - an edge-triggered (low to high) input signal to the
processor that will make the microprocessor jump to the interrupt vector table
after it finishes the current instruction.
u Cannot be masked by software.
80286 Microprocessor

• 80286 works in real or

protected mode.
• Real mode maximum memory
access is 1M. (00000H to
FFFFFH)
• In protected mode the entire
16M bytes of memory is
available. (000000H to
FFFFFFH)
• Use in protected mode
requires extremely complex
memory management.
80286 address bus
• Providing a memory address
uses all 24 pins (A0–A23), a
maximum of 16M.
• For an I/O address, pins A0–
A15 are used.
• If a 16-bit I/O address, A0–
A15 provide the address &
A16–A23are low.
• If an 8-bit address, only A0–
A7 are used, and A8–A23 are
all low
80286 Data bus

• Separate address/data pins results in

higher pin counts but saves time by
eliminating the address demultiplexer.
• The 2-byte data path allows the transfer
of data on either byte or both bytes,
depending on the operation.
• 80286 coordinates the activity on the
data bus using A0 and BHE.
80286 MICROPROCESSOR pin descriptions

u Pin BHE (bus high enable) - an active-low output signal used to

indicate that data is being transferred on D8–D15.
u BHE and A0 are used to indicate whether the data transfer is on D0–
D7, D8–D15, or the entire bus, D0–D15.
16-BIT ISA BUS

Address, data &

control buses in
this figure are used
throughout the
motherboard, and
provided to the ISA
expansion slot.
80386

u Protection
u Protect the OS
u Protect one user from the other
u 386 uses privilege level for protection
u Virtual memory
u Segmentation: variable size
u Paging: fixed size
80486

u The first 1-million transistor microprocessor (actually 1.2

million)
u 168-pin PGA packaging (Pin Grid Array)
u 32-bit processor
u 486 has a 32-bit data bus (D0 – D31)
u Data type: 8-bit, 16-bit, and 32-bit
u 486 has a 32-bit address bus (A2 – A31 plus BE0 – BE3)
u Physical memory: 4G byte
80486
u The pipeline stages is broken into 5 stages
u Fetch
u Decode 1
u Decode 2
u Execute
u Register write-back
u Many 486 instructions are executed in only one clock cycle because of using a
deeper pipeline
u On-chip cache (8K byte) in microprocessor
u eliminates the interchip delay of external cache.
u Math coprocessor on the same chip as the CPU
u Faster execution of FP instructions
u 486SX without math coprocessor
Pipelined execution

Execute Mem. Access

Execute Mem. Access

Execute Mem. Access

80486
u The use of 4 pins for data parity (bidirectional pins: DP0, DP1, DP2,
and DP3)
u The 486 involves the burst cycle
u Nonburst mode: it takes a minimum of 2 clocks to read from or
u write to external memory
u Burst mode: 486 can perform 4 memory cycles in 5 clocks (2-1-1-1) for reading
4 double words (16 bytes).
u Supports new instructions
u XADD EAX, EBX ; Exchange and add
u BSWAP EAX ;change little endian to big endian
u The input frequency to the 486 is the same as the system frequency.
How to increase the processing power?

u Increase the clock frequency of the chip

u The higher frequency, the more power dissipation
u The higher frequency, the more difficult the design of microprocessor and
motherboard
u The higher frequency, the more expensive
u Increase the number of data buses
u Change the internal architecture to exploit parallelism
u Super pipeline: deeper pipeline
u superscalar: issuing multiple instructions per clock cycle
Features of the Pentium
u 3.1 million transistors and 273-pins
u The external data bus is 64-bit
u Pentium registers are 32-bit
u 8 bytes external bus requires 8 byte enable (BE) pins
u The data parity (DP) pins are 8 in Pentium
u The Pentium has 16K bytes of on chip cache (8K for code and 8K for
data)
u Internally, it has 4 buses:
address code, code, address data, and data buses
u The on-chip math coprocessor of the Pentium (FPU) has been
redesigned to be faster (8-stage pipeline).
Features of Pentium (TLB)
u Translation Lookaside Buffer (TLB):
u When a virtual address needs to be
translated into a physical address,
the TLB is searched first. If a match
is found (a TLB hit), the physical
address is returned, and memory
access can continue.
u However, if there is no match
(called a TLB miss), the handler will
typically look up the address
mapping in the page table to see
whether a mapping exists (a Page
Walk).
Features of Pentium

u The Pentium is a superscalar architecture

u It has two execution unites (V: simple, U: complex)
u Includes branch prediction
u Provides the option of 4K and 4M for the page size
u The TLB for data: 64 entries for 4K pages and
The TLB for code: 32 entries for 4K pages
u The Pentium has both burst read and burst write cycles.
Pentium advanced models

u 5.5 million transistors on 150 MHz

u Single package with two separate dies
u L2 cache (256K bytes) on a separate die to reduce the interchip
delay.
u L1 cache (16K) on the same die with the CPU
u Internally RISC: translate 80x86 into microoperations
u 12-stage pipeline: increase the clock rate
u It has multiple execution unites working in parallel
u Out-of-order execution: increase performance