Scribd
Upload
3 views2 pages

Crash Dump

The document reports an unhandled SIG_SEGV error in a software version r2.6.0.4a build 109, caused by an instruction at a specific address. It provides detailed information about the registers and the state of emulated ARM9 and ARM7 processors, indicating that all registers are set to zero. Additionally, it includes translation cache details with specific memory addresses and allocation information.

Uploaded by

clorhetza
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
3 views2 pages

Crash Dump

The document reports an unhandled SIG_SEGV error in a software version r2.6.0.4a build 109, caused by an instruction at a specific address. It provides detailed information about the registers and the state of emulated ARM9 and ARM7 processors, indicating that all registers are set to zero. Additionally, it includes translation cache details with specific memory addresses and allocation information.

Uploaded by

clorhetza
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
You are on page 1/ 2

Unhandled SIG_SEGV in ''

caused by instruction blvc d68737f4 (at d5c596f4), address 0


Version: r2.6.0.4a build 109
Reference: C515CAEC
Registers:
r00: D5D7D668
r01: F17B9860
r02: 00000001
r03: 00000000
r04: C8854E30
r05: F17B9860
r06: DF5FCA20
r07: 00000000
r08: 00000001
r09: 00000000
r10: 00000001
r11: F503A620
r12: D5D6F3B4
r13: C8854DF0
r14: D5C53341

Emulated ARM9:
Mode 00, IRQ 00000000, CPSR 00000000, PC 00000000, cycles 00000000
r0: 00000000
r1: 00000000
r2: 00000000
r3: 00000000
r4: 00000000
r5: 00000000
r6: 00000000
r7: 00000000
r8: 00000000
r9: 00000000
r10: 00000000
r11: 00000000
r12: 00000000
r13: 00000000
r14: 00000000
r15: 00000000
Debug instruction count: 0

Emulated ARM7:
Mode 00, IRQ 00000000, CPSR 00000000, PC 00000000, cycles 00000000
r0: 00000000
r1: 00000000
r2: 00000000
r3: 00000000
r4: 00000000
r5: 00000000
r6: 00000000
r7: 00000000
r8: 00000000
r9: 00000000
r10: 00000000
r11: 00000000
r12: 00000000
r13: 00000000
r14: 00000000
r15: 00000000
Debug instruction count: 0

Translation cache details:


main: 0xc5319000 - 0xc6319000
main: 986607616 + -969830400 bytes
itcm: 0xc6319000 - 0xc6419000
itcm: 969830400 + -968781824 bytes
alternate: 0xc6419000 - 0xc6619000
alternate: 968781824 + -966684672 bytes

0 texture cache bytes allocated, 0 texture cache elements.

You might also like