Tutorials Computer Architecture

SECTION A
1) What do processors of all computers must have? c) Java
A. Control unit d) All
B. ALU 10) Which unit is used to measure the CPU’s
C. Primary Storage processing power?
D. All of these a) GIPS
2) In the CPU, what is the functionality of the control b) LIPS
unit? c) MIPS
A. To decode program instruction d) Nanoseconds
B. To perform logic operations 11) Which unit is used to measure the CPU’s speed
C. To store program instruction of a computer?
D. To transfer data to primary storage a) IPS
3) With the help of _______ we reduce the memory b) GPS
access time: c) Clock speed
A. SDRAM d) IPC
B. Cache 12) Which of the following is used by ALU to store
C. Heaps intermediate results?
D. Higher capacity RAMs a) Registers
b) Heap memory
4) What is a dedicated computer?
c) Stack memory
A. Which does one kind of software
d) Accumulator
B. Which is meant for application software only
13) Which of the following special-purpose register
C. Which is used by one person only
keeps track of the address of the instruction
D. Which is assigned to one and only one task
which is to be executed next?
5) What is used to increase the apparent size of
a) Stack pointer
physical memory?
b) Program counter
A. Disks
c) ALU
B. Hard-disk
d) Both b and c
C. Virtual memory
14) Both the CISC and RISC architectures have been
D. Secondary memory
developed to reduce the ______
a) Time delay
6) What is a collection of 8 bits called? b) Semantic gap
A. Byte c) Cost
B. Word d) All of the mentioned
C. Record 15) Which of the following is the full form of CISC?
D. None of these a) Complex Instruction Sequential Compilation
7) The first computer architecture was designed (or b) Complete Instruction Sequential Compilation
developed) in c) Computer Integrated Sequential Compiler
a) 1970 d) Complex Instruction Set Computer
b) 1971 16) . There are ___ kinds of buses.
c) 1968 a. One
d) 1972 b. Two
8) The hardware in which data is stored permanently c. Three
for a computer system is d. Fou
a) Registers 17) Which of them is a CPU register.
b) Bus a. PC
c) Secondary memory b. MAR
d) Main memory c. MDR
9) Which language can be understood directly by d. All of the above
CPU?
a) C 18) Which of the following is not considered as a
b) Machine peripheral device?

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a. CPU - A) RAM
b. Keyboard - B) Cache
c. Monitor
- C) ROM
d. All of the above
- D) Virtual Memory
19) Which of the following computer memory is
fastest?
25. **What is the purpose of cache
a. Register memory?**
b. Hard disk
- A) To store data permanently
c. RAM
d. None of the above
- B) To speed up access to frequently used
data
20) Which of the following computer register collects - C) To increase the size of main memory
the result of computation?
- D) To store temporary data only
a. Accumulator
b. Instruction Pointer
c. Storage register 26. **Which of the following describes
d. None of the above
virtual memory?**
- A) Memory that is physically present in
the computer
21. **What are the two main types of
memory?** - B) An extension of main memory using
disk space
- A) RAM and ROM
- C) A type of RAM
- B) Cache and Virtual Memory
- D) A high-speed memory used for
- C) Flash and Hard Disk caching
- D) DRAM and SRAM
27. **What is the primary function of the
22. **Which type of RAM must be Control Unit in a CPU?**
refreshed periodically to retain data?** - A) To perform arithmetic calculations
- A) SRAM - B) To fetch data from memory
- B) ROM - C) To coordinate the operations of the
- C) DRAM CPU
- D) Flash Memory - D) To store temporary data

23. **What does SRAM stand for?** 28. **In the von Neumann architecture,
- A) Static Random Access Memory which component is responsible for
- B) Simple Random Access Memory arithmetic and logic operations?**
- C) Synchronous Random Access - A) Control Unit
Memory - B) Memory
- D) Secondary Random Access Memory - C) Datapath
- D) Cache
24. **Which type of memory is used to store
permanent data?**

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29. **What is the purpose of the Program 34. **What does I/O stand for in computer
Counter (PC) in a CPU?** architecture?**
- A) To hold data values - A) Internal/Output
- B) To keep track of the next instruction - B) Input/Output
to be executed - C) Input/Online
- C) To control data flow in the bus - D) Internal/Online
- D) To store temporary results
35. **Which of the following interrupts
30. **Which type of architecture is MARIE signals that a device is ready for data
an example of?** transfer?**
- A) CISC - A) Hardware malfunction
- B) RISC - B) User-defined break
- C) Flash - C) I/O completion
- D) Hybrid - D) Arithmetic error

31. **What is a page fault?** 36. **What is the function of the Arithmetic
- A) An event when data is lost Logic Unit (ALU) in a CPU?**
- B) An event when a requested page is - A) To manage memory
not in main memory - B) To execute arithmetic and logical
- C) An error in the CPU operations
- D) A type of cache miss - C) To control input/output operations
- D) To store instructions
32. **What does the term "memory
hierarchy" refer to?** 37. **Which type of cache is used to store
- A) The organization of memory types both data and instructions?**
based on speed and size - A) Instruction Cache
- B) The arrangement of CPUs in a - B) Data Cache
system - C) Unified Cache
- C) The order in which instructions are - D) Victim Cache
executed
- D) The structure of the hard disk 38. **What does the term "paging" refer to
in virtual memory management?**
33. **Which of the following is a - A) The process of copying data to cache
characteristic of RISC architecture?** - B) Dividing physical memory into fixed-
- A) Complex instruction sets size blocks
- B) Fixed instruction sizes - C) Refreshing DRAM to maintain data
- C) Large number of instructions - D) Storing data permanently on a hard
- D) Variable instruction lengths drive

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39. **Which of the following is not a type - B) Exclusive Cache
of ROM?** - C) Shared Cache
- A) PROM - D) Unified Cache
- B) EPROM
- C) SRAM 45. **What is an interrupt?**
- D) EEPROM - A) A signal that temporarily halts the
CPU's operation
40. **What is the typical access time for - B) A method for data storage
Level 1 cache?** - C) A type of memory access
- A) 10 - 20 ns - D) A speed enhancement technique
- B) 4 ns
- C) 15 - 20 ns 46. **What is the primary purpose of the
- D) 1 ms input/output subsystem?**
- A) To manage memory allocation
41. **What is the main advantage of using - B) To facilitate communication with
virtual memory?** peripheral devices
- A) Increased speed - C) To execute program instructions
- B) Reduced hardware costs - D) To perform arithmetic calculations
- C) Increased data security
- D) Simplified programming 47. **Which of the following describes a
"bus arbitration" method?**
42. **In a computer system, what is the role - A) The process of refreshing memory
of the bus?** - B) The method of controlling access to
- A) To increase data storage capacity the bus
- B) To connect various components for - C) The technique for data compression
data transfer - D) The strategy for cache management
- C) To enhance graphics processing
- D) To manage power consumption 48. **What is the maximum addressable
memory space for a 32-bit architecture?**
43. **What does "byte-addressable" - A) 2 GB
memory mean?** - B) 4 GB
- A) Each byte has its own address - C) 8 GB
- B) Memory is accessed in word sizes - D) 16 GB
only
- C) Memory is accessed in blocks 49. **Which register holds the current
- D) Each word has its own address instruction being executed?**
- A) Program Counter (PC)
44. **Which type of cache allows only one - B) Memory Address Register (MAR)
copy of data to exist at a time?** - C) Instruction Register (IR)
- A) Inclusive Cache - D) Accumulator (AC)
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 55. **What is the purpose of the Memory
50. **What does the term "locality Buffer Register (MBR)?**
principle" refer to in cache memory?** - A) To hold the address of the next
- A) Data is stored in a remote location instruction
- B) Recently accessed data is likely to be - B) To store data being transferred to or
accessed again soon from memory
- C) Data is retrieved from the hard disk - C) To keep track of the current
instruction
- D) Data is always accessed in sequential
order - D) To manage the bus control signals
51. **What is the primary characteristic of
dynamic RAM (DRAM)?** 56. **Which of the following is a common
- A) It is faster than SRAM method for improving cache
performance?**
- B) It requires periodic refreshing to
maintain data - A) Increasing the size of the main
memory
- C) It is used for cache memory
- B) Using virtual memory
- D) It retains data without power
- C) Implementing a victim cache
- D) Decreasing the clock speed
52. **In which component of the CPU does
decoding of instructions occur?**
- A) Arithmetic Logic Unit (ALU) 57. **What is a "cache miss"?**
- B) Control Unit - A) When the CPU retrieves data from
cache
- C) Cache
- B) When the requested data is not found
- D) Registers
in cache
- C) When cache memory is full
53. **What is the main difference between
- D) When data is incorrectly stored in
CISC and RISC architectures?**
cache
- A) RISC has more complex instructions
- B) CISC instructions are all the same
58. **What role does the bus controller play
size
in a computer system?**
- C) RISC focuses on a smaller set of
- A) It manages data storage
instructions
- B) It controls data flow on the bus
- D) CISC uses less memory than RISC
- C) It performs arithmetic operations
- D) It fetches instructions from memory
54. **Which type of memory is typically the
fastest?**
- A) Main Memory (RAM) 59. **What does the term "fragmentation"
refer to in memory management?**
- B) Cache Memory
- A) Memory that is lost permanently
- C) Virtual Memory
- B) Inefficient use of memory due to
- D) Hard Disk
allocation patterns
- C) A method for compressing data

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 - D) The process of refreshing memory
63. **Which register is responsible for
60. **Which of the following best describes holding the address of the next instruction to
a "hard fault"?** be executed?**
- A) An error in instruction execution - A) Accumulator (AC)
- B) An event when data must be retrieved - B) Memory Address Register (MAR)
from disk to memory - C) Instruction Register (IR)
- C) A temporary loss of power - D) Program Counter (PC)
- D) An error in data transmission
64. **What does the term "instruction cycle"
61. **What is the function of the data bus in refer to?**
a computer system?** - A) The time taken to execute a single
- A) To manage control signals instruction
- B) To carry data between components - B) The process of fetching, decoding,
and executing instructions
- C) To store instructions
- C) The duration of clock cycles
- D) To refresh memory
- D) The speed of the CPU
62. **In memory interleaving, what is the
purpose of high-order interleaving?** 65. **What is one of the key benefits of
using associative cache?**
- A) To improve access speed by
distributing addresses across chips - A) It reduces power consumption
- B) To ensure data is always stored in the - B) It allows data to be fetched based on
same chip content rather than address
- C) To increase memory capacity - C) It increases the size of the cache
- D) To simplify the memory architecture - D) It simplifies the memory hierarchy

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 SECTION B: STRUCTURAL

1) Explain the following terms (4 marks)

a) Instruction Set Architecture
b) Virtual memory
c) Stored-program computer
d) Interrupt
2) Differentiate SRAM from DRAM. (2 marks)
3) Give the use of each of the following features or components of Von Neumann Architecture (4 marks)
• Control unit
• Arithmetic and Logic Unit (ALU)
• Memory
• Input/output interface
4) Differentiate the Von Neuman Architecture from the Harvard Architecture (1 mark)
5) In relation to the Von Neuman Architecture, what is the role played by (3 marks)
a) Memory Address Register (MAR)
b) Program Counter (PC)
c) Accumulator
6) The sequence of operations shows the register transfer notation of the Fetch-Decode-execute cycle.
1-MAR  [PC]
2-PC  [PC] + 1
3-IR  [MAR]
3-MAR  IR[11-0]
4-MBR  M[MAR]
5-AC  MBR
Note that [register] denotes the content of the specified register or memory location
Describe briefly what happens in each step. (5 marks)
7) What is a Buffer memory? (1 mark)