2015 International Conference on Advances in Computer Engineering and Applications (ICACEA)

IMS Engineering College, Ghaziabad, India

Area-Efficient Layout Design of Comparator using

Cascaded Technique
Manish Trikha Rajesh Mehra
M.E Scholar Associate Professor,
Department of Electronics & Communication, Department of Electronics & Communication, NITTTR,
NITTTR,Chandigarh, UT, India. Chandigarh, UT, India.
Email: [email protected] Email:[email protected]

Abstract—In this paper a new design of cascaded comparator is The wiring complexity is determined by the number of
described.Comparatoris the basic building block of many arithmetic connections and their lengths. All these characteristics may
and logical units used in microprocessors and DSP. In the world of vary considerably from one logic style to another and thus
new emerging technology it has become essential to develop various proper choice of logic style is very important for circuit
new design concepts to reduce the power consumption and chip performance [4], [5].
area. In this paper a semi-custom design ofcascaded comparator
has been presented and compared with the auto-generated layout
on CMOS 90nm foundry technology. The proposed semi-custom Table1: Truth Table for 2 Bit Comparator
Word A Word B Output
design of cascaded comparator has showed an improvement of
A1 A0 B1 B0 A>B A=B A<B
35.65 % of total area as compared to auto-generated layout.
0 0 0 0 0 1 0
0 0 0 1 0 0 1
Keywords: Cascaded Comparator; CMOS technology; Area 0 0 1 0 0 0 1
efficiency; Very large scale integration. 0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
I. INTRODUCTION 0 1 1 0 0 0 1
Digital comparator or magnitude comparator is a hardware 0 1 1 1 0 0 1
1 0 0 0 1 0 0
digital electronic device that willaccept two numbers as input
1 0 0 1 1 0 0
and determines whether any one number is greater than,less 1 0 1 0 0 1 0
than or equal to the other number. Comparators are used in 1 0 1 1 0 0 1
central processing units (CPUs) and microcontrollers (MCUs). 1 1 0 0 1 0 0
Magnitude Comparators are basic and very useful arithmetic 1 1 0 1 1 0 0
components of digital systems and there are various approaches 1 1 1 0 1 0 0
for designing CMOS comparators with different noise margin, 1 1 1 1 0 1 0
operating speed, power consumption, and its complexity [1].
As the CMOS technology grows the VLSI industry has
Magnitude comparator is a combinational circuit which been drifted toward the design of system on chip. So the
compares two numbers say A and B, and produced 3 bit output demand of the area efficient devices has been increased
depending upon the magnitude of the two numbers to be industry. As Comparator is one of the basic circuitry used in
compared i.e. either A>B, A=B and A<B shown in fig. 1. [2], many arithmetic unit circuits of various portable devices so
[3] area efficient comparator can provide the fulfilment of these
demands. Due to this area efficient design of comparator has
become very important for the researchers. Area of the circuit
mainly depends on three things [6]:
a) Number of transistors in the circuit,
b) Feature size of the transistor
c) Wiring complexity.

No of transistors is of course the primary concern in the

Fig 1: n-Bit Magnitude Comparator area efficient design because it affects the complexity of any
circuit.
The logic style used in logic gates basically influences the Power dissipation in any combinational circuit depends on
speed, size, power dissipation, and the wiring complexity of a two components: One is static dissipation which occurs due to
circuit. Circuit size bacically depends on the number of the leakage current or other current drawn continuously from
transistors and their sizes and also on the wiring complexity. the power supply and second is dynamic dissipation which
occurs due to switching of transient current and
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 2015 International Conference on Advances in Computer Engineering and Applications (ICACEA)
IMS Engineering College, Ghaziabad, India
charging/discharging of load capacitances. The static = (3)
powerdissipation is the product of the leakage current and
supply voltage. The total static power dissipation Ps is given by Total power dissipation is given by the sum of these three
[7]: power dissipation i.e. static power dissipation, dynamic power
dissipation and short circuit dissipation [9], [10].
=∑ (1) = + + (4)
Where n= no of devices and the leakage current is
described by the equation III. CASCADEDCOMPARATOR
= −1 (2) For comparing higher order binary word we generally used
the conventional approach in which we design a truth-table and
Where, is reverse saturation current, is diode voltage, q develop the logic necessary for implementation. But if we see
is electronic charge, k is Boltzmann’s constant and T is the concept behind the comparator then it can be find that if
temperature. one-bit cascaded comparator is designed using simple logic and
The majority of the power dissipated in CMOS VLSI if it is cascaded number of time according to the number bit in
circuits is due to dynamic power. Thus for performance input words. Example 4-bit comparator can be designed using
estimation of comparator only dynamic power is of interest. four 1-bit cascaded comparator as shown in fig.2.
Average dissipated dynamic power is proportional to energy
required to charge and discharge the circuit capacitance and
switching frequency [8].

Fig 2: 4-Bit Comparator using 1-bit Cascaded Comparator

1-Bit cascaded comparator is the basic building block of Where ( > ) , ( < ) and ( = ) are
comparison and can be cascaded any number of times to outputs and ( > ) , ( = ) ,( > ) , , are
obtained higher order bits comparison. As shown in fig. 3. In the inputs to the comparator.The gate level circuit diagram of
comparison to the general higher bit comparator these 1-bit cascaded comparator is shown in fig. 4 which are
comparators are much easy to design and required repeated developded using the above equation, but some logic has been
logic. saved by using the comcept that only one of the output of the
comparator will be at high level so for the logic of (A=B) out we
use other two input connected to NOR gate as if (A<) out and
(A>B)out both are zero then (A=B)out will be high

Fig 3: 1-Bit Cascaded Comparator

The input-output equation of the 1-bit cascaded comparator

is given in equation 5,6 and 7.
Input-Output Equations
( > ) = ( > ) + ( = ) .( ) (5)
( < ) = ( < ) + ( = ) .( ) (6)
( = ) = [( > ) + ( < ) ]′ (7)
Fig 4: 1-Bit Cascaded Comparator(Gate Level) designed in Dsch 3.1 Software

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 2015 International Conference on Advances in Computer Engineering and Applications (ICACEA)
IMS Engineering College, Ghaziabad, India
Truth-table for 1 bit Cascaded Comparator is shown In
Table 2
The auto-generated layout design shown in fig. 7 can be
Table2: Truth Table for 1 bit Cascaded Comparator obtained by generatingVerilog file in Dsch 3.1software and
(A>B)in (A<B (A=B)in Ai Bi (A>B)o (A<B)out (A=B)o then compile the file in Microwind 3.1.
)in ut ut
0 0 1 0 0 0 0 1
0 0 1 0 1 0 1 0
0 0 1 1 0 1 0 0
0 0 1 1 1 0 0 1
0 1 0 0 0 0 1 0
0 1 0 0 1 0 1 0
0 1 0 1 0 0 1 0
0 1 0 1 1 0 1 0
1 0 0 0 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 0 1 0 0
1 0 0 1 1 1 0 0

IV. DESIGN SIMULATION Fig 7:1-Bit Cascaded Comparator in Microwind 3.1(Autogenerated)

The 1-bit cascaded comparator is first design in Dsch3.1
software according to the equation number 5, 6 and 7, as Related waveform shown in fig.8 has been obtained by
shown in fig. 5. by using W/L of n-MOS and c-MOS transistor simulating the auto-generated circuit in Microwind 3.1
equal to 5. software.

Fig 8: 1-Bit Cascaded Comparator waveform in Microwind

Fig 5: 1-Bit Cascaded Comparator(Transistor Level) in Dsch 3.1 Software For constructing the proposed area efficient 1- bit cascading
comparator the Microwind 3.1 software has been used with
The waveform for input- output are in fig 6. Which justified CMOS technology and design the circuit using 3 and 2 input
the above equation and truth-table in Table 2. NAND gates, 2 input NOR gates and NOT gates with the help
of the basic equation given in 5,6 and 7 with 90nm foundry file
as shown in fig. 9., This Layout is designed using only one
Metal layer.

Fig 9:1-Bit Cascaded Comparator in Microwind 3.1(Proposed)

Fig 6: 1-Bit Cascaded Comparator Waveform in Dsch 3.1

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 2015 International Conference on Advances in Computer Engineering and Applications (ICACEA)
IMS Engineering College, Ghaziabad, India
Related waveform shown in fig.10 has been obtained by much a matter of concerned then there is an
simulating the Designed circuit in Microwind 3.1 software. alternativeapproach which provide considerably area efficiency
over conventional design technology. So by using the proposed
design of comparator there will be an increased in power
consumption from 11.6μW to 78.2 μW but significantdecrease
in area required on silicon chip from 369.4μm2 to 237.7μm2in
comparison to the auto-generated design using 90nm CMOS
technology.
ACKNOWLEDGMENT
The authors would also like to thank Director, National
Institute of Technical Teachers’ Training & Research,
Chandigarh, India for their constant inspirations and support
throughout this research work.
REFERENCES
Fig 10: 1-Bit Cascaded Comparator waveform in Microwind [1] Anjuliand SatyajitAnand, “2-Bit Magnitude Comparator Design Using
Different Logic Styles”, International Journal of Engineering Science
Invention, Vol. 2, Issue 01, pp.13-24, January. 2013.
[2] VijayaShekhawat, Tripti Sharma and Krishna Gopal Sharma, “2-Bit
V. LAYOUT DESIGN Magnitude Comparator using GDI Technique”, IEEE International
As can be seen from Table 3. That the Auto-generated Conference on Recent Advances and Innovations in Engineering
layout consume 369.4μm2 surface area of silicon while (ICRAIE-2014), Jaipur, India, May 09-11, 2014.
[3] PushpaSaini and Rajesh Mehra, “A Novel Technique for Glitch and
proposed Layout consume only 237.7μm2 surface area of Leakage Power Reduction in CMOS VLSI Circuits”, International
silicon which provide significant savings in silicon area in the Journal of Advanced Computer Science and Applications, Vol. 3, No.
implementation of the cascaded comparator. 10, pp. 162-168, 2012.
[4] H. Traff, “Noval approach to high speed CMOS current Comparator”,
Electron. Letter, vol. 28, no. 3, pp. 310- 312, Jan.1992.
Table 3: Surface and Power analysis for Two Designs [5] VandanaChoudhary and Rajesh Mehra, “2-Bit Comparator Using
Factors Auto-generated Proposed different Logic Style of full-adder”, InternationalJournal of Soft
Layout Layout Computing and Engineering, Vol.3, pp. 277-279,May 2013.
Surface Area 369.4 μm2 237.7 μm2 [6] J.S. Wang and C.S. Huang, "High-speed and low-power CMOS
priority encoder”, IEEE J. Solid-State Circuits, vol.3S, pp.1511- 1514,
Power 11.6μW 78.2 μW Oct.2000.
Width 39.3μm 20.4μm [7] Chandrahash Patel, Veena C.S, “Comparator Design Using Full
Height 9.4μm 11.7μm Adder”, International Journal of Research in Engineering and
Technology, Vol. 03, Issue 07, pp. 365-368, Jul-2014.
The power consumed by the auto-generated layout take [8] VandanaChoudhary and Rajesh Mehra, "2- Bit CMOS Comparator by
Hybridizing PTL and Pseudo Logic", International Journal of Recent
11.6μW while proposed layout consumed 78.2μW which Technology and Engineering (IJRTE), ISSN: 2277-3878, Vol. 2,
shows that auto-generated layout give good power efficiency Issue2, pp. 29-32,May2013.
then proposed layout as shown in fig. 11. [9] S. Rahul, F. L. Richard and M. Carver, “A Low Power Wide Dynamic-
Range Analog VLSI Cochlea”,Analog Integral Circuits Signal Process,
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[10] WangGuangjie, ShengShimin and JiLijiu, “New Efficient Design of
Digital Comparator”, ASIC, 1996. 2nd International Conference, pp.
263 – 266, 21-24, Oct 1996.
[11] Monika Singh, Rajesh Mehra, “Comparative Analysis of CMOS
Comparator Using BSIM 4 Model”, National Student Conference On
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[12] Anjali Sharma, Richa Singh and PankajKajla, “Area Efficient 1-Bit
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Fig 11: Layout Comparision for surface area and power AUTHORS
Manish Trikhareceived the Bachelors of
V. CONCLUSION Technology degree in Electronics and
Communication Engineering from
In this paper, the simulation of two layout designs of 1-bit
cascaded comparator has been presented. In which the Moradabad Institute of Technology,UPTU,
proposed designed provide area efficiencythen the auto- Moradabad, India in 2007, and He is
generated version. But when we see the power consumed by pursuing Masters of Engineering degree in
the two designed then auto-generatedis more power efficient.
So for the certain application where the power efficiency is not

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 2015 International Conference on Advances in Computer Engineering and Applications (ICACEA)
IMS Engineering College, Ghaziabad, India
Electronics and Communication Engineering from National in Electronics and Communication Engineering from National
Institute of Technical Teachers’ Training & Research, Institute of Technical Teachers’ Training& Research,
PanjabUnivsrsity, Chandigarh, India. PanjabUnivsrsity, Chandigarh, India in 2008. He is pursuing
He is an Assistant Professor with the Department of Doctor of Philosophy degree in Electronics and
Electronics & Communication Engineering,, Moradabad Communication Engineering from National Institute of
Institute of Technology, Moradabad, India. His current Technical Teachers’ Training & Research, PanjabUnivsrsity,
research and teaching interests are in Digital electronics and Chandigarh, India.
digital signal processing. He has authored 13 research He is an Associate Professor with the Department of
publications including 9 in International Journal and 4 in Electronics & Communication Engineering,, National Institute
International Conferences. of Technical Teachers’ Training & Research, Ministry of
Human Resource Development, Chandigarh, India. His
Rajesh Mehra received the Bachelors of current research and teaching interests are in Signal, and
Technology degree in Electronics and Communications Processing, Very Large Scale Integration
Communication Engineering from National Design. He has authored more than 175 research publications
Institute of Technology, Jalandhar, India in including more than 100 in Journals. Mr.Mehra is member of
1994, and the Masters of Engineering degree IEEE and ISTE.

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