Exp No:1 HALF ADDER AND FULL ADDER

Date:

AIM:

To design and simulate half adder and full adder circuit using Xilinx simulation
software and verify its truth table.

BLOCK DIAGRAM:

EXPRESSION:

HALF ADDER: FULL ADDER:

SUM S= A B SUM S=A B Cin

CARRY C= AB CARRY C0= CARRY = AB + ACin + BC

CIRCUIT DIAGRAM:

HALF ADDER:
 FULL ADDER:

TRUTH TABLE:

HALF ADDER:

A B SUM ‘S’ CARRY ‘C’

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

FULL ADDER:

A B Cin SUM ‘S’ CARRY ‘C0’

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
THEORY:

HALF ADDER:
Adders are the basic building blocks of all arithmetic circuits; adders add two binary
numbers and give out sum and carry as output. Adding two single-bit binary values X, Y
produces a sum S bit and a carry out C-out bit. This operation is called half addition and
the circuit to realize it is called a half adder
Half adder is a circuit, which can add two numbers and produce two outputs, sum and
carry. From the truth table it is clear that sum represent the logic output of an EX-OR
gate and carry, that of an AND gate. Thus a half adder can be built using two gates.
SUM = A B
CARRY = AB

FULL ADDER:
Full adder is a combinational circuit that forms the arithmetic sum of three bits.It consists
of three inputs namely X,Y and C-in. Adding two single-bit binary values X, Y with a
carry input bit C-in produces a sum bit S and a carry out C-out bit.

SUM = A'B'Cin + AB'Cin' + A'BCin'

CARRY = AB + ACin + BCin

When the carry is generated by the addition of two bits, this has to be added to next bit
sum. Half adders do not allow this. There are only two inputs present. A full adder can be
used for this purpose. Here three inputs are given, addend augends and the previous
carry.

PROGRAM:

--HALF ADDER

--Dataflow modelling
library ieee;
use ieee.std_logic_1164.all;
entity ha_d is
port(a,b:in std_logic;s,c:out std_logic);
end ha_d;
architecture haa of ha_d is
begin
s<=a xor b;
c<=a and b;
end haa;
--Behavioural modelling
library ieee;
use ieee.std_logic_1164.all;
entity ha_b is
port(a,b:in std_logic;s,c:out std_logic);
end ha_b;
architecture haab of ha_b is
begin
process(a,b)
begin
if((a='0') and (b='0'))then
s<='0';c<='0';
elsif((a='0') and (b='1'))then
s<='1';c<='0';
elsif((a='1') and (b='0'))then
s<='1';c<='0';
elsif((a='1') and (b='1'))then
s<='0';c<='1';
end if;
end process;
end haab;

--Structural modelling
library ieee;
use ieee.std_logic_1164.all;
entity ha_s is
port(a,b:in std_logic;s,c:out std_logic);
end ha_s;
architecture haas of ha_s is
component xorg
port(a,b:in std_logic;s:out std_logic);
end component;
component andg
port(a,b:in std_logic;c:out std_logic);
end component;
begin
g1:xorg port map(a,b,s);
g2:andg port map(a,b,c);
end haas;
--XOR GATE
library ieee;
use ieee.std_logic_1164.all;
entity xorg is
port(a,b:in std_logic;s:out std_logic);
end xorg;
architecture xorga of xorg is
begin
c<=a xor b;
end xorga;
--AND GATE
library ieee;
use ieee.std_logic_1164.all;
entity andg is
port(a,b:in std_logic;c:out std_logic);
end andg;
architecture andga of andg is
begin
c<=a and b;
end andga;

--FULL ADDER

--Dataflow modelling:

library ieee;

use ieee.std_logic_1164.all;

entity fa_data is

port(a,b,cin:in std_logic;s, cout:out std_logic);

end fa_data;

architecture fa_arch_data of fa_data is

begin
 s<=a xor b xor cin;

cout <=(a and b)or(cin and b)or(a and cin) ;

end fa_arch_data;

--Behavoiural modelling

library ieee;

use ieee.std_logic_1164.all;

entity fa_behav is

port(a,b,c:in std_logic;s,cout:out std_logic);

end fa_behav;

architecture fa_behav_arc of fa_behav is

begin

process(a,b,c)

begin

if(a='0' and b='0' and c='0')then

s<='0'; cout <='0';

elsif(a='0' and b='0' and c='1')then

s<='1'; cout <='0';

elsif(a='0' and b='1' and c='0')then

s<='1'; cout <='0';

elsif(a='0' and b='1' and c='1')then

s<='0'; cout <='1';

elsif(a='1' and b='0' and c='0')t hen

s<='1'; cout <='0';

elsif(a='1' and b='0' and c='1')then

s<='0'; cout <='1';

elsif(a='1' and b='1' and c='0')then

s<='0'; cout <='1';

 elsif(a='1' and b='1' and c='1')then

s<='1'; cout <='1';

end if;

end process;

end fa_behav_arc;

--STRUCTURAL MODELLING

library ieee;

use ieee.std_logic_1164.all;

entity fa_struct is

port(a,b,cin:in std_logic;s, cout:out std_logic);

end fa_struct;

architecture fa_arch_struct of fa_struct is

component andg

port(a,b:in std_logic;c:out std_logic);

end component;

component org

port(a,b:in std_logic;c:out std_logic);

end component;

component xorg

port(a,b:in std_logic;c:out std_logic);

end component;

signal z0,z1,z2:std_logic;

begin

x1:xorg port map(a,b,z0); x2:xorg port

map(cin,z0,s); a1:andg port map(a,b,z1);

a2:andg port map(cin,z0,z2);

o1:org port map(z1,z2,cout);

end fa_arch_struct;

SUB PROGRAMS:

--AND GATE

library ieee;

use ieee.std_logic_1164.all;

entity andg is

port(a,b:in std_logic;c:out std_logic);

end andg;

architecture andg_arch of andg is

begin

c<=a and b;

end andg_arch;

--OR GATE

library ieee;

use ieee.std_logic_1164.all;

entity org is

port(a,b,:in std_logic;c:out std_logic);

end org;

architecture org_arch of org is

begin

c<=a or b;

end org_arch;

--XOR GATE

library ieee;

use ieee.std_logic_1164.all;

entity xorg is

port(a,b:in std_logic;c:out std_logic);

end xorg;

architecture xorg_arch of

xorg is begin

c<=a
xor b;

end xorg_arch;

OUTPUT WAVEFORM:
--HALF ADDER:

BEHAVIORAL MODELLING

FULL ADDER:
 Viva Questions :
1) What is a half adder?

2) What is a full adder?

3) What are the applications of adders?

4) How to construct a full adder using two half adder.

5) Which type of modeling is simpler to design full adder using VHDL.

RESULT:

Thus the half adder and full adder circuit was designed and simulated using
Xilinx software and the truth table is verified successfully.
Exp No:2 HALF SUBTRACTOR AND FULL SUBTRACTOR
Date:

AIM:
To design and simulate half subtractor and full subtractor circuit using Xilinx
simulation software and verify its truth table.

HALF SUBTRACTOR:

BLOCK DIAGRAM:

CIRCUIT DIAGRAM:

TRUTH TABLE:-
FULL SUBTRCTOR:

BLOCK DIAGRAM:

CIRCUIT DIAGRAM:

TRUTHTABLE:

THEORY:

The half-subtractor is a combinational circuit which is used to perform subtraction of two

bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and
B (borrow).
 The full-subtractor is a combinational circuit which is used to perform subtraction of
three bits. It has three inputs, B (minuend) and A (subtrahend) and Z (subtrahend) and two
outputs D (difference) and Bor (borrow).
D=X-Y-Z (don't bother about sign)
B = 1 If X<(Y+Z)

PROGRAM:

HALF SUBTRACTOR

1.DATAFLOW MODELLING

library ieee;
use ieee.std_logic_1164.all;
entity hdsub is
port(a,b:in std_logic;
diff,borr:out std_logic);
end hdsub;
architecture hdsub1 of hdsub is
begin
diff<=a xor b;
borr<=not(a) and b;
end hdsub1;

2.BEHAVIOURAL MODELLING

library ieee;
use ieee.std_logic_1164.all;
entity hbsub is
port(a,b:in std_logic;
diff,borr:out std_logic);
end hbsub;
architecture hbsub1 of hbsub is
begin
process(a,b)
begin
if a='0' and b='0' then diff<='0';borr<='0';
elsif a='0' and b='1' then diff<='1';borr<='1';
elsif a='1' and b='0' then diff<='1';borr<='0';
elsif a='1' and b='1' then diff<='0';borr<='0';
end if;
end process;
end hbsub1;

3.STRUCTURAL MODELLING

library ieee;
use ieee.std_logic_1164.all;
entity hssub is
port(a,b:in std_logic;
diff,borr:out std_logic);
end hssub;
architecture hssub1 of hssub is
signal c:std_logic;
component xorg
port(a,b:in std_logic;
c:out std_logic);
end component;
component notg
port(a:in std_logic;
ab:out std_logic);
end component;
component andg
port(a,b :in std_logic;
c:out std_logic);
end component;
begin
x1:xorg port map(a,b,diff);
x2:notg port map(a,c);
x3:andg port map(c,b,borr);
end hssub1;
Sub Program:
AND Gate
library ieee;
use ieee.std_logic_1164.all;
entity andg is
port(a,b:in std_logic;
c:out std_logic);
end andg;
architecture andg1 of andg is
begin
c<=a and b;
end andg1;
NOT Gate
library ieee;
use ieee.std_logic_1164.all;
entity notg is
port(a:in std_logic;
ab:out std_logic);
end notg;
architecture notg1 of notg is
begin
ab<=not(a);
end notg1;
XOR Gate
library ieee;
use ieee.std_logic_1164.all;
entity xorg is
port(a,b:in std_logic;
c:out std_logic);
end xorg;
architecture xorg1 of xorg is
begin
c<=a xor b;
end xorg1;

FULL SUBTRACTOR

1.DATAFLOW MODELLING

library ieee;
use ieee.std_logic_1164.all;
entity fdsub is
port(a,b,bi:in std_logic;
diff,borr:out std_logic);
end fdsub;
architecture fdsub1 of fdsub is
begin
diff<=a xor b xor bi;
borr<=((not(a) and b) or (not(a) and bi) or (b and bi));
end fdsub1;

2.BEHAVIOURAL MODELLING

library ieee;
use ieee.std_logic_1164.all;
entity fbsub is
port(a,b,bi:in std_logic;
diff,borr:out std_logic);
end fbsub;
architecture fbsub1 of fbsub is
begin
process(a,b,bi)
begin
if a='0' and b='0' and bi='0' then diff<='0';borr<='0';
elsif a='0' and b='0' and bi='1' then diff<='1';borr<='1';
elsif a='0' and b='1' and bi='0' then diff<='1';borr<='1';
elsif a='0' and b='1' and bi='1' then diff<='0';borr<='1';
elsif a='1' and b='0' and bi='0' then diff<='1';borr<='0';
elsif a='1' and b='0' and bi='1' then diff<='0';borr<='0';
elsif a='1' and b='1' and bi='0' then diff<='0';borr<='0';
elsif a='1' and b='1' and bi='1' then diff<='1';borr<='1';
end if;
end process;
end fbsub1;

3.STRUCTURAL MODELLING

library ieee;
use ieee.std_logic_1164.all;
entity fssub is
port(a,b,bi:in std_logic;
diff,borr:out std_logic);
end fssub;
architecture fssub1 of fssub is
signal a’,p,q,r,s:std_logic;
component xorg
port(a,b:in std_logic;
c:out std_logic);
end component;
component notg
port(a:in std_logic;
a’:out std_logic);
end component;
component andg
port(a,b:in std_logic;
c:out std_logic);
end component;
component org3
port(a,b,d:in std_logic;
c:out std_logic);
end component;
begin
x1:xor3g port map(a,b,bi,diff);
x2:notg port map(a,a’);
x3:andg port map(a’,b,q);
x4:andg port map(a’,bi,r);
x5:andg port map(b,bi,s);
x6:org port map(q,r,s,borr);
end fssub1;
SUB PROGRAM:
XOR GATE:
library ieee;
use ieee.std_logic_1164.all;
entity xorg is
port(a,b,e:in std_logic;
c:out std_logic);
end xorg;
architecture xorg1 of xorg is
begin
c<=a xor b xor e;
end xorg1;
NOT GATE:
library ieee;
use ieee.std_logic_1164.all;
entity notg is
port(a:in std_logic;
a’:out std_logic);
end notg;
architecture notg1 of notg is
begin
a’<=not(a);
end notg1;
AND GATE:
library ieee;
use ieee.std_logic_1164.all;
entity andg is
port(a,b:in std_logic;
c:out std_logic);
end andg;
architecture andg1 of andg is
begin
c<=a and b;
end andg1;
OR GATE:
library ieee;
use ieee.std_logic_1164.all;
entity org3 is
port(a,b,d:in std_logic;
c:out std_logic);
end org3;
architecture org31 of org3 is
begin
c<=a or b or d;
end org31;
HALF SUBTRACTOR

OUTPUT WAVEFORM:

FULLSUBTRACTOR

OUTPUT WAVEFORM:
Viva Questions:
1) What is a half subtractor?

2) What is a full subtractor?

3) What are the applications of subtractors?

4) Obtain the minimal expression for above circuits.

5) Realize a full subtractors using two half subtractors.

RESULT:

Thus the half subtractor and full subtractor circuit was designed and simulated using
Xilinx software and the truth table is verified successfully.