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VLSI Design using Open source tools

The E&ICT Academy at PDPM IIITDM Jabalpur is hosting an Online Winter Faculty Development Programme on VLSI Design using Open source tools from February 10 to 21, 2025. The program includes various topics such as high-level synthesis, logic synthesis, physical design, and low power flow basics, with sessions scheduled from 02:00 PM to 06:00 PM. Registration is open until February 03, 2025, with a fee of INR 500, and participants can register through a provided link.

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7 views

VLSI Design using Open source tools

The E&ICT Academy at PDPM IIITDM Jabalpur is hosting an Online Winter Faculty Development Programme on VLSI Design using Open source tools from February 10 to 21, 2025. The program includes various topics such as high-level synthesis, logic synthesis, physical design, and low power flow basics, with sessions scheduled from 02:00 PM to 06:00 PM. Registration is open until February 03, 2025, with a fee of INR 500, and participants can register through a provided link.

Uploaded by

cr7subho
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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E&ICT Academy, PDPM IIITDM Jabalpur

Online Winter Faculty Development Programme


VLSI Design using Open source tools
February 10 - 21, 2025 : Online live streaming
Jointly Organized by
IIT Guwahati IIITDM Jabalpur IIT Roorkee NIT Patna MNIT Jaipur

Schedule and Course Contents


[February 10 - 21, 2025, 02:00 PM to 06:00 PM]
▪ Introduction to VLSI design flow.
▪ Introduction to High Level Synthesis, Intel HLS Compiler and System Integration, HLS Implementation, Software design with the new HLS Component system
Introduction to Intel SoC FPGAs, Basic SoC lab demo with hands on
▪ High level synthesis- scheduling, binding
▪ Logic synthesis- two level, multilevel logic optimization, encoding
▪ Sequential circuit optimization, FSM synthesis, retiming, state encoding
▪ Library binding
▪ Physical design- partitioning, placement, floor planning, global & channel routing
▪ Layer and Power Planning
▪ Delay Calculations and System Implications
▪ Setup and Hold Discussion Placement Basics and Settings
▪ DRC LVS and Extraction
▪ Low Power Flow Basics
▪ Sign Off

Coordinators RESOURCE PERSONS


Dr Pushpa Raikwal,
Joint- Principal Coordinator, IIITDM Jabalpur • Dr. Sarfraz Hussain, SoECE, REVA University, Bangalore
Email: [email protected], • Dr. Amol Boke, Nine Labs, IIT Guwahati
Mobile: 91-7566961114 • Dr. Bikram Paul, SCEE, IIT Mandi
Prof. Gaurav Trivedi, • Dr. Rahul Shrestha, IIT Mandi
Principal Coordinator, IIT Guwahati • Dr. Shaik Rafi Ahamed, IIT Guwahati
Email: [email protected],

Registration Details
Registration link – Please fill in the registration form Online payment details:
using the following link: • Internet banking
https://forms.gle/uTxD6ZTr56QEMsXz8 Beneficiary Name: PDPM IIITDM Jabalpur
Bank Name: INDIAN BANK
Registration fee: INR 500/- A/C No. : 50018692852
IFSC Code: IDIB000M694
Last Date for Registration: February 03, 2025
• UPI ID: iiitdmj@indianbk
Contact Details
• Email: [email protected], [email protected]
• Mr. Durgesh Kushwaha (+91 7898670354)

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