SECTION 2.

9: RISC ARCHITECTURE IN THE PIC

There are three ways available to microprocessor designers to increase the

I. Increase the clock frequency of the chip. One drawback of this method is that
the higher the frequency, the more power and heat dissipation. Power and heat
dissipation is especially a problem for hand-held devices.
2. Use Harvard architecture by increasing the number of buses to bring more
information (code and data) into the CPU to be processed. While in the case of
x86 and other general purpose microprocessors this architecture is very expen-
sive and unrealistic, in today's microcontrollers this is not a problem. As we
saw in the last section, the PIC 18 has Harvard architecture.
3. Change the internal architecture of the CPU and use what is called RISC archi-
tecture.

Microchip used all three methods to increase the processing power of the
PIC 18 microcontrollers. In this section we discuss the merits of RISC architecture
and examine how the PIC18 microcontrollers have adapted it.

RISC architecture
In the early 1980s, a controversy broke out in the computer design com-
munity, but unlike most controversies, it did not go away. Since the 1960s, in all
mainframes and minicomputers, designers put as many instructions as they could
think of into the CPU. Some of these instructions perfonned complex tasks. An
example is adding data memory locations and storing the sum into memory.
Naturally, microprocessor designers followed the lead of minicomputer and main-
frame designers. Because these microprocessors used such a large number of
instructions and many of them perfonned highly complex activities, they came to
be known as CISC (complex instruction set computer). According to several stud-
ies in the 1970s, many of these complex instructions etched into the brain of the
CPU were never used by programmers and compilers. The huge cost of imple-
menting a large number of instructions (some of them complex) into the micro-
processor, plus the fact that a good portion of the transistors on the chip are used
by the instruction decoder, made some designers think of simplifying and reduc-
ing the number of instructions. As this concept developed, the resulting processors
came to be known as RISC (reduced instruction set computer).
Features of RISC
The following are some of the features of RISC as implemented by the
PICLS microcontroller.
Feature 1
RISC processors have a fixed instruction size. In a CISC microcontroller
such as the 8051, instructions can be 1, 2, or even 3 bytes. For example. look at
the following instructions in the 8051:
CLR C ;Clear Carry flag ,a 1-byte instruction
ADD Accumulator, #mybyte ;a 2-byte instruction
UMP target_address ;a 3-byte instruction
This variable instruction size makes the task of the instruction decoder very
difficult because the size of the incoming instruction is never known. In a RISC
architecbJre, the size of all instructions is fixed. Therefore, the CPU can decode the
instructions quickly. This is like a bricklayer working with bricks of the same size
as opposed to using bricks of variable sizes. Of course, ii is much more efficient
to use bricks of the same size. In the last section we saw how the PIC 18 uses 2-
byte instructions with very few 4-byte instructions.

Feature 2
One of the major characteristics of RISC architecture is a large number of
registers. All RISC architectures have al least 32 registers. Of these 32 registers,
only a few are assigned to a dedicated function . One advantage of a large number
of registers is that it avoids the need for a large stack to store parameters. Although
a stack can be implemented on a RISC processor, it is not as essential as in CISC
because so many registers are available. In the PIC microcontrollers the use of a
256-byte bank for the file register satisfies this RISC feature. The stack for the
PIC18 is covered in the next chapter.

Feature 3
RISC processors have a small instruction set. RISC processors have only
the basic instructions such as ADD, SUB, MUL, LOAD, STORE, AND, OR,
EXOR. CALL, JUMP, and so on. The limited number of instructions is one of the
criticisms leveled at the RISC processor because it makes the job of Assembly lan-
guage programmers much more tedious and difficult compared to CISC Assembly
language programming. This is one reason that RISC is used more commonly in
high-level language environments such as the C programming language rather
than Assembly language environments. It is interesting to note that some defend-
ers of CISC have called it "complete instruction set computer" instead of "com-
plex instruction set computer" because it has a complete set of every kind of
instruction. How many of these instructions are used and how often is another mat-
ter. The limited nwnber of instructions in RISC leads to programs that are large.
Although these programs can use more memory, this is not a problem because
memory is cheap. Before the advent of semiconductor memory in the 1960s, how-
ever, CISC designers had to pack as much action as possible into a single instruc-
tion to get the maximum bang for their buck. In the PIC16 we have around 35
instructions, while the PIC18 has 75 instructions. We will examine more of the
instruction set for the PIC 18 in future chapters.

Feature 4
At this point, one might ask, with all the difficulties associated with RISC
programming, what is the gain? The most important characteristic of the RISC
processor is that more than 95% of instructions are executed with only one clock
cycle, in contrast to CISC instructions. Even some of the 5% of the RISC instruc-