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VL4111 Set 1

PFA

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30 views3 pages

VL4111 Set 1

PFA

Uploaded by

Kumaravel S
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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M.E / M.Tech.

PRACTICAL END SEMESTER EXAMINATIONS, JANUARY 2022


First Semester

VL4111– FPGA Laboratory

(Regulations 2021)

Time : 3 Hours Answer any one Question Max. Marks 100

Aim/Principle/ Tabulation/ Calculation Viva-Voce Recor Total


Apparatus Circuit/ & Results d
required/Procedure Program/Drawing
30 25 25 10 10 100

1. Write a Verilog code for the following circuit diagram and implement using FPGA.

2. “A circuit which is used to select and route any one of the several input signals to a
single output.” Justify the above statement and compare the pre synthesis and post
synthesis for the designed circuit.

3. Write a Verilog code for encoder circuit and compare the pre synthesis and post
synthesis simulation using FPGA

4. Connect a external source with FPGA kit and show how it interfaces with FPGA.

5. Show how the wire and reg data types works in FPGA and analyze the performance.

6. Is logic a data type? If So, analyze the performance using field programmable gate
array.

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7. Analyze the performance of blocking assignment in sequential circuit and verify its
output.

8. Write a Verilog code for ALU and verify its function using FPGA.

9. Construct a model and verify its instruction stack in FPGA

10. Generate a test bench waveform for half adder and analyze the interface between DUT
and test bench in FPGA.

11. Write a suitable testing program for your own model and show how it works on FPGA.

12. Create a simple test bench waveform for two input and gate as well as a flip flip.

13. Create a dynamic array for the analysis port in scoreboard and verify it.

14. Show how mailbox is sharing the data on transmitter and receiver sides and analyze the
performance.

15. Create a proper testbench for the ring buffer FIFO that uses constrained random
verification and verify the values.

16. “Enables us to cover many more system behaviors through random input variations,
random fault injections, and automatic output comparisons”. Justify the above statement
and verify its coverage.

17. Analyze the performance of any two data types in Field Programmable Gate Array.

18. The data type which stores whole numbers that ranges from -2,147,483,647 to
2,147,483,647 for 9 or 10 digits of precision. Implement using FPGA.

19. Demonstrate how the following data types work in FPGA.

i) Byte data type

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ii) Shortint data type

20. Show how the 64 bit IEEE floating point number works in FPGA.

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