Turkish Journal of Computer and Mathematics Education Vol.11 No.

03 (2020),2825- 2837
Research Article

EMBEDDED SYSTEM BASED 1-BIT FULL SUBTRACTOR FOR

ARITHMETIC APPLICATIONS
S Naresh Kumar1,Dr. Mahesh Kaumr Porwal2
1
Assistant Professor,2Associate Professor
Department Of ECE
Sree Chaitanya College of Engineering, Karimnagar

ABSTRACT
In today's VLSI design, static or leakage power consumption is a crucial metric due to component
shrinkage. This research proposes and compares a 10-transistor 1-bit complete circuit to alternatives that
employ 20 and 14 transistors.
Microwind 3.1, a CAD program, was utilized for every circuit simulation.
Reductor layout for feature size The 90nm technology has been applied to determine the values of certain
parameters.
The energy efficiency of the suggested 10-transistor complete subtractor is higher than that of its
competitors.
I. INTRODUCTION (performance, power, and cost) are a balancing
1.1 INTRODUCTION TO VLSI: act in most other areas of engineering as well.
Very large scale integration is frequently However, when transistor size drops, power
abbreviated to VLSI. With the advent of very consumption reduces, space occupied reduces,
large-scale integration (VLSI) technology, the performance increases, and the cost to
electronic sector has experienced unprecedented manufacture decreases.
expansion over the past two decades. In Electronic circuits throughout the first half of the
addition, the intelligence of these applications, 20th century are bulky, power-intensive, cost-
or the processing power they demand, is the sole prohibitive, and unreliable since they rely on
driving force behind the explosive growth of the vacuum tubes. In 1947, at Bell Labs, John
sector. For video and cellular communication, Bardeen and Walter Brattain created the first
low bit rate is now cutting edge since it gives working point contact transistor. Bell Labs
customers a certain degree of processing power introduced the technology to the public, but it
and portability. was a military secret at the time. Transistor.
In 1958, Jack Kilby of Texas Instruments Because it acts as an amplifier and transfers
created the first integrated circuit flip-flop out of resistance between terminals, scientists dubbed
just two transistors. More than two billion it the transistor.
transistors are included in Intel's Itanium An electrical signal can be amplified and
processor, and more than four billion transistors transferred between the input and output
are present in the 16 GB of Flash memory. Over terminals of a transistor, a semiconductor
the next 50 years, the integrated circuit industry device. There is no vacuum, no glass tube, and
is expected to increase at a rate of 53% every no filament. All of its elements are chilly and
year. There hasn't been any innovation that saw solid.
such rapid expansion for so long. Consistent
reductions in transistor count and size, as well as
advancements in processing technology, enable
this phenomenal expansion. The 3p's

2825
Turkish Journal of Computer and Mathematics Education Vol.11 No.03 (2020),2825- 2837
Research Article

of transistors in electronic devices doubles every

half a year. Moore's Law is the name given to
this observation, which has come to fulfil itself.
Transistor count for Intel processors is depicted
in Fig. 1.1.1. Increasing chip size and decreasing
transistor size are both contributing factors to
Moore's Law. Chips can be categorized by their
level of integration into SSI, MSI, LSI, VLSI, or
ULSI.
Figure 1: Quantity of semiconductors sold
around the world
A transistor consists of a control terminal and
two additional terminals that connect or detach
based on the voltage or current applied to the
control terminals, and hence can be thought of as
electrically controlled switches. BJT was created
by Bell Labs not long after the point contact
transistor was first introduced. There is a
considerable improvement in reliability, noise Figure 2: CPU transistors from Intel.
immunity, power efficiency, and speed in Less than ten gates and about six transistors per
bipolar devices. For early IC designs, BJTs were gate characterize small-scale integration (SSI)
the norm. Bipolar transistors can only switch circuits like the inverter (IC 7404). The counter
bigger currents between the emitter and collector (IC74161) is an example of a medium-scale
terminals when modest currents are supplied to integration circuit. It includes thousands of
the base terminal. The greatest number of gates. Even a basic 8-bit processor uses up to
transistors that can be integrated on a single die 10,000 gates in a large-scale integration circuit.
is capped due to the transistors' quiescent power It quickly became evident that fresh names will
dissipation caused by base currents, drawn even be required every five years. If current
when the circuit is not switching. Production of terminology preferences persist, VLSI will be
MOS Transistors started in the 1960s. When not used to characterize the vast majority of ICs
conducting, the MOS transistor provides almost produced after the 1980s. Dennard's Scaling
no current. They are available in NMOS and Law [Dennard74] is similar to Moore's law in
PMOS varieties. The German physicist Julius that it states that as transistors get smaller, they
Lilien field came up with the concept of field get quicker, use less power, and are cheaper to
effect transistors in 1925, and Oskar Heil produce. Time-to-execute-an-application
presented a structure similar to the MOSFET in benchmarks show that computer performance
1935, but early attempts to construct operational has improved even more than raw clock speed.
devices were thwarted by issues with the Currently, the number of cores on a
materials used. semiconductor determines performance rather
In 1965, Gordon Moore noticed that the number than the clock speed. Compared to a single
of transistors that could be made most cheaply transistor, the power requirements of an
on a chip followed a straight line on a semi- integrated design are extremely high. This is
logarithmic scale. He discovered that the number because numerous transistors are involved in the
design. Furthermore, as transistors have shrunk

2826
Turkish Journal of Computer and Mathematics Education Vol.11 No.03 (2020),2825- 2837
Research Article

in size, they no longer switch off entirely. With

millions or billions of transistors on a chip, even
a small amount of current escaping through each
transistor now results in enormous power
consumption.
1.2 INTRODUCTION TO 90nm
TECHNOLOGY
The first company to release an
Industrial 65nm process was Toshiba in 2002,
followed by Fujitsu, STM, NEC, and Intel in
Figure 3: There are now three distinct 90nm
2004. Following the release of their own
process variations available.
techniques, IBM, Motorola, TI, TSMC, and
The third type, low leakage, is used for
Samsung.
integrated circuits (ICs) in which leakage must
Table I: What's special about 90nm technology
be kept to a minimum, such as in embedded
devices, mobile phones, etc.
In 90nm technology, the operating voltage can
range from 0.85 V to 1.2 V. In the instance of
Microwind, the rule file has it set to 1V as a
middle ground between the several possible
The advantages of 90nm technology over 180nm
processes.
are:
1.3 LOW POWER VLSI:
• Increases in velocity of 1.20 times
There is no other source of energy on Earth but
• There is a doubling in density.
the sun and nuclear power. Over billions of
• A halving of power output
years, the Earth has stored the energy of the sun
Process variants in 90 nm technology:
in the form of plant growth, which has been
Several variations on the 90nm technique are
converted to carbon and later to oil, gas, coal, or
now in use. Maximum speed at the expense of a
other carbon-based fuels, making it function like
massive leakage current is represented by a
a massive battery. These days, we may also
value of 1. Due to its focus on high-speed
harness energy from the wind, tides, and
devices like fast processors and digital signal
precipitation (hydro) or the earth itself
processors, this technology is classified as "high
(geothermal) in addition to the sun (solar
speed" and is therefore absent from the
power). Changes occur in the form of energy.
Microwind 90nm rule file.
The importance of sunlight to plant
The second technological alternative, general
development. To carbon, via plants. Coal to
purpose, is aimed at commodity items in which
flame. Heat into usable energy. Powering
the speed factor is not crucial and features a
batteries using electricity. Converting chemicals
leakage current that is an order of magnitude
into energy (discharged batteries). Power to
lower than that of the high speed variation while
music (through an MP3) by electrical current.
also reducing the gate switching delay by 50%.
The last transformation releases a portion of the
energy as sound waves into space. As the music
is deciphered and performed, the rest is
converted into heat. It has been dispersed
throughout space (maybe warming our fingertips

2827
Turkish Journal of Computer and Mathematics Education Vol.11 No.03 (2020),2825- 2837
Research Article

slightly on a cold night) and is now gone the expense of greater physical capacitance or
forever. Energy changes are so ubiquitous in our higher circuit activity. Unfortunately, there is a
daily lives that we usually have no idea they are trade-off in speed as we decrease the supply
happening. Most of the time, they happen voltage, with delays becoming increasingly
without anyone noticing. severe as VDD gets closer to the threshold
Batteries eventually die and must be recharged voltage VT of the devices. Because of this, VDD
or replaced. Designers of consumer electronics is typically only effective between roughly 2-3
are always looking for ways to improve their VT. The below equation shows that the strategy
products, whether it's through new features, incurs a cost in the form of a reduction in
smaller form factors, or longer battery life. The switching speed.
constant need to lessen reliance on fossil fuels
and cut down on greenhouse gas emissions
compels us to seek for low power solutions for II. POWER ANALYSIS IN CMOS
all electronic difficulties in applications that are CIRCUITS
permanently plugged into an electrical outlet. 2.1. INTRODUCTION
About 150 watts is the upper limit for high- Digital CMOS circuits' power dissipation can be
performance chips before liquid cooling or other modelled as:
expensive heat sinks are required. The electricity
needs of American data centers and servers
totaled 61 billion kWh in 2006 [EPA07]. This is Where Pavg is the average power dissipation, P
equivalent to the production of 15 power plants, dynamic is the power dissipation caused by the
would cost around $4.5 billion, and would use switching of transistors, P short circuit is the
1.5% of the total energy utilized in the United power dissipation caused by a short circuit
States. Whereas the size of a chip used to be a between the power supply and ground, P leakage
limiting factor in its capabilities, today it is is the power dissipation caused by leakage
typically power consumption. High-performance currents, and P static is the power dissipation
design now automatically means energy- caused by static electricity.
efficient design. 2.1.1 DYNAMIC POWER DISSIPATION
1.4 Power Optimization Methods Charging and discharging capacitances in the
Below, we will go over how minimizing voltage, circuit generate the dynamic power dissipation P
capacitance, and switching activity can help save dynamic. As illustrated in Figure 2.1, we will
power. use a CMOS inverter supplying power to a load
1.4.1 Voltage capacitor CL to demonstrate how dynamic
Reducing voltage, which has a quadratic power dissipation is calculated. The output
relationship to power, is the most efficient way capacitor is the sum of the parasitic capacitances
to cut down on energy use. A reduction of the of the Nmos and Pmos transistors (gate-to-bulk
supply voltage by a factor of two results in a and source- and drain-diffusion to bulk), the
reduction of the power consumption by a factor inverter cell's internal and external wiring, and
of four without the need of any special circuits the circuits driven by the inverter.
or technologies. This reduction in power
consumption is not localized to any one chip's
sub-circuit or block, but rather permeates the
entire layout. These considerations explain why
engineers so frequently opt for lower voltage at

2828
Turkish Journal of Computer and Mathematics Education Vol.11 No.03 (2020),2825- 2837
Research Article

primary areas: lowering the voltage supply and

increasing the effective capacitance. Since
power savings are proportional to the square of
Vdd, one of the most aggressive methods
involves lowering the voltage at which the
supply operates. While this type of reduction is
typically quite effective, it requires the designer
to address a number of critical aspects to ensure
Figure 4: The three phases of a CMOS inverter's
the system's performance is not compromised.
operation are as follows: (a) CMOS inverter, (b)
Delay propagation (or the rate at which a circuit
charging, and (c) discharging.
moves) increases when the supply voltage is
Since the output capacitor can be connected
lowered. The transition of industry from a
directly to ground, a discharge current can flow
supply voltage value to a smaller one is quite
through it. The load capacitor's 12 CL.V2dd of
costly and slow since the input and output signal
energy is wasted in the Nmos transistor and the
levels should be compatible with the peripheral
connection. This means that across the range [0,
electronics. In contrast, new design methods are
T], the dynamic power dissipated by a CMOS
mostly responsible for lowering switching
inverter may be calculated as:
activity and/or capacitance for a given
technology. As a result, instead of spending a
tons of money on brand new equipment, a low-
2.1.2 POWER REDUCTION APPROACHES power version of an existing circuit can be built.
OF DYNAMIC DISSIPATION. Several circuit-level design strategies, such as
The average switching power dissipation P optimized logic synthesis and balanced routes,
dynamic of CMOS logic gates is shown to be must be implemented in order to reduce
related to the load capacitance CL, the square of switching activity, and a thorough examination
Vdd, the switching activity, and the clock of signal transition probabilities is essential. By
frequency f, as shown by the derived equation. downsizing transistors and choosing the right
Thus, the power reduction can be accomplished logic family, for example, the output capacitance
in a variety of ways, including (but not limited can be decreased. The Pentium-I consumed 15
to) the following: watts of electricity at 5 volts and 66 megahertz
(i) decreasing the output capacitance CL (or the (MHz), while the Pentium-II consumed 8 watts
switching activity), at 3.3 volts and 133 MHz, respectively.
(ii) decreasing the power supply voltage Vdd (or 2.1.3 SHORT-CIRCUIT POWER
the average number of transitions per clock DISSIPATION
cycle), and The energy lost in a short circuit During the
(iii) decreasing the clock frequency. switching phase, pshortcircuit occurs when
Combining two or more of the aforementioned current flows through the direct path between
methods apparently allows for minimal power the power source and the ground. Think about
reduction. The effective capacitance, or switched the CMOS inverter from Figure1.4 again. Short-
capacitance, is the product of the output circuit current flows between the power supply
capacitance and the switching activity, and its and the ground during the extremely brief time
decrease is a common low power method. interval in which both Nmos and Pmos
If a designer wants to cut down on power transistors are ON when the input signal
consumption, he or she should focus on two transitions from the logic value '1' to the logic

2829
Turkish Journal of Computer and Mathematics Education Vol.11 No.03 (2020),2825- 2837
Research Article

value '0', or vice versa. A CMOS inverter's A paper proposing a reversible logic gate was
response to a short circuit is seen in Figure 1.2. presented in 2012 by Parminder Kaur[et al.
Specifically, the Nmos transistor of the inverter Many studies highlight reversible logic gates as
circuit conducts if the input voltage rises beyond the newest area of study. In this paper, the
the threshold voltage, Vthn, and the Pmos author pursues a fault-tolerant complete adder.
transistor conducts until the input voltage The design may function independently as a full
reaches the value of (Vdd - |Vthp|). That's why adding and subtracting unit. The inputs and
there's a window of time when both transistors outputs both have the same parity, as this is a
are active. As the output voltage drops, the reversible adder cell that preserves parity. Any
Nmos transistor is discharging the capacitance desired Boolean function can be synthesized
CL. The Pmos transistor can conduct because with the help of the suggested parity-preserving
the drain-to-source voltage drop is no longer reversible adder. It makes it easy to spot any
zero. When the input voltage transition is problem with the circuit at the principal outputs
complete, the Pmos is turned off, ending the if it only impacts a single signal. The suggested
short-circuit current. In the case of a solution is more effective than existing
symmetrical inverter with identical rise and fall alternatives while also requiring less hardware
periods, the output waveform begins to climb as complexity because to its reduced gate count,
both MOSFET transistors are ON due to the garbage outputs, and constant inputs.
short-circuit current component originating from Prashanth[et al.] published the reversible logic
the falling edge of the input signal. gate in 2013. Low-cost CMOS design has
Total power consumption is calculated by recently benefited from the development of
averaging the short-circuit current component of reversible logic gates. Quantum computing,
the rising edge of the input signal with the nanotechnology, and optical commuting are just
equivalent current component of the falling a few of the many uses for reversible logic gates.
edge. An effective fault-tolerant carry skip
III. LITERATURE REVIEW adder/subtractor is proposed here. This
With the proliferation of battery-powered mobile document also includes the designs for a
devices like smartphones, PDAs, and laptops, complete adder/subtractor and a parallel
manufacturers are under pressure to create VLSI adder/subtractor, which are prerequisites for
and ultra-LSI designs with better power delay creating a carry skip adder/subtractor. In terms
characteristics. One of the most fundamental of gate count, constant input, garbage output,
building elements of all these circuit and quantum cost, all of the designs in this study
applications is the full adder/subtractor, are effective. The proposed design is an all-in-
therefore studying it has been a primary focus of one adder and subtractor that performs as either
researchers for many years. To construct 1-bit function depending on the control logic input.
complete adder cells, many different logic The design of a Carry skip adder/subtractor
models were explored, each with their own requires knowledge of both the Full
benefits and drawbacks. Generally speaking, the adder/subtractor and the Parallel
reported designs can be broken down into two adder/subtractor.
groups: 1) static styles, and 2) dynamic styles. In A work on the Reversible Logic Gate was
comparison to their dynamic counterparts, static presented in 2014 by Dondapati Naresh[et al]. In
logic designs are typically more secure, easier to the very-large-scale-integration (VLSI) realm,
implement, and less demanding of power, at the reversible logic gates are crucial. These days, it's
expense of a larger on-chip footprint. used for a wide variety of tasks, including

2830
Turkish Journal of Computer and Mathematics Education Vol.11 No.03 (2020),2825- 2837
Research Article

quantum computing, optical computing, cellular boost computational speed. Quantum efficiency
automata and digital signal processing on is enhanced by the comparator layout that makes
quantum dots, low-power CMOS architecture, use of the half subtraction technique. The entire
and nanotechnology. In this study, we suggest a subtraction method is used in the comparator
fault-tolerant carry skip adder/subtractor that design, which successfully decreases the number
employs reversible logic gates that preserve of reversible gates and eliminates garbage
parity. The suggested architecture can function output.
as either a carry skip adder or a carry skip IV. SUBTRACTOR CIRCUITS AND
subtracter, depending on the control logic input. EXISTING SYSTEMS
When ctrl is set to zero, the design functions as a 4.1 SUBTRACTOR
parallel adder, and when it's set to one, it One of the four elementary operations in binary,
functions as a parallel subtractor, according to subtraction is the primary function of a
the control logic input. subtractor, a digital circuit. Subtractors are used
S. Mounika[et al.] published a study advocating extensively in many computer and other device
for reversible logic as a promising new area for processors, and not just for arithmetic
low-power computing in 2015. It will be useful computations. This includes areas where it is
in numerous fields, including computers (both necessary to calculate addresses, table indexes,
quantum and classical), nanotechnology, optical and similar operations. Moreover, it can be an
computing, and others. A fault-tolerant carry- Attenuator in various situations.
skip adder and subtractor is proposed here. This Most subtractors work with binary integers, but
document also includes the designs for full and they can be built for other binary code
parallel adders and subtractors, which are representations like excess-3 or grey code or
prerequisites for creating a carry skip even binary-coded decimal. Two's complement
adder/subtractor. In terms of gate count, constant or ones' complement is frequently used to
input, garbage output, and quantum cost, all of indicate negative integers when subtracting two
the designs in this study are effective. positive values. Modifying an adder into an
Subramanian Saravanan[et al.] published an adder-subtractor is often seen as somewhat
article in 2016 describing Optical information important due to the simplicity with which
processing, low-power CMOS design, DNA computations can be conducted. A more
computing, etc. are just a few of the many complicated subtractor is needed for other
potential new areas where reversible logic is signed number representations.
being put to use. Comparators are crucial in Inputs to the circuit device can range from two
industrial automation as they separate bad to three, depending on the nature of the
patterns from good ones. These comparators application or the desired outcome of the task at
have been developed in the past, albeit with a hand. If we have two inputs, we can use a Half-
higher computational cost and number of Subtractor, and if we have three, we can use a
reversible gates. Each of these comparators Full-Subtractor.
utilizes a form of "propagation" to examine the When performing subtraction between two bits,
data. The comparators' performance will suffer a complete subtractor takes into account a third
as a result of this. To address this issue, the bit, called a borrow bit, from another circuit.
authors of this study present a (Thapliyal Therefore, it accepts input from three separate
Ranganathan) TR gate-based efficient bits. Two bits, difference and borrow, are
comparator that makes use of a complete produced as a result. Everywhere we go, we
subtraction and a half subtraction approach to encounter various forms of digital media,

2831
Turkish Journal of Computer and Mathematics Education Vol.11 No.03 (2020),2825- 2837
Research Article

including smartphones, computers, televisions,

video game consoles, and so on. We must carry
out the arithmetic operations in the devices'
CPUs. One of the most fundamental arithmetic
operations is subtraction. One bit, two bits, etc.,
can be subtracted using a subtractor. There must
be at least three inputs for a full subtractor of
one bit. Traditional CMOS technology allows
for the building of a complete subtractor.
A full subtractor is a combinational circuit that
uses the minuend, subtrahend, and borrow-in
bits to execute subtraction. Full subtraction
produces Difference and Borrow as output. In
this post, we break down the XOR gate as a
whole subtractor. Used in addition to the NOT
gate, AND gate, and XOR gate. The gate level
diagram of a full subtractor is displayed in Fig.
2.5. In this case, a full subtractor is constructed
by joining two half subtractors.

Fig 5. In CMOS, a complete subtractor with 20

transistors

Table 4.1 below displays the truth table for a full

1-bit subtractor..
If we examine how the Full-Subtractor operates,
we see that it is possible to subtract the two
given binary values by first adding the
complement of the subtrahend to the minuhend.
This technique can also be used to transform the
Fig 6. All-gate subtraction circuit

2832
Turkish Journal of Computer and Mathematics Education Vol.11 No.03 (2020),2825- 2837
Research Article

subtraction operation into an addition operation accordance with the input bit variation make up
that can be implemented in machines using the rest. Ten transistors, five PMOS and five
complete adders. Now, in a direct subtraction NMOS, make up the borrow section, which is
method using logic circuits, each subtrahend bit analogous to the carry section in a standard 1-bit
of the number is subtracted from its full adder. Comparing the truth tables of a one-
corresponding significant minuhend bit to bit adder and a one-bit subtractor reveals that
generate a separate bit. A 1 is "borrowed" from their respective outputs sum and difference are
the next most significant position if the identical, while the adder's output carry differs
minuhend bit is less than the subtrahend bit. in four of the eight possible results.
Simply put, the Full-Subtractor performs a Three PMOS transistors (M1, M3, and M5) and
subtraction operation between two bits (a three NMOS transistors (M2, M4, and M6)
minuend and a subtrahend) while also make up the 6T XOR gate, four transistors (M7,
accounting for whether or not a '1' has been M8, M19, and M20) function as two inverters,
borrowed by the preceding adjacent lower and transistors (M9, M10, M13, M14, and M15)
minuend bit. Therefore, a Full-Subtractor takes from the PMOS side and transistors (M11, 12,
in three bits—the two bits to be subtracted and a 16, 17, and 18) from the NMOS side manage the
borrow bit named Bin—at its input. Difference borrow function. When A=1, B=1, and C=1 are
(D) and Borrow (Bo) are the two possible used as inputs, the difference output should be 1
results. The Borrow output bit indicates whether and the borrow output should be 1.
or not the lowest minuend bit requires a '1' to be
"borrowed" from the next available highest
minuend bit.
The equations provide the Boolean expression
for the two output variables.

4.2. ONE BIT FULL SUBTRACTOR BY

USING 20 TRANSISTORS
Figure 4.1 depicts the circuit layout for a 20-
transistor 1-bit full subtractor. When compared Fig.7 A full-bit, 1-transistor subtractor
to standard full subtractor architectures, full 4.3. ONE BIT FULL SUBTRACTOR USING
subtractor designs use less transistors. To create 14 TRANSISTORS
a full subtractor, 6 transistors are used for the Figure 4.3 depicts the 14 transistors needed to
difference equation, 10 for the borrow equation, create the XOR-XNOR modules and 2x1
and the final 4 for the inverting operation. multiplexer that make up the one bit full
In this study, we seek to use the extensive subtractor circuit. Two intermediate signals are
literature on adder design to create a one-bit generated by the XNOR - XOR modules and
complete subtractor with a minimal number of sent to the 21 multiplexer. The output of the
transistors. Twenty transistors make up the aforementioned logic gates serves as one input
circuit; one 6-transistor EX-OR module, two to a 21 multiplexer, while the output of the third
CMOS inverters (one at the difference output input serves as the multiplexer's selection line. A
and another at the borrow output), and a 10- 6T XOR-XNOR cell and a multiplexer provide
transistor section that generates the borrow in the difference output, whereas a 6T XOR gate

2833
Turkish Journal of Computer and Mathematics Education Vol.11 No.03 (2020),2825- 2837
Research Article

produces the borrow output. Transistors M1, size, weight, and cost. This can be accomplished
M2, M3, and M4 all use the 4T XOR module. by cutting down on the number of transistors
Combining the XOR module's four transistors used in the design of the circuit.
with the XNOR module's two, we get a 6T ONE BIT SUBTRACTOR USING 10
XOR-XNOR module. To create a 2x1 TRANSISTORS
multiplexer, transistors M9 and M10 are used Figure 4.2 presents the logic circuit of a one-bit
here. Bit C is the multiplexer's choose or control complete subtractor design that makes use of
input. However, besides OR and NOR, XOR two XOR gates and one multiplexer. This design
and XNOR are also used to provide inputs to has three inputs, such as A, B, and C, and two
this multiplexer. The difference output of the outputs, which are labelled Difference and
subtractor is the XNOR output if C=1, and the Borrow respectively. The implementation of the
XOR output if C=0. The input combination and transistor level circuit consists of four XOR
the other module, a 6T XOR-XNOR cell and a gates built out of transistors, as well as a two-
multiplexer, generate the borrow output. transistor 2x1 multiplexer. In addition to this, the
Modules M7, M8, M11, M12, M13, and M14 differential outputs are derived from second
are all 6T XOR modules. The XOR CELL based XOR gates and are borrowed from the
feedback inverter is the main component of this multiplexer.
setup.

Fig 9. A full subtractor logic cell with only one

bit proposed.
The multiplexer takes the logic value from the
output of the first XOR gate, which is treated as
Fig.8. Fourteen-transistor full-bit subtractor for a selection line. The multiplexer takes inputs
one bit. from both the B and the C.
V. PROPOSED METHODS
These days, one of the most difficult challenges
in the design of digital integrated circuits is
overcoming the power consumption and sub
threshold leakages. A microprocessor chip is the
foundation for expanding both the functionality Fig. a Fig. b
and the density of transistors. The scaling Fig.10 a) (b) The total number of XOR gates and
function contributes to the integrated circuit multiplexers in the circuit.
design's improved performance as well as its The XOR gate and multiplexer transistor-based
increased speed of operation. Leakage current circuits are depicted in (a) and (b) of Figure 6.2.
and power are two issues that frequently arise in The circuit diagram for a 10-transistor-strong
the design of digital circuits in the modern day. complete one-bit subtractor is depicted in Figure
Improving the digital system's reliability can be For the first EX-OR gate, we use the first four
performed by reducing the circuit's physical transistors (M1, M2, M3, and M4), and for the

2834
Turkish Journal of Computer and Mathematics Education Vol.11 No.03 (2020),2825- 2837
Research Article

second, we use the fifth through tenth. Microwind 3.1, and several different low-
Multiplexer components M7 and M8 are a pair transistor-count complete subtractor circuits
of transistors. With some tweaks to the were analyzed. Area, Power, and Delay were
connections and the choice of input combination measured and compared to a standard complete
to the multiplexer, the suggested design was subtractor with one bit of precision using the
based on a 10T one-bit full adder. Here, the simulation results.
choose line leading out of the first XOR cell is
the input to the second XOR cell and a
multiplexer. The difference output is the
complement of input bit C if the first XOR
output is at logic 0; otherwise, the difference
output is the same as input bit C only. Borrow
output is input bit C only if the first EX-OR
output is a logical 0. Similarly, if the first output
of an EX-OR gate is logic 1, then only input bit
B will be borrowed at the output. Figure 5.8
shows the timing waveforms for all the possible Fig.13. Microwind circuit area for 20 transistors.
input bit combinations, illustrating the full
operation of the device.

Fig.14. Circuit layout using microwind for 14

transistors
Fig.11 A 10-transistor, 1-bit subtraction circuit.

Fig.12 The timing waveform of a 10-transistor,

1-bit complete subtractor.
Fig.15. Circuit layout using microwind for 10
VI. RESULTS AND DISCUSSIONS
transistors
All of the simulation in this work was performed
at 90nm technology using the CAD tool

2835
Turkish Journal of Computer and Mathematics Education Vol.11 No.03 (2020),2825- 2837
Research Article

and finds that the 10T version is the most

effective.

Fig.16. Timing and power consumption for a 20-

transistor microwind circuit Fig 19: Comparative study of the footprints of
many full-bit, one-bit subtractor circuits

Fig.17. Timing and power consumption for a 14- Fig 20: Delay performance investigation of
transistor microwind circuit. various complete subtractor circuits with 1 bit of
precision

Fig.18. Power and delay in a microwind circuit

with 10 transistors Fig 21. Comparison of power consumption over
a range of 1-bit complete subtractor circuits
In figures 7.7, 7.8, and 7.9, we saw the results of
our examination of the area, latency, and power
consumption of several different kinds of one-bit
complete subtractor circuits.
Table 7.1. The outcomes of various one-bit full
subtraction circuit simulations. Table 7.1
compares the energy and EDP efficiency of one
bit complete subtractors of 10T, 14T, and 20T

2836
Turkish Journal of Computer and Mathematics Education Vol.11 No.03 (2020),2825- 2837
Research Article

VII. CONCLUSION AND FUTURE Circuits and Systems I: Regular Papers, vol.
SCOPE 66, no. 3, pp. 1042-1050, March 2019.
CONCLUSION: 7) Design and analysis of a novel low-power
The findings indicate that the 10T one bit and energy-efficient 18T hybrid full adder
complete subtractor needs less room than its Majid Amini-Valashani, Mehdi Ayat, Sattar
rivals. Mirzakuchaki *Department of Electrical
Even though it uses less power than its Engineering, Iran University of Science and
competitors, the 10T one bit complete subtractor Technology (IUST), Tehran, Iran,
causes more delay than the 14T and 20T models. Microelectronics Journal (2018).
As a result, the 10T one-bit complete subtractor 8) A. Shams, T. Darwish, M. Bayoumi,
decreases delay and consumes a significant Performance analysis of low power 1-Bit
amount of less power and space. CMOS full adder cells, IEEE Trans. Very
FUTURE SCOPE : Large Scale Integr. VLSI Syst. 20 (7) (2002)
It is possible to develop the circuit to produce a 20–29.
powerful multiplier for signal and picture 9) M. Zhang, J. Gu, C.H. Chang, A novel
processing. hybrid pass logic with static CMOS output
Applications that make use of this technology drive full-adder cell, in: Int. Symp. Circuits
are ADCs and DACs. Syst., ISCAS, Bangkok, Thailand, 2003, pp.
To find out how many transistors are in the 317–320.
suggested 10-transistor architecture, 10) S. Goel, A. Kumar, M. Bayoumi, Design of
investigations are presently underway. robust, Energy-Efficient full adders for
REFERENCES Deep-Submicrometer design using Hybrid-
1) Neil Weste and D. Harris, “CMOS VLSI CMOS logic style, IEEE Trans. Very Large
Design: A Circuit and System Perspective,” Scale Integr. VLSI Syst. 14 (12) (2006)
Pearson Addition Wesley, third Edition, 1309–1321.
2005. 11) P. Kumar, R.K. Sharma, An energy efficient
2) Ken Martin, Digital Integrated Circuit logic approach to implement CMOS full
Design, Oxford University Press, New York, adder, J Circuit Syst. Compd. 26 (5) (2017)
2000. 240–260.
3) CMOS Digital Integrated Circuits Analysis
and Design Third Edition2003, By Sung-Mo
Kang, Yusuf Leblebici.
4) Anamika Sharma, Rajesh Mehra “Area
Efficient Layout Design & Analysis of Full
Subtractor” IJSRET EATHD-2015
Conference Proceeding, 14-15 March, 2015.
5) Kamal Jeet Singh, Rajesh Mehra “Design
&Analysis of Full Subtractor using 10T at
45nm Technology” IJETT, Volume 35
Number 9 - May 2016.
6) B. K. Mohanty and P. K. Meher, "Area–
Delay–Energy Efficient VLSI Architecture
for Scalable In-Place Computation of FFT
on Real Data," in IEEE Transactions on

2837