UNIT I

COMBINATIONAL LOGIC
Combinational Circuits Analysis and Design Procedures - Binary Adder- Subtractor -Decimal Adder -
Binary Multiplier - Magnitude Comparator - Decoders Encoders Multiplexers - Introduction to HDL
HDL Models of Combinational circuits.

COMBINATIONAL CIRCUITS
A combinational circuit consists of logic gates whose outputs at any time are determined from only the
present combination of inputs.
A combinational circuit performs an operation that can be specified logically by a set of Boolean
functions.

Sequential circuits:
Sequential circuits employ storage elements in addition to logic gates. Their outputs are a function of
the inputs and the state of the storage elements.
Because the state of the storage elements is a function of previous inputs, the outputs of a sequential
circuit depend not only on present values of inputs, but also on past inputs, and the circuit behavior must
be specified by a time sequence of inputs and internal states.

ANALYSIS PROCEDURE

Explain the analysis procedure. Analyze the combinational circuit the following logic diagram.
(May
2015)

The analys is o f a co mbinat ional circuit requ ir es t hat we deter mine t he fu nct io n t hat
t he cir cuit implement s.
The analys is can be per for med manually by find ing t he Bo o lean fu nct io ns o r trut h
t able o r by using a co mput er simulat io n pro gram.
The first st ep in t he analys is is t o make t hat t he g iven circuit is co mb inat io nal o r
sequent ial.
Once t he lo gic diagram is verified t o be co mbinat io nal, o ne can pro ceed t o o bt ain t he
out put Boo lean funct io ns or t he t rut h t able.
To obtain the output Boolean functions from a logic diagram,
Label all gate outputs that are a function of input variables with arbitrary symbols or names.
Determine the Boolean functions for each gate output.
Label the gates that are a function of input variables and previously labeled gates with other
arbitrary symbols or names. Find the Boolean functions for these gates.
Repeat the process in step 2 until the outputs of the circuit are obtained.
By repeated substitution of previously defined functions, obtain the output Boolean functions in
terms of input variables.

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 Logic diagramforanalysis example

The Boolean functions for the above outputs are,

Proceed to obtain the truth table for the outputs of those gates which are a function of previously
defined values until the columns for all outputs are determined.

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 DESIGNPROCEDURE
Explain the procedure involved in designing combinational circuits.
The design of combinational circuits starts from the specification of the design objective and culminates
in a logic circuit diagram or a set of Boolean functions from which the logic diagram can be obtained.
The procedure involved involves the following steps,
From the specifications of the circuit, determine the required number of inputs and outputs and assign a
symbol to each.
Derive the truth table that defines the required relationship between inputs and outputs.
Obtain the simplified Boolean functions for each output as a function of the input variables.
Draw the logic diagram and verify the correctness of the design.

**************************************************

CIRCUITS FOR ARITHMETIC OPERATIONS

Half adder:
Construct a half adder with necessary diagrams. (Nov-06,May- 07)

A half-adder is an arithmetic circuit block that can be used to add two bits and produce two outputs
SUM and CARRY.
The Boolean expressions for the SUM and CARRY outputs are given by the equations

Truth Table:

Logic Diagram: Half adder using NAND gate:

*************************

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Full adder:
Design a full adder using NAND and NOR gates respectively. (Nov -10)

A Full-adder is an arithmetic circuit block that can be used to add three bits and produce two outputs
SUM and CARRY.
The Boolean expressions for the SUM and CARRY outputs are given by the equations

Truth table:

Karnaugh map:

K-Map for Sum K-Map for Carry

C = AB + BX + AX

Logic diagram:

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Full adder using Two half adder:

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Half subtractor:
Design a half subtractor circuit. (Nov-2009)

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A half-subtractor is a combinational circuit that can be used to subtract one binary digit from anotherto
produce a DIFFERENCE output and a BORROW output.
been borrowed to perform the subtraction. The
Boolean expression for difference and borrow is:

Logic diagram:

*************************************

Full subtractor:

Design a full subtractor. (Nov-2009,07)

A full subtractor performs subtraction operation on two bits, a minuend and a subtrahend, and also takes

or not.
As a result, there are three bits to be handled at the input of a full subtractor, namely the two bits to be
subtracted and a borrow bit designated as Bin .
There are two outputs, namely the DIFFERENCE output D and the BORROW output Bo. The
ossible higher
minuend bit. The Boolean expression for difference and barrow is:

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 K-Map:

Full subtractor using two half subtractor:

*************************************

Parallel Binary Adder: (Ripple Carry Adder):

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Explain about four bit adder. (or) Design of 4 bit binary adder subtractor circuit. (Apr 2019)
A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected
to the input carry of the next full adder in the chain.
Addition of n-bit numbers requires a chain of n- full adders or a chain of one-half adder and n-1 full
adders. In the former case, the input carry to the least significant position is fixed at 0.
Figure shows the interconnection of four full-adder (FA) circuits to provide a four-bit binary ripple carry
adder.
The carries are connected in a chain through the full adders. The input carry to the adder is C0, and it
ripples through the full adders to the output carry C4. The S outputs generate the required sum bits.
Example: Consider the two binary numbers A = 1011and B = 0011. Their sum S = 1110 is formed with
the four-bit adder as follows:

The carry output of lower order stage is connected to the carry input of the next higher order stage.
Hence this type of adder is called ripple carry adder.
In a 4-bit binary adder, where each full adder has a propagation delay of tp ns, the output in the fourth
stage will be generated only after 4tp ns.
The magnitude of such delay is prohibitive for high speed computers.
One method of speeding up this process is look-ahead carry addition which eliminates ripple carry
delay.

**********************************
Complement of a number:
complement:
The 1 s complement of a binary number is formed bychanging 1 to 0 and 0 to 1.
Example:
1.
2.
2

number.
Example:
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 1. T
2. T

The subtraction of unsigned binary number can be done by means of complements.

Subtraction of A-
Check the resulting number. If carry present, the number is positive and remove the carry.
of result and put
negative sign.
Example:
Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction
(a) X - Y and (b) Y - X
Solution:
(a) X = 1010100
2 s complement of Y = + 0111101
Sum= 10010001
Discard end carry. Answer: X - Y = 0010001
(b) Y = 1000011
2 s complement of X= + 0101100
Sum= 1101111
There is no end carry. Therefore, the answer is Y - X = -(2 s complement of 1101111) =-0010001.

****************************

Parallel Binary Subtractor:

The subtraction of unsigned binary numbers can be done most conveniently by meansof complements.
The subtraction A - B B and adding it to A
he least significant pair

the input carry.

The circuit for subtracting A - B consists of an adder with inverters placed betweeneach data input B and
the corresponding input of the full adder. The input carry Cin mustbe equal to 1 when subtraction is

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performed. The operation thus performed becomes A B , plus 1. This is equal
to A B.
For unsigned numbers, that gives A-B if A>=B B - Aif A <B. For signed
numbers, the result is A - B, provided that there is no overflow.

****************************

Fast adder (or) Carry Look Ahead adder:

Design a carry look ahead adder circuit. (Nov-2010)
The carry look ahead adder is based on the principle of looking at the lower order bits of the augend
and addend to see if a higher order carry is to be generated.
It uses two functions carry generate and carry propagate.

Consider the circuit of the full adder shown in Fig. If we define two new binaryvariables

the output sum and carry can respectively be expressed as

Gi is called a carry generate, and it produces a carry of 1 when both Ai and Bi are 1,regardless of
the input carry Ci. Pi is called a carry propagate, because it determines whether a carry into stage i will
propagate into stage i + 1 (i.e., whether an assertion of Ci will propagate to an assertion of Ci+1 ).

We now write the Boolean functions for the carry outputs of each stage and substitutethe value
of each Ci from the previous equations:

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The construction of a four-bit adder with a carry lookahead scheme is shown in Fig.
Each sum output requires two exclusive-OR gates.
The output of the first exclusive-OR gate generates the Pi variable, and the AND gate generates the Gi
variable.
The carries are propagated through the carry look ahead generator and applied as inputs to the second
exclusive-OR gate.
All output carries are generated after a delay through two levels of gates.
Thus, outputs S1 through S3 have equal propagation delay times. The two-level circuit for the output
carry C4 is not shown. This circuit can easily be derived by the equation-substitution method.

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 ******************************

4 bit-Parallel adder/subtractor:
Explain about binary parallel / adder subtractor. [NOV 2019]
The addition and subtraction operations can be combined into one circuit with one common binary adder
by including an exclusive-OR gate with each full adder. A four-bit adder subtractor circuit is shown in
Fig.
The mode input M controls the operation. When M = 0, the circuit is an adder, and when M = 1, the
circuit becomes a subtractor.

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It performs the operations of both addition and subtraction.
It has two 4bit inputs A3A2A1A0 and B3B2B1B0.
The mode input M controls the operation when M=0 the circuit is an adder and when M=1 the circuits
become subtractor.
Each exclusive-OR gate receives input M and one of the inputs of B .
When M = 0, we have B xor0 = B. The full adders receive the value of B , the input carry is 0, and the
circuit performs A plus B . This results in sum S3S2S1S0and carry C4.
When M = 1, we have B xor 1 = B C0 = 1. The B inputs are all complemented and a 1 is added
through the input carry thus pr
Now the data A3A2A1 A0 3B2B1B0to produce the sum i.e., A-B if
A -A if A<B.

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Comparators
Design a 2 bit magnitude comparator. (May 2006)

It is a combinational circuit that compares two numbers and determines their relative magnitude. The
output of comparator is usually 3 binary variables indicating:
A<B, A=B, A>B

1-bitcomparator: Le begin with 1bit comparator and from the name we can easily make out that this
circuit would be used to compare 1bit binary numbers.
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 A B A>B A=B A<B
0 0 0 1 0
1 0 1 0 0
0 1 0 0 1
1 1 0 1 0

For a 2-bit comparator we have four inputs A1 A0 and B1 B0 and three output E (is 1 if two numbers are
equal) G (is 1 when A>B) and L (is 1 when A<B) If we use truth table and K-map the result is

Design of 2 bit Magnitude Comparator.

The truth table of 2-bit comparator is given in table below

Truth table:

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K-Map:

Logic Diagram:

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 ********************

4 bit magnitude comparator:

Design a 4 bit magnitude comparators. (Apr 2019)

Input

Function Equation

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 *************************

BCD Adder:
Design to perform BCD addition.(or) What is BCD adder? Design an adder to perform arithmetic
addition of two decimal bits in BCD. (May -08)(Apr 2017,2018)[Nov 2019]

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Consider the arithmetic addition of two decimal digits in BCD, together with an input carry from a
previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than 9 + 9 + 1
= 19, the 1 in the sum being an input carry.
Suppose we apply two BCD digits to a four-bit binary adder. The adder will form the sum in binary and
produce a result that ranges from 0 through 19. These binary numbers are listed in Table and are labeled
by symbols K, Z8, Z4, Z2, and Z1. K is the carry, and the subscripts under the letter Z represent the
weights 8, 4, 2, and 1 that can be assigned to the four bits in the BCD code.

A BCD adder that adds two BCD digits and produces a sum digit in BCD is shown in Fig. The two
decimal digits, together with the input carry, are first added in the top four-bit adder to produce the
binary sum.

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When the output carry is equal to 0, nothing is added to the binary sum. When it is equal to 1, binary
0110 is added to the binary sum through the bottom four-bit adder.
The condition for a correction and an output carry can be expressed by the Boolean function
C = K + Z8Z4 + Z8Z2
The output carry generated from the bottom adder can be ignored, since it supplies information already
available at the output carry terminal.
A decimal parallel adder that adds n decimal digits needs n BCD adder stages. The output carry from
one stage must be connected to the input carry of the next higher order stage.

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Binary Multiplier:
Explain about binary Multiplier.
Multiplication of binary numbers is performed in the same way as multiplication of decimal numbers.
The multiplicand is multiplied by each bit of the multiplier, starting from the least significant bit. Each
such multiplication forms a partial product.
Successive partial products are shifted one position to the left. The final product is obtained from the
sum of the partial products.

A combinational circuit binary multiplier with more bits can be constructed in a similar fashion.
A bit of the multiplier is ANDed with each bit of the multiplicand in as many levels as there are bits in
the multiplier.
The binary output in each level of AND gates is added with the partial product of the previous level to
form a new partial product. The last level produces the product.

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 *************************************

CODE CONVERSION
Design a binary to gray converter. (Nov-2009)(Nov
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2017)
Binary to Grayconverter

Gray code is unit distance code.

Input code: Binary [B3 B2 B1 B0]
output code: Gray [G3 G2 G1 G0]

Truth Table

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-MAP FORG3: K-MAP FORG2:

G3=B3 G2=B B2+B3B2 =B3 B2

K-MAP FORG1: K-MAP FORG0:

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G1=B B2+B1B2 =B1 B2 G0=B1 B0+B1B0 =B1 B0

Logic diagram:

Gray to Binary converter:

Design a gray to binary converter.(OR) Design a combinational circuit that converts a four bit gray
code to a four bit binary number using exclusive OR gates. (Nov-2009) [NOV 2019]
Gray code is unit distance code.
Input code: Gray [G3 G2 G1 G0]
output code: Binary [B3 B2 B1 B0]

Truth Table:

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K-Map:

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Logic Diagram:

BCD to Excess -3 converter:

Design a combinational circuits to convert binary coded decimal number into an excess-3 code.

Excess-3 code is modified form of BCD code. (Nov-06,09,10, May-08,10)

Excess -3 code is derived from BCD code by adding 3to each coded number.

Truth table:

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K-Map:

Logic Diagram

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Excess -3 to BCD converter:
Design a combinational circuit to convert Excess-3 to BCD code. (May 2007)

Truth table:

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Page 27
Design Binary to BCD converter.
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Truth table:

K-map:

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Logic diagram:

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DECODERS AND ENCODERS

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 Decoder:
Explain about decoders with necessary diagrams. (Apr 2018)(Nov 2018)

A decoder is a combinational circuit that converts binary information from n input lines to a maximum
of 2n unique output lines. If the n -bit coded information has unused combinations, the decoder may
have fewer than 2n outputs.
The purpose of a decoder is to generate the 2 n (or fewer) minterms of n input variables, shown below for
two input variables.

2 to 4 decoder:

3 to 8 Decoder:
Design 3 to 8 line decoder with necessary diagram. May -10)
Truth table:

Logic diagram:

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Design for 3 to 8 decoder with 2 to 4 decoder:

Not that the two to four decoder design shown earlier, with its enable inputs can be used to build a three
to eight decoder as follows.

Implementation of Boolean function using decoder:

Since the three to eight decoder provides all the minterms of three variables, the realisation of a
function in terms of the sum of products can be achieved using a decoder and OR gates as follows.
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Example: Implement full adder using decoder.

Sum m(1, 2, 4, 7) while Carry is given by m(3, 5, 6, 7) as given by the minterms

each of the OR gates are connected to.

Design for 4 to 16 decoder using 3 to 8 decoder: Design 5 to 32 decoder using 3 to 8 and 2 to 4 decoder:

**********************************

BCD to seven segment decoder

Design a BCD to seven segment code converter. (May-06,10, Nov- 09)

Truth table:

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K-Map:

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Logic Diagram:

The specification above requires that the output be zeroes (none of the segments are lighted up) when
the input is not a BCD digit.
In practical implementations, this may defer to allow representation of hexadecimal digits using the
seven segments.
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 Encoder:
Explain about encoders. (Nov 2018)
An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2 n (or
fewer) input lines and n output lines. The output lines, as an aggregate, generate the binary code
corresponding to the input value.

Octal to Binary Encoder:

The encoder can be implemented with OR gates whose inputs are determined directly from the truth
table. Output z is equal to 1 when the input octal digit is 1, 3, 5, or 7.
Output y is 1 for octal digits 2, 3, 6, or 7, and output x is 1 for digits 4, 5, 6, or 7. These conditions can
be expressed by the following Boolean output functions:

The encoder can be implemented with three OR gates.

Truth table:

Another ambiguity in the octal-to-

inputs are 0; but this output is the same as when D0 is equal to 1. The discrepancy can be resolved by
providing one more output to indicate whether at least one input is equal to 1.

Logic Diagram:

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 ************************

Priority Encoder:
Design a priority encoder with logic diagram.(or) Explain the logic diagram of a 4 input priority
encoder. (Apr 2019)
A priority encoder is an encoder circuit that includes the priority function. The operationof the
priority encoder is such that if two or more inputs are equal to 1 at the same time,the input having the
highest priority will take precedence.
Truth table:

Modified Truth table:

K-Map:

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Logic Equations:

Logic diagram:

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MULTIPLEXERS AND DEMULTIPLEXERS

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Multiplexer: (MUX)
Design a 2:1 and 4:1 multiplexer.

A multiplexer is a combinational circuit that selects binary information from one of many input lines and
directs it to a single output line. The selection of a particular input line is controlled by a set of selection
lines.
Normally, there are 2n input lines and n selection lines whose bit combinations determine which input is
selected.

2 to 1 MUX:

A 2 to 1 line multiplexer is shown in figure below, each 2 input lines A to B is applied to one input of an
AND gate. Selection lines S are decoded to select a particular AND gate. The truth table for the 2:1 mux
is given in the table below.

To derive the gate level implementation of 2:1 mux we need to have truth table as shown in figure. And
once we have the truth table, we can draw the K-map as shown in figure for all the cases when Y is
equal to '1'.
Truth table:

Logic Diagram:

4 to 1 MUX:
A 4 to 1 line multiplexer is shown in figure below, each of 4 input lines I0 to I3 is applied to one input
of an AND gate.

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Selection lines S0 and S1 are decoded to select a particular AND gate.
The truth table for the 4:1 mux is given in the table below.

Logic Diagram:

Truth Table:
SELECT OUTPUT
INPUT
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Problems :
Example: Implement the Boolean expression using MUX
(Apr 2017, Nov 2017)

Example: Implement the boolean function using Multiplexer. [NOV 2019]

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 Solution:
Implementation table:

Multiplexer Implementation:

Example: 32:1 Multiplexer using 8:1 Mux (Nov 2018) (Apr 2019)

DEMULTIPLEXERS:
Explain about demultiplexers.

The de-multiplexer performs the inverse function of a multiplexer, that is it receives information on one
line and transmits its onto one of 2n possible output lines.

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 The selection is by n input select lines. Example: 1-to-4 De-multiplexer

Logic Diagram: Truth Table:

INPUT OUTPUT

E D S0 S1 Y0 Y1 Y2 Y3

1 1 0 0 1 0 0 0

1 1 0 1 0 1 0 0

1 1 1 0 0 0 1 0

1 1 1 1 0 0 0 1

Example:
1. Implement full adder using De-multiplexer.

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2. Implement the following functions using de-multiplexer.

Solution:

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Parity Checker / Generator:

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 A parity bit is an extra bit inc
even. The message, including the parity bit, is transmitted and then checked at the receiving end for
errors. An error is detected if the checked parity does not correspond with the one transmitted.
The circuit that generates the parity bit in the transmitter is called a parity generator. The circuit that
checks the parity in the receiver is called a parity checker.
s in the data and the parity bit

3-bit Even Parity generator:

Truth Table:

Logic Diagram:

4-bit Even parity checker:

Truth Table:

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Logic Diagram:

INTRODUCTION TO HDL

In electronics, a hardware description language or HDL is any language from a class of computer
languages and/or programming languages for formal description of digital logic and electronic circuits.
HDLs are used to write executable specifications of some piece of hardware.
A simulation program, designed to implement the underlying semantics of the language statements,
coupled with simulating the progress of time, provides the hardware designer with the ability to model a
piece of hardware before it is created physically.
Logic synthesis is the process of deriving a list of components and their interconnection (called net list)
from the model of a digital system.
Logic Simulation is the representation of the structure and behavior of a digital logic synthesis through
the use of a computer.
The standard HDLs that supported by IEEE.
VHDL (very High Speed Integrated Circuit HDL)
Verilog HDL

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 HDL MODELS OF COMBINATIONAL CIRCUITS

The Verilog HDL model of a combinational circuit can be described in any one of the following
modeling styles,

Gate level modeling-using instantiations of predefined and user defined primitive gates.
Dataflow modeling using continuous assignment with the keyword assign.
Behavioral modeling using procedural assignment statements with the keyword always.

Gate level modeling

In this type, a circuit is specified by its logic gates and their interconnections. Gate level modeling
provides a textual description of a schematic diagram. The verilog HDL includes 12basic gates as
predefined primitives. They are and, nand, or, nor, xor, xnor, not &buf.

Data flow modeling

Data flow modeling of combinational logic uses a number of operators that act on operands to produce
desired results. Verilog HDL provides about 30 different operators. Data flow modeling uses continuous
assignments and the keyword assign. A continuous assignment is a statement that assigns a value to a
net. The data type family net is used to represent a physical connection between circuit elements.

HDL for2-to-4 line decoder

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Behavioral modeling

Behavioral modeling represents digital circuits at a functional and algorithmic level. It is used mostly to
describe sequential circuits, but can also be used to describe combinational circuits.
Behavioral descriptions use the keyword always, followed by an optional event control expression and a
list of procedural assignment statements.

UNIT II
COMBINATIONAL LOGIC
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 TWO MARK QUESTIONS & ANSWERS

1) Define combinational logic. (May 2008, 2016)

A combinational circuit consists of logic gates whose outputs at any time are determined from
only the
present combination of inputs. A combinational circuit performs an operation that canbe specified
logically by a set of Boolean functions.

2) What are sequential circuits?

Sequential circuits employ storage elements in addition to logic gates. Their outputs are a function
of the inputs and the state of the storage elements. Because the state of the storage elements is a function
of previous inputs, the outputs of a sequential circuit depend not only on present values of inputs, but also
on past inputs, and the circuit behavior must be specified by a time sequence of inputs and internal states.

3) Write the design procedure for combinational circuits?

The procedure involves the following steps:
1. From the specifications of the circuit, determine the required number of inputs and outputs and assign
a symbol to each.
2. Derive the truth table that defines the required relationship between inputs and outputs.
3. Obtain the simplified Boolean functions for each output as a function of the input variables.
4. Draw the logic diagram and verify the correctness of the design (manually or by simulation).

4) What is Half adder?

A half-adder is an arithmetic circuit block that can be used to add two bits and produce two
outputs SUM and CARRY.
The Boolean expressions for the SUM and CARRY outputs are given by the equations

Truth Table:

5) Draw the logic diagram of half adder using NAND gate. (May 2006,13)

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Logic Diagram: Half adder using NAND gate:

6) What is Full adder? Draw the truth table of full adder. (Apr 2018)
A Full-adder is an arithmetic circuit block that can be used to add three bits and produce two
outputs SUM and CARRY.
The Boolean expressions for the SUM and CARRY outputs are given by the equations

7) Draw the Logic diagram of full adder.

8) What is Half subtractor? (May 2005)

A half-subtractor is a combinational circuit that can be used to subtract one binary digit from
another to produce a DIFFERENCE output and a BORROW output. The BORROW output here specifies
The Boolean expression for difference and
borrow is:

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 Logic diagram:

9) Draw Full adder using Two half adder. (Apr 2019)

10) What is Full subtractor? Write the truth table of full subtractor. (Nov 2017)
A full subtractor performs subtraction operation on two bits, a minuend and a subtrahend, and
also takes
minuend bit or not. As a result, there are three bits to be handled at the input of a full subtractor, namely
the two bits to be subtracted and a borrow bit designated as Bin . There are two outputs, namely the
DIFFERENCE output D and the BORROW output Bo. The BORROW output bit tells whether the
minuend bit needs The Boolean expression for
difference and barrow is:

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 11) Draw Full subtractor using two half subtractor.

12) What is Parallel Binary Adder (Ripple Carry Adder)?

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers.It can
beconstructed with full adders connected in cascade, with the output carryfrom each full adder connected
to the input carry of the next full adder in the chain.
13) Draw the logic diagram for four bit binary parallel adder.

14)
The 1 s complement of a binary number is formed bychanging 1 to 0 and 0 to 1.
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 Example:
1.
2. 1010010.
15)

number.
Example:
1) T
2) T

16) How Subtracti

The subtraction of unsigned binary number can be done by means of complements.
Subtraction of A-
Check the resulting number. If carry present, the number is positive and remove the carry.

negative sign.

17) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction
(a) X - Y and (b) Y -
Solution:
(c) X = 1010100
2 s complement of Y = + 0111101
Sum= 10010001
Discard end carry. Answer: X - Y = 0010001

(d) Y = 1000011
2 s complement of X= + 0101100
Sum= 1101111
There is no end carry. Therefore, the answer is Y - X = -(2 s complement of 1101111) =-0010001.

18) Draw the logic diagram of Parallel Binary Subtractor.

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 19) Draw 1:8 Demux using two 1:4 demux. (Nov 2018)

20)

The mode input M controls the operation. When M = 0, the circuit is an adder, and when M = 1,
the circuit becomes a subtractor.

21) What is Magnitude Comparator? [NOV 2019]

The comparison of two numbers is an operation that determines whether one number is
greater than, less than, or equal to the other number. A magnitude comparator is a combinational
circuit that compares two numbers A and B and determines their relative magnitudes.

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 The outcome of the comparison is specified by three binary variables that indicate whether A
> B, A = B, or A < B.

22) Design a 1-bit Magnitude Comparator.

Truth table:

Logic Circuits:

23) What is Decoder? What are binary decoders? (Nov 2017)

A decoder is a combinational circuit that converts binary information from n input lines to a
maximum of 2n unique output lines. If the n -bit coded information hasunused combinations, the
decoder may have fewer than 2 n outputs.

The purpose of a decoder is to generate the 2 n (or fewer) minterms of n input variables, shown below
for two input variables.

24) Design a 3 to 8 decoder with 2 to 4 decoder.

Not that the two to four decoder design shown earlier, with its enable inputs can be used to build a
three to eight decoder as follows.

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 25) What is Encoder? (May 2012)
An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder
has 2n (or fewer) input lines and n output lines. The output lines, as an aggregate, generate the binary
code corresponding to the input value.
26) What is Priority Encoder? (Apr 2017)
A priority encoder is an encoder circuit that includes the priority function. The operation of
the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having
the highest priority will take precedence.

27) Define Multiplexer (MUX) (or) Data Selector. (Dec 2006, May 2011) [NOV 2019]
A multiplexer is a combinational circuit that selects binary information from one of many
input lines and directs it to a single output line. The selection of a particular input line is controlled by
a set of selection lines. Normally, there are 2 n input lines and n selection lines whose bit combinations
determine which input is selected.

28) What is De-multiplexer?

The de-multiplexer performs the inverse function of a multiplexer, that is it receives information on
one line and transmits its onto one of 2n possible output lines. The selection is by n input select
lines.
29) What is Parity?
A parity bit is an extra
odd or even. The message, including the parity bit, is transmitted and then checked at the receiving

Page 55
 end for errors. An error is detected if the checked parity does not correspond with the one
transmitted.
30) What is Parity Checker / Generator:
The circuit that generates the parity bit in the transmitter is called a parity generator. The
circuit that checks the parity in the receiver is called a parity checker.
31) What is even parity and odd parity?

parity b

31) Give the applications of Demultiplexer.

i) It finds its application in Data transmission system with error detection.
ii) One simple application is binary to Decimal decoder.

32) Mention the uses of Demultiplexer.

Demultiplexer is used in computers when a same message has to be sent to different receivers. Not only
in computers, but any time information from one source can be fed to several places.

33) Give other name for Multiplexer and Demultiplexer.

Multiplexer is otherwise called as Data selector.
Demultiplexer is otherwise called as Data distributor.
34) What is the function of the enable input in a Multiplexer?
The function of the enable input in a MUX is to control the operation of the unit.
35) List out the applications of decoder? (Dec 2006)
a. Decoders are used in counter system.
b. They are used in analog to digital converter.
c. Decoder outputs can be used to drive a display system.

36) What is the Application of Mux?

1. They are used as a data selector to select one output of many data inputs.
2. They can be used to implement combinational logic circuits
3. They are used in time multiplexing systems.
4. They are used in frequency multiplexing systems.
5. They are used in A/D & D/A Converter.
6. They are used in data acquisition system.

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37) List out the applications of comparators?
a. Comparators are used as a part of the address decoding circuitry in computers to select a
specific input/output device for the storage of data.
b. They are used to actuate circuitry to drive the physical variable towards the
reference value.
c. They are used in control applications.
38) What is carry look-ahead addition?
The speed with which an addition is performed limited by the time required forthe carries to
propagate or ripple through all of the stage of the adder. One method ofspeeding up the process is by
eliminating the ripple carry delay.

39) What is the Difference between Decoder & Demux.?

S.No Decoder Demux
1 Decoder is a many inputs to many Demux is a single input to many outputs
Outputs
2 There are no selection lines. The selection of specific output line is
controlled by the value of selection lines.

40) How Binary to Gray Code Conversion done?

Consider b1, b2, b3, b4 and b5 is the Binary Number and it is need be converted into Grey Code.
1. Write Most Significant Bit (MSB) is same as the MSB in Binary Number.

2. The second bit of the Grey code can be found by performing the Exclusive-OR (EX-OR)
operation between the First and second bits of the Binary Number.

3. The Third bit of the Grey code can be found by performing the Exclusive-OR (EX-OR) operation
between the Third and Second bits of the given Binary Number; and so on

EX-OR Operation:
1. Both the bits are 0 or 1 then the output of EX-OR gate will be 0.
2. Any one of the bit in two bits is 1 then the output of EX-OR gate will be 1.

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41) How Gray Code to Binary Conversion done?
Consider g0, g1, g2 and g3 is the Gray Code and it is need be converted into Binary Number. The
steps for Binary to Gray Code Conversion needs to be reversed to find out the equivalent Binary
Number

1. The Most Significant Bit (MSB) of the Binary is same as the First MSB of the Gray Code.

2. If the second Gray Bit is 0 then the second bit of the Binary is bit will be same as that of the First
Binary bit; if the Second Gray Bit is 1 then the Second Bit of the Binary will be inverse of its
previous binary bit. Refer the below image for easy understanding of Gray to Binary Conversion

32) Draw the circuit for 4 to 1 line multiplexer. (Apr 2017) [NOV 2019]
Logic Diagram:

Page 58
Truth Table:
SELECT OUTPUT
INPUT
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

42) What do you meant by HDL?

Hardware description language (HDL)- hardware description language or HDL is any
language from a class of computer languages and/or programming languages for formal
description of digital logic and electronic circuits.

43) List the Verilog HDL model of a combinational circuits.

Gate level modeling-using instantiations of predefined and user defined primitive gates.
Dataflow modeling using continuous assignment with the keyword assign.
Behavioral modeling using procedural assignment statements with the keyword always.

44) What is meant by Gate level modeling?

In this type, a circuit is specified by its logic gates and their interconnections. Gate level
modeling provides a textual description of a schematic diagram.

45) What is meant by data flow modeling?

Data flow modeling of combinational logic uses a number of operators that act on
operands to produce desired results. Verilog HDL provides about 30 different operators.

46) What is meant by Behavioral modeling?

Behavioral modeling represents digital circuits at a functional and algorithmic level. It is
used mostly to describe sequential circuits, but can also be used to describe combinational
circuits.

47) What is Verilog?

Verilog is a general purpose hardware descriptor language. It has similar in syntax to the C
programming language. It can be used to model a digital system at many levels of abstraction
ranging from the algorithmic level to the switch level.

48) Define logic synthesis and simulation.

Logic synthesis is the process of deriving a list of components and their interconnection (called
netlist) from the model of a digital system.

Logic Simulation is the representation of the structure and behavior of a digital logic synthesis
through the use of a computer.

49) List the standard HDLs that supported by IEEE.

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 VHDL (very High Speed Integrated Circuit HDL)
Verilog HDL
50) Write the truth table of 2 to 4 line decoder and draw its logic diagram. (Apr 2019)

2 to 4 decoder:

51) State the different modeling techniques used in HDL. (Apr 2018)
Gate level modeling
Data flow modeling
Behavioral modeling

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 UNIT III
SYNCHRONOUS SEQUENTIAL LOGIC

Sequential Circuits - Storage Elements: Latches , Flip-Flops - Analysis of Clocked Sequential Circuits - State
Reduction and Assignment - Design Procedure - Registers and Counters - HDL Models of Sequential
Circuits

SEQUENTIAL CIRCUITS
Sequential circuits:
Sequential circuits employ storage elements in addition to logic gates. Their outputs are a function of
the inputs and the state of the storage elements.
Because the state of the storage elements is a function of previous inputs, the outputs of a sequential
circuit depend not only on present values of inputs, but also on past inputs, and the circuit behavior
must be specified by a time sequence of inputs and internal states.

Types of sequential circuits:

There are two main types of sequential circuits, and their classification is a function ofthe timing
of their signals.
1. Synchronous sequential circuit:
It is a system whose behaviorcan be defined from the knowledge of its signals at discrete
instants of time.
2. Asynchronous sequential circuits:
The behaviorof an asynchronous sequential circuit depends upon the input signals at any
instant of timeand the order in which the inputs change. The storage elements commonly used
in asynchronoussequential circuits are time-delay devices.

LATCHES AND FLIP FLOPS

Flip-Flop:
The storage elements (memory) used in clocked sequential circuits are called flipflops. A flip-flop is
a binary storage device capable of storing one bit of information. In a stable state, the output of a flip-
flop is either 0 or 1.
A sequential circuit may use many flip-flops to store as many bits as necessary. The block diagram of
a synchronous clocked sequential circuit is shown in Fig.

Page 1
 A storage element in a digital circuit can maintain a binary state indefinitely (as long as power is
delivered to the circuit), until directed by an input signal to switch states.
The major differences among various types of storage elements are in the number of inputs they
possess and in the manner in which the inputs affect the binary state.
Latch:
The storage elements that operate with signal levels (rather than signal transitions) are referred to as
latches; those controlled by a clock transition are flip-flops.Latches are said to be level sensitive
devices; flip-flops are edge-sensitive devices.

SR Latch: Using NOR gate

Realize SR Latch using NOR and NAND gates and explain its operation.
The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates, and
two inputs labeled S for set and R for reset.
The SR latch constructed with two cross-coupled NOR gates is shown in Fig.

The latch has two useful states. When output Q = 1 and Q set state .
When Q = 0 and Q reset state . Outputs Q and Q
each other.
However, when both inputs are equal to 1 at the same time, a condition in which both outputs are
equal to 0 (rather than be mutually complementary) occurs.
If both inputs are then switched to 0 simultaneously, the device will enter an unpredictable or
undefined state or a metastable state. Consequently, in practical applications, setting both inputs to 1
is forbidden.

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 FLIP FLOPS
Triggering of Flip Flops:
Explain about triggering of flip flops in detail.
The state of a latch or flip-flop is switched by a change in the control input. This momentary change
is called a trigger, and the transition it causes is said to trigger the flip-flop.

Level Triggering:
SR, D, JK and T latches are having enable input.
Latches are controlled by enable signal, and they are level triggered, either positive level triggered or
negative level triggered as shown in figure (a).
The output is free to change according to the input values, when active level is maintained at the
enable input.

Edge Triggering:
A clock pulse goes through two transitions: from 0 to 1 and the return from 1 to 0.
As shown in above Fig (b) and (c)., the positive transition is defined as the positive edge and the
negative transition as the negative edge.

*******************************
Explain the operation of flipflops.(Nov 2017)

FLIP FLOP CONVERSIONS

The purpose is to convert a given type A FF to a desired type B FF using some conversion logic.

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The key here is to use the excitation table, which shows the necessary triggering signal (S,R, J,K, D and

T) for a desired flipflop state transition :

Excitation table for all flip flops:

1. SR Flip Flop to JK Flip Flop

The truth tables for the flip flop conversion are given below. The present state is represented by
Qp and Qp+1 is the next state to be obtained when the J and K inputs are applied.
For two inputs J and K, there will be eight possible combinations. For each combination of J, K and Qp,
the corresponding Qp+1 states are found. Qp+1 simply suggests the future values to be obtained by the
JK flip flop after the value of Qp.

The table is then completed by writing the values of S and R required to get each Qp+1 from the
corresponding Qp. That is, the values of S and R that are required to change the state of the flip flop from
Qp to Qp+1 are written.

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2.JK Flip Flop to SR Flip Flop
This will be the reverse process of the above explained conversion. S and R will be the external
inputs to J and K. As shown in the logic diagram below, J and K will be the outputs of the combinational
circuit. Thus, the values of J and K have to be obtained in terms of S, R and Qp. The logic diagram is
shown below.

A conversion table is to be written using S, R, Qp, Qp+1, J and K. For two inputs, S and R, eight
combinations are made. For each combination, the corresponding Qp+1 outputs are found. The outputs
for the combinations of S=1 and R=1 are not permitted for an SR flip flop. Thus the outputs are

Page 5
3.SR Flip Flop to D Flip Flop
As shown in the figure, S and R are the actual inputs of the flip flop and D is the external input of
the flip flop. The four combinations, the logic diagram, conversion table, and the K-map for S and R in
terms of D and Qp are shown below.

4.D Flip Flop to SR Flip Flop

D is the actual input of the flip flop and S and R are the external inputs. Eight possible
combinations are achieved from the external inputs S, R and Qp. But, since the combination of S=1 and
logic diagram showing
the conversion from D to SR, and the K-map for D in terms of S, R and Qp are shown below.

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5.JK Flip Flop to T Flip Flop
J and K are the actual inputs of the flip flop and T is taken as the external input for conversion.
Four combinations are produced with T and Qp. J and K are expressed in terms of T and Qp. The
conversion table, K-maps, and the logic diagram are given below.

6.JK Flip Flop to D Flip Flop

D is the external input and J and K are the actual inputs of the flip flop. D and Qp make four
combinations. J and K are expressed in terms of D and Qp. The four combination conversion table, the
K-maps for J and K in terms of D and Qp, and the logic diagram showing the conversion from JK to
D are given below.

7.D Flip Flop to JK Flip Flop

AUQ: How will you convert a D flip-flop into JK flip-flop? (AUQ: Dec 2009,11,Apr 2017)
In this conversion, D is the actual input to the flip flop and J and K are the external inputs. J, K
and Qp make eight possible combinations, as shown in the conversion table below. D is expressed in
terms of J, K and Qp.The conversion table, the K-map for D in terms of J, K and Qp and the logic
diagram showing the conversion from D to JK are given in the figure below.

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 *******************************************
MEALY AND MOORE MODELS

Write short notes on Mealy and Moore models in sequential circuits.

In synchronous sequential circuit the outputs depend upon the order in which its input variables
change and can be affected at discrete instances of time.
General Models:
There are two models in sequential circuits. They are:
1. Mealy model
2. Moore model

Moore machine:
In the Moore model, the outputs are a function of present state only.

Mealy machine:
In the Mealy model, the outputs are a function of present state and external inputs.

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Difference between Moore model and Mealy model.

Example:
-Flops A and B, one input (x) and one output (y).
The Flip-Flop input functions are:
DA= Ax+ Bx
DB and
the circuit output function is, .
(a) Draw the logic diagram of the circuit, (b) Tabulate the state table, (c) Draw the state diagram.

Solution:

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State table:

State diagram:

***************************************

TWO MARKS
1. Difference between Combinational & Sequential Circuits.
S .no Combinational Circuits Sequential Circuits
1 The output at all times depends only on The output not only depends on the present
the present combination of input input but also depends on the past history input
variables. variables.
2 Memory unit is not Required Memory unit is required to store the past
history of input variable
3 Clock input is not needed. Clock input is needed.

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4 Faster in Speed Speed is Slower
5 Easy to design. Difficult to design. Eg: Shift Register,
Eg:Mux, Demux, Encoder, Decoder, Counters.
Adders, Subtractors.

2. What are the classifications of sequential circuits?

The sequential circuits are classified on the basis of timing of their signals in to two types. They are
1) Synchronous sequential circuit.2) Asynchronous sequential circuit.
3. Define Latch.
The basic unit for storage is Latch. A Latch maintain its output state either at 1or 0 until directed by
an input signal to change its state.
4. Define a flip flop.
A flip-flop is a storage device capable of storing one bit of information. It has two states either 0 or 1.
It is also called bistable multivibrator.
5. What are the different types of flip-flop?
The various types of flip flops are 1). SR flip-flop 2). D flip-flop 3). JK flip-flop 4). T flip-flop
6. What is the main difference between a latch and flip flop?
The output of latch changes immediately when its input changes.
The output of a flip-flop changes only when its clock pulse is active and its input changes.
Input changes do not affect output if its clock is not activated.
7. State few application of Flip-Flop.
Used as a memory element.
Used as delay elements.
Data transfer
Used as a building block in sequential circuits such as counters and registers.
8. What is the operation of D flip-flop?
In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output
is reset. Set 1, Reset 0.
9. What is the operation of JK flip-flop?
When K input is low and J input is high the Q output of flip-flop is set.
When K input is high and J input is low the Q output of flip-flop is reset.
When both the inputs K and J are low the output does not change
When both the inputs K and J are high it is possible to set or reset the flip-flop(ie) the output toggle
onthe next positive clock edge.
10. What is the operation of T flip-flop? (Nov 2018)

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 T flip-flop is also known as Toggle flip-flop. 1). When T=0 there is no change in the output. 2). When
T=1 the output switch to the complement state (ie) the output toggles.
11. Define race around condition.
In JK flip-flop output is fed back to the input. Therefore change in the output results change in
the input. Due to this in the positive half of the clock pulse if both J and K are high then output
toggles continuously
12. What is triggering? What is the need for trigger in flip-flop?
A flip-flop is made to change its state by application of a clock pulse after giving inputs. This is
called triggering. The clock (triggering input) is given to synchronize the change in the output with it.
13. What is meant by level and edge-triggering? (Nov 2017) (Apr 2019)
If flip-flop changes its state when the clock is positive (high) or negative (low) then, that flip-
flop is said to be level triggering flip-flop.
If the flip-flop changes its state at the positive edge (rising edge) or negative edge (falling
edge) of the clock is sensitive to its inputs only at this transition of the clock then flip-flop is
said to be edge triggered flip-flop.
14. How do you eliminate race around condition in JK flip flop. ?
Using master-slave flip-flop which consists of two flip-flops where one circuit serves as a master and
the other as a slave race around condition in JK flip flop is eliminated .
15. Define rise time.
The time required to change the voltage level from 10% to 90% is known as rise time (tr).
16. Define fall time.
The time required to change the voltage level from 90% to 10% is known as falltime (tf).
17. Define skew and clock skew.
The phase shift between the rectangular clock waveforms is referred to as skew and the time
delay between the two clock pulses is called clock skew.
18. Define setup time.
The setup time is the minimum time required to maintain a constant voltage levels at the excitation inputs of the
flip-flop device prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into
the flip flop.
19. Draw the logic diagram and write the function table of D Latch. (Apr 2019)

Page 12
20. Define hold time.
The hold time is the minimum time for which the voltage levels at the excitation inputs must remain
constant after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop.
21. Define propagation delay.
A propagation delay is the time required to change the output after the application of the input
22. Explain the flip-flop excitation tables for RS FF.
In RS flip-flop there are four possible transitions from the present state to theNext state. They are
sition: This can happen either when R=S=0 or when R=1 and S=0.

.
23. Give some applications of clocked RS Flip-flop.
Clocked RS flip flops are used in Calculators & Computers.
It is widely used in modern electronic products.
24. What is the drawback of SR Flipflop? How is this minimized? (Apr 2018)
In SR flipflop when both S and R inputs are one it will generate a Undetermined state.This is
Minimized by providing feedback path or by using JK flip flop.
25. How many flip flops are required to build a Binary counter that counts from 0 to 1023?
210= 1024 hence 10 flipflops are required.
26. State the difference between latches and flipflops. (Apr 2019)

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27. What is mealy and Moore circuit? Or what are the models used to represent clocked sequential
circuits?
Mealy circuit is a network where the output is a function of both present state and input.
Moore circuit is a network where the output is function of only present state

*****************************************
COUNTERS
Counter:
A counter is a register (group of Flip-Flop) capable of counting the number of clock pulse
arriving at its clock input.
A counter that follows the binary number sequence is called a binary counter.
Counter are classified into two types,
1. Asynchronous (Ripple) counters.
2. Synchronous counters.
In ripple counter, a flip- flop output transition serves as clock to next flip-flop.

Page 14
 o With an asynchronous circuit, all the bits in the count do not all change at the same time.
In a synchronous counter, all flip-flops receive common clock.
o With a synchronous circuit, all the bits in the count change synchronously with the
assertion of the clock
A counter may count up or count down or count up and down depending on the input control.

Uses of Counters:
The most typical uses of counters are
To count the number of times that a certain event takes place; the occurrence of event to be
counted is represented by the input signal to the counter
To control a fixed sequence of actions in a digital system
To generate timing signals
To generate clocks of different frequencies

Modulo 16 ripple /Asynchronous Up Counter

Explain the operation of a 4-bit binary ripple counter.
The output of up-counter is incremented by one for each clock transition.
A 4-bit asynchronous up-counter consists of 4JK Flip-Flops.
The external clock signal is connected to the clock input of the first FlipFlop.
The clock inputs of the remaining Flip-Flops are triggered by the Q output of the previous stage.
We know that in JK Flip-Flop, if J=1 , K=1 and clock is triggered the past output will be
complemented.
Initially, the register is cleared, QDQCQBQA =0000.
During the first clock pulse, Flip-Flop A triggers, therefore QA=1, QB=QC=QD=0.
QDQCQBQA=0001
At the second clock pulse FLipFlop A triggers, therefore QA changes from 1 to 0, which triggers
FlipFlop B, therefore QB=1,QA=QC=QD=0
QDQCQBQA=0010
At the third clock pulse FlipFlop A triggers, therefore QA changes from 0 to 1, This never triggers
FlipFlop B because 0 to 1 transition gives a positive edge triggering,but here the FlipFlops are
triggered only at negative edge( 1 to 0 transition) therefore QA=QB=1, QC=QD=0.
QDQCQBQA=0011
At the fourth clock pulse Flip-Flop A triggers, therefore QA changes from 1 to 0, This triggers
FlipFlop B therefore QB changes from 1 to 0. The change in QB from 1 to 0 triggers C Flip-Flop,

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 Therefore QC changes from 0 to 1. Therefore QA=QB=QD=0, QC=1.
QDQCQBQA=0100

Truth table:

Page 16
Timing diagram:

**********************************
Modulo 16 /4 bit Ripple Down counter/ Asynchronous Down counter
Explain about Modulo 16 /4 bit Ripple Down counter.
The output of down-counter is decremented by one for each clock transition.
A 4-bit asynchronous down-counter consists of 4JK Flip-Flops.
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The external clock signal is connected to the clock input of the first Flip-Flop.
The clock inputs of the remaining Flip-Flops are triggered by the Q output of the previous stage.
We know that in JK Flip-Flop, if J=1 , K=1 and clock is triggered the past output will be
complemented.

Initially, the register is cleared, QDQCQBQA =0000.

During the first clock pulse, Flip-Flop A triggers, therefore QA changes from 0 to 1 also QA
changes from 1 to 0.This triggers Flip-Flop B, therefore QB changes from 0 to 1, also QB changes
from 1 to 0which triggers Flip-FlopC. Hence QC changes from 0 to 1 and QC changes from 1 to
0, which further triggers, Flip-Flop D.
QDQCQBQA=1111
QD QC QB QA=0000
During the second clock pulse Flip-Flop A triggers, therefore QA changes from 1 to 0 also QA
changes from 0 to 1 which never triggers B Flip-Flop. Therefore C and D Flip-Flop are not
triggered.
QDQCQBQA =1110
The same procedure repeats until the counter decrements upto 0000.

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***************************

Page 19
Asynchronous Up/Down Counter:
Explain about Asynchronous Up/Down counter.
The up-down counter has the capability of counting upwards as well as downwards. It is also
called multimode counter.
In asynchronous up-counter, each flip-flop is triggered by the normal output Q of the preceding
flip-flop.
In asynchronous down counter, each flip-flop is triggered by the complement output Q of the
preceding flip-flop.
In both the counters, the first flip-flop is triggered by the clock output.

If Up/Down =1, the 3-bit asynchronous up/down counter will perform up-counting. It will count
from 000 to 111. If Up/Down =1 gates G2 and G4 are disabled and gates G1 and G3 are enabled.
So that the circuit behaves as an up-counter circuit.
If Up/Down =0, the 3-bit asynchronous up/down counter will perform down-counting. It will
count from 111 to 000. If Up/Down =0 gates G2 and G4 are enabled and gates G1 and G3 are
disabled. So that the circuit behaves as an down-counter circuit.

******************************

Page 20
4- bitSynchronous up-counter:
Explain about 4-bit Synchronous up-counter.

In JK Flip-Flop, If J=0, K=0 and clock is triggered, the output never changes. If J=1 and K=1 and
the clock is triggered, the past outpit will be complemented.
Initially the register is cleared QDQCQBQA= 0000.
During the first clock pulse, JA= KA = 1, QA becomes 1, QB, QC, QD remains 0.
QDQCQBQA= 0001.
During second clock pulse, JA= KA = 1, QA=0.
JB= KB = 1, QB =1, QC, QD remains 0.
QDQCQBQA= 0010.
During third clock pulse, JA= KA = 1, QA=1.
JB= KB = 0, QB =1, QC, QD remains 0.
QDQCQBQA= 0011.
During fourth clock pulse, JA= KA = 1, QA=0.
JB= KB = 1, QB =0
JC= KC = 1, QC=1
QD remains 0
QDQCQBQA= 0100.
The same procedure repeats until the counter counts up to 1111.

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*******************************************

Page 22
4- bit Synchronous down-counter:
Explain about 4-Bit Synchronous down counter.

In JK Flip-Flop, If J=0, K=0 and clock is triggered, the output never changes. If J=1 and K=1 and the
clock is triggered, the past outpit will be complemented.
Initially the register is cleared QDQCQBQA= 0000
QDQCQBQA= 1111

During the first clock pulse, JA= KA = 1, QA=1

JB= KB = 1, QB =1
JC= KC = 1, QC =1
JD= KD = 1, QD =1
QDQCQBQA= 1111
QDQCQBQA= 0000

During the second clock pulse, JA= KA = 1, QA =0

JB= KB = 0, QB =1
JC= KC = 0, QC =1
JD= KD = 0, QD =1
QDQCQBQA= 1110
QDQCQBQA= 0001

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During the second clock pulse, JA= KA = 1, QA =1
JB= KB = 1, QB =0
JC= KC = 0, QC =1
JD= KD = 0, QD =1
QDQCQBQA= 1101
The process repeats until the counter down-counts up to 0000.

************************************

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Modulo 8 Synchronous Up/Down Counter:
Explain about Modulo 8 Synchronous Up/Down Counter.

In synchronous up-counter the QA output is given to JB, KBand QA. QB is given to JC, KC. But in
synchronous down counter QAoutput is given toJB, KB and QA. QB is given to JC, KC.

A control input Up/Down is used to select the mode of operation.

If Up/Down =1, the 3-bit asynchronous up/down counter will perform up-counting. It will count from
000 to 111. If Up/Down =1 gates G2 and G4 are disabled and gates G1 and G3 are enabled. So that the
circuit behaves as an up-counter circuit.

If Up/Down =0, the 3-bit asynchronous up/down counter will perform down-counting. It will count from
111 to 000. If Up/Down =0 gates G2 and G4 are enabled and gates G1 and G3 are disabled. So that the
circuit behaves as an down-counter circuit.

*******************************************

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 TWO MARKS
1. What is counter?
A counter is a register (group of Flip-Flop) capable of counting the number of clock pulse
arriving at its clock input.
2. What is binary counter?
A counter that follows the binary number sequence is called a binary counter.
3. State the applications of counters.
1. Used as a memory Element.
2. Used as a Delay Element.
3. Used as a basic building block in sequential circuits such as counters and registers.
4. Used for Data Transfer, Frequency Division & Counting.
4. List the types of counters.
Counter are classified into two types,
Asynchronous (Ripple) counters.
Synchronous counters.
5. Give the comparison between synchronous & Asynchronous counters. (Nov/Dec 2009, Nov
2017)
S.No Asynchronous counters Synchronous counters
1. In this type of counter flip-flops are connected in In this type there is no connection between
such a way that output of 1st flip-flop drives output of first flip-flop and clock input of the next
the clock for the next flip - flop. flip flop
2 All the flip-flops are not clocked All the flip-flops are clocked simultaneously
simultaneously
3 Logic circuit is very simple even for Design involves complex logic circuit as
more number of states number of states increases
4 Counters speed is low. Counters speed is high.
6. State the Steps or Design procedure for Synchronous Counter.
Preparation of 1). State Diagram
2). State Table
3). State Assignment
4). Excitation Table (Consider which Memory Unit Using)
5). K-Map
6). Circuit Diagram
7. What is modulo-N counter?
A modulo ncounter will count n states. For example a mod-6 counter will count the sequence
000,001,010,011,100,101 and then recycles to 000. Mod -6 counter skips 110 and 111 states and it goes through only
six different states.
******************************************

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 DESIGN OF RIPPLE COUNTERS
3-Bit Asynchronous Binary Counter/ modulo -7 ripple counter:
Design a 3-bit binary counter using T-flip flops. [NOV 2019]
Explain about 3-Bit Asynchronous binary counter. (Nov -2009)
The following is a three-bit asynchronous binary counter and its timingdiagram for one cycle. It
works exactly the same way as a two-bitasynchronous binary counter mentioned above, except it has
eight statesdue to the third flip-flop.

Asynchronous counters are commonly referred to as ripple counters forthe following reason: The
effect of the input clock pulse is first
thepropagation delay through FF0. Then there is the propagation delaythrough FF1 before FF2 can be
ome time, due
topropagation delays, to reach the last flip-flop.

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 **********************************
ANALYSIS OF CLOCKED SEQUENTIAL CIRCUIT
Design and analyze of clocked sequential circuit with an example.
The analysis of a sequential circuit consists of obtaining a table or a diagram for the time sequence of
inputs, outputs and internal states.

Fig: Example of sequential circuit

Consider the sequential circuit is shown in figure. It consists of two D flip-flops A and B, an input x and
an output y.
A state equation specifies the next state as function of the present state and inputs.
A(n+1)= A(n)x(n)+B(n)x(n)
B(n +1)= A(n)x(n)
They can be written in simplified form as,
A(n+1) = Ax +Bx
B(n +1) = Ax
The present state value of the output can be expressed algebraically as,

y(n)=(A+B) x

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 DESIGN OF SYNCHRONOUS COUNTERS
Design and analyze of clocked sequential circuit with an example.
The procedure for designing synchronous sequential circuit is given below,
1. From the given specification, Draw the state diagram.
2. Plot the state table.
3. Reduce the number of states if possible.
4. Assign binary values to the states and plot the transition table by choosing the type of Flip-Flop.
5. Derive the Flip flop input equations and output equations by using K-map.
6. Draw the logic diagram.

State Diagram:
State diagram is the graphical representation of the information available in a state table.
In state diagram, a state is represented by a circle and the transitions between states are indicated by
directed lines connecting the circles.
State Table:
A state table gives the time sequence of inputs, outputs ad flip flops states. The table consists of
four sections labeled present state, next state, input and output.
The input
section gives a value of x for each possible present state.
The next state section shows the states of flip flops one clock cycle later, at time n+1.

The state table for the circuit is shown. This is derived using state equations.

The above state table can also be expressed in different forms as follows.

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The state diagram for the logic circuit in below figure.

Flip-Flop Input Equations:

The part of the circuit that generates the inputs to flip flops is described algebraically by a set of Boolean
functions called flip flop input equations.
The flip flop input equations for the circuit is given by,
DA =Ax +Bx
DB = Ax

**************************************

TWO MARKS
1. Define state diagram.
State diagram is the graphical representation of the information available in a state table.
In state diagram, a state is represented by a circle and the transitions between states are indicated
by directed lines connecting the circles.
2. What is the use of state diagram?
i) Behavior of a state machine can be analyzed rapidly.
ii) It can be used to design a machine from a set of specification.
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 3. What is state table? (Nov 2018)
A stable table is a table that represents relationship between inputs, outputs and flip-flop
states, is called state table. Generally it consists of four section present state, next state, input and
output.
4. What is a state equation?
A state equation also called, as an application equation is an algebraic expression that specifies the condition
for a flip-flop state transition. The left side of the equation denotes the next state of the flip-flop and the right
side, a Boolean function specifies the present state.

5. Define sequential circuit.

Sequential circuits are circuits in which the output variables dependent not only on the
present input variables but they also depend up on the past output of these input variables.
6. What do you mean by present state?
The information stored in the memory elements at any given time defines the present state
of the sequential circuit.
7. What do you mean by next state?
The present state and the external inputs determine the outputs and the next state of the
sequential circuit.
8. Define synchronous sequential circuit.
SynchronousSequential circuits are circuits in which the signals can affect the memory elements
only atdiscrete instant of time.
9. What are the steps for the design of asynchronous sequential circuit?
i) Construction of primitive flow table
ii) Reduction of flow table
iii) State assignment is made
iv) Realization of primitive flow table

*****************************************

Design of a Synchronous Decade Counter Using JK Flip- Flop (Apr 2018, Nov 2018)
A synchronous decade counter will count from zero to nine and repeat thesequence.
State diagram:
The state diagram of this counter is shown in Fig.

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Excitation table:

K-Map:

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Page 33
Logic Diagram:

*************************************

Design of an Asynchronous Decade Counter Using JK Flip- Flop.

An asynchronous decade counter will count from zero to nine and repeat thesequence. Since the
JK inputs are fed from the output of previous flip-flop,therefore, the design will not be as complicated as
the synchronous version.
At the ninth count, the counter is reset to begin counting at zero. The NAND gateis used to reset
the counter at the ninth count. At the ninth count the outputs offlip-flop Q3 and Q1 will be high
-flip. The
logic design of thecounter is shown in Fig.

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 **************************************

Design of a Synchronous Modulus-Six Counter Using SR Flip-Flop(Nov 2017)

The modulus six counters will count 0, 2, 3, 6, 5, and 1 and repeat the sequence.This modulus six
counter requires three SR flip-flops for the design.
State diagram:

Truth table:

K-Map:

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Logic Diagram:

SHIFT REGISTERS
Explain various types of shift registers. (or) Explain the operation of a 4-bit bidirectional shift register.
(Or) What are registers? Construct a 4 bit register using D-flip flops and explain the operations on the
register. (or) With diagram explain how two binary numbers are added serially using shift registers.
(Apr 2019)[NOV 2019]
A register is simply a group of Flip-Flops that can be used to store a binary number.
There must be one Flip-Flop for each bit in the binary number.
For instance, a register used to store an 8-bit binary number must have 8 Flip-Flops.
The Flip-Flops must be connected such that the binary number can be entered (shifted) into the
register and possibly shifted out.
A group of Flip-Flops connected to provide either or both of these functions is called a shift register.
A register capable of shifting the binary information held in each cell to its neighboring cell in a
selected direction is called a shift register.

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 There are four types of shift registers namely:
1. Serial In Serial Out Shift Register,
2. Serial In Parallel Out Shift Register
3. Parallel In Serial Out Shift Register
4. Parallel In Parallel Out Shift Register

1.Serial In Serial Out Shift Register

The block diagram of a serial out shift register is as below.

As seen, it accepts data serially .i.e., one bit at a time on a single input line. It produces the stored
information on its single output also in serial form.
Data may be shifted left using shift left register or shifted right using shift right register.

Shift Right Register

The circuit diagram using D flip-fops is shown in figure

As shown in above figure,the clock pulse is applied to all the flip-flops simultaneously.
The output of each flip-flop is connected to D input of the flip-flop at its right.
Each clock pulse shifts the contents of the register one bit position to the right.
New data is entered into stage A whereas the data presented in stage D are shifted out.
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 For example, consider that all stages are reset and a steady logical 1 is applied to the serial input
line.
When the first clock pulse is applied, flip-flop A is set and all other flip-flops are reset.
When the second clock pulse is shifted into flip-flop A
that was in flip flop A is shifted to flip-flop B.
This continues till all flip-flop sets.
The data in each stage after each clock pulse is shown in table below

Shift Left Register

The figure below shows the shift left register using D flip-flops.

The clock is applied to all the flip-flops simultaneously. The output of each flip-flop is connected
to D input of the flip-flop at its left.
Each clock pulse shifts the contents of the register one bit position to the left.
Let us illustrate the entry of the 4-bit binary number 1111 into the register beginning with the
right most bit.
When the first clock pulse is applied, flip flop A is set and all other flip-flops are reset.
When second clock pulse is ap 1 shifted into flip-
was in flip flop A is shifted toflip-flop B. This continues fill all flip-flop are set.
The data in each stage after each clock pulse is shown in table below.
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2. Serial in Parallel out shift register:
A 4 bit serial in parallel out shift register is shown in figure.

It consists of one serial input and outputs are taken from all the flip-flops simultaneously.
The output of each flip-flop is connected to D input of the flip-flop at its right. Each clock pulse
shifts the contents of the register one bit position to the right.
1
input line.
When the first clock pulse is applied flip flop A is set and all other flip-flops are reset.
When the second pulse 1 1
was in flip flop A is shifted into flip-flop B. This continues till all flip-flops are set. The data in
each stage after each clock pulse is shown in table below.

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3. Parallel In Serial Out Shift register:
For register with parallel data inputs, register the bits are entered simultaneously into their
respective stages on parallel lines.
A four bit parallel in serial out shift register is shown in figure. Let A,B,C and D be the four
parallel data input lines and SHIFT/LOAD is a control input that allows the four bits of data to be
entered in parallel or shift the serially.

When SHIFTS/LOAD is low, gates G1 through G3 are enabled, allowing the data at parallel
inputs to the D input of its respective flip-flop. When the clock pulse is applied the flip-flops with
D=1 will set and those with D=0 will reset, thereby storing all four bits simultaneously.

When SHIFT/LOADis high. AND gates G1 through G3 are disabled and gates G4 through G6are
enabled, allowing the data bits to shifts right from one stage to next. The OR gates allow either
the normal shifting operation or the parallel data entry operation, depending on which AND gates
are enabled by the level on the SHIFT/LOAD input.

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Parallel In Parallel OutShift Register:
In parallel in parallel out shift register, data inputs can be shifted either in or out of the register in
parallel.
A four bit parallel in parallel out shift register is shown in figure.Let A, B, C, D be the four
parallel data input lines and QA,QB,QC and QD be four parallel data output lines. The
SHIFT/LOAD is the control input that allows the four bits data to enter in parallel or shift the
serially.

When SHIFT/LOAD is low, gates G1 through G3 are enabled, allowing the data at parallel inputs
to the D input of its respective flip-flop. When the clock pulse is applied, the flip-flops with D =1
willset those with D=0 will reset thereby storing all four bits simultaneously. These are
immediately available at the outputs QA,QB,QC and QD.

When SHIFT/LOAD is high, gates G1, through G3 are disabled and gates G4 through G6 are
enabled allowing the data bits to shift right from one stage to another. The OR gates allow either
the normal shifting operation or the parallel data entry operation, depending on which AND gates
are enabled by the level on the SHIFT/LOAD input.
**************************************

Page 41
 Universal Shift Register:
Explain about universal shift register.( Apr -2018)
A register that can shift data to right and left and also has parallel load capabilities is called
universal shift register.
It has the following capabilities.
1. A clear control to clear the register to 0.
2. A clock input to synchronize the operations.
3. A shift right control to enable the shift right operation and the associated serial input
and output lines.
4. A shift left control to enable the shift left operation and the associated serial input and
output lines.
5. A parallel load control to enable a parallel transfer and the n input lines.
6. n parallel output lines.
7. A control state that leaves the information in the register unchanged in the presence of
the clock.

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 The diagram of 4-bit universal shift register that has all that capabilities listed above is shown in
figure. It consists of four D flip-flop and four multiplexers.All the multiplexers have two common
selection inputs S1 and S0. Input 0 is selected when S1S0=00, input 1 is selected when S1S0=01
and similarly for other two inputs.
The selection inputs control the mode of operation of the register. When S1S0=00, the present
value of the register is applied to the D inputs of the flip-flop. The next clock pulse transfers into
each flip-flop the binary value it held previously, and no change of state occurs.
When S1S0=01,terminal 1 of the multiplexer inputs has a path to be the D inputs of the flip-flops.
This causes a shift right operation, with the serial input transferred into flip-flop A3.
When S1S0=10, a shift left operation results with the other serial input going into flip-flop A0.
Finally, when S1 S0 = 11, the binary information on the parallel input lines is transferred into the
register simultaneously during the next clock edge. The function table is shown below.

****************************************
SHIFT REGISTER COUNTERS:
Explain about Johnson and Ring counter. (Nov 2018)
Most common shift register counters are Johnson counter and ring counter.
Johnson counter:
A 4 bit Johnson counter using D flip-flop is shown in figure. It is also called shift counter or
twisted counter.

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 The output of each flip-flop is connected to D input of the next stage. The inverted output of last
flip-flop QDis connected to the D input of the first flip-flop A.
Initially, assume that the counter is reset to 0. i.e., QA QB QC QD =0000. The value at DB =
DC=DD=0, whereas DA =1 since QD.
When the first clock pulse is applied, the first flip-flop A is set and the other flip-flops are reset.
i.e., QA QB QC QD =1000.
When the second clock pulse is applies, the counter is QA QB QC QD = 1100. This continues and

The sequence of states is shown in the table. As observed from the table, a 4-bit shift counter has
8 states. In general, an n-flip-flop Johnson counter will result in 2n states.

The timing diagram of Johnson counter is as follows:

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Ring Counter:

A 4- bit ring counter using D Flip-Flop is shown in figure.

As shown in figure, the true output of flip-flop D. i.e., QD is connected back to serial input of flip-
flop A.
Initially, 1 preset into the first flip-flop and the rest of the flip-flops are cleared i.e.,
QAQBQCQD=1000.
When the first clock pulse is applied, the second flip-flop is set to 1while the other three flip flops
are reset to 0.
in the second flip-flop is shifted to the third flip-
flop and so on.
The truth table which describes the operation of the ring counter is shown below.

As seen a 4-bit ring counter has 4 states. In general, an n-bit ring counter has n states. Since a
called a ring counter. The
timing diagram of the ring counter is shown in figure.

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 ******************************************

TWO MARKS
1. Define registers.
A register is a group of flip-flops. An-bit register has a group of n flip-flops and is capable of storing
any binary information/number containing n-bits.
2. Define shift registers.
A register capable of shifting its binary information in one or both directions is called as a
shift register. It consists of a chain of flip flops in cascade, with the output of one flip flop
connected to the input of the next flip-flop
3. What are the different types of shift registers?[Nov 2010,April 2007,Apr 2018, Nov 2018]
Serial In Serial Out Shift Register
Serial In Parallel Out Shift Register
Parallel In Serial Out Shift Register
Parallel In Parallel Out Shift Register
Bidirectional Shift Register
4. State the applications of shift register.
Shift registers are widely used in
Time delay circuits
As Serial to parallel converter
As Parallel to serial converters
As Counters

Page 46
5. Define Shift Register Counter.
A shift register can also be used as a counter. A shift register with the serial output
connection back to the serial input is called Shift register counter
6. What is bi-directional shift register and unidirectional shift register?
A register capable of shifting both right and left is called bi-directional shift register. A register capable of
shifting only one direction is called unidirectional shift register.
7. What are the two types of shift register counters?[April/May 2007,Nov/Dec 2006,2011,2012]
There are 2 types of shift Register counters are:
Ring counter:
A ring counter is a circular shift register with only one flip flop being set, at any particular
time, all others are cleared.
Johnson counters:
The Johnson counter is K-bit switch-tail rings counter2k decodinggates to provide outputs
for 2k t i m i n g s i g n a l s .
8. How can a SIPO shift register is converted in to SISO shift register? (Apr/May 2010)
By taking output only on the Q output of last flip flop SIPO shift register is converted in to
SISO shift register.
9. What is bi-directional shift register and unidirectional shift register?
A register capable of shifting both right and left is called bi-directional shift register. A register capable of
shifting only one direction is called unidirectional shift register.
10. What is sequence generator?
The sequential circuit used to repeat a particular sequence repeatedly is called Sequence
generator.

***********************************

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 HDL FOR SEQUENTIAL CIRCUITS
Write coding in HDL for various flip-flops.

Page 48
Page 49
Page 50
Page 51
Page 52
Test Bench:

Page 53
Write the VHDL Code for 4-Bit Binary Up Counter and explain. (Apr 2019)
VHDL Code for 4-Bit Binary Up Counter

The clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus,
all the flip-flops change state simultaneously (in parallel).

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vhdl_binary_counter is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end vhdl_binary_counter;
architecture bhv of vhdl_binary_counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin

tmp <= "0000";

tmp <= tmp + 1;

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end if;
end process;
Q <= tmp;
end bhv;

******************************************

TWO MARKS
1. Draw 5-bit Johnson counter.

2. Draw the diagram of 3-bit ripple counter.

3. Give few applications of shift register.

Serial to parallel converter
Parallel to serial converter
As a counter
To introduce delay in a digital circuit.

************************

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