0% found this document useful (0 votes)
12 views2 pages

Faculty of Engineering & Technology: Ganpat University

The document outlines the syllabus for the Computer System Architecture course for Diploma Engineering in Computer Engineering at Ganpat University, effective from the academic year 2019-20. It includes course learning outcomes, detailed unit content, and assessment schemes. Additionally, it lists reference books and online resources for further learning.

Uploaded by

Sathavara Dhruv
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
12 views2 pages

Faculty of Engineering & Technology: Ganpat University

The document outlines the syllabus for the Computer System Architecture course for Diploma Engineering in Computer Engineering at Ganpat University, effective from the academic year 2019-20. It includes course learning outcomes, detailed unit content, and assessment schemes. Additionally, it lists reference books and online resources for further learning.

Uploaded by

Sathavara Dhruv
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

GANPAT UNIVERSITY

FACULTY OF ENGINEERING & TECHNOLOGY


Programme Diploma Engineering Branch Computer Engineering
Semester IV Version 1.0.0.0
Effective from Academic Year 2019-20 Effective for the batch Admitted in July 2018
Subject code 1CE2405 Subject Name COMPUTER SYSTEM ARCHITECTURE
Teaching scheme Examination scheme (Marks)
(Per week) Lecture(DT) Practical(Lab.) Total CE SEE Total
L TU P TW
Credit 3 0 0 0 3 Theory 40 60 100
Hours 3 0 0 0 3 Practical 00 00 00

Pre-requisites:
Fundamental knowledge of computers

Course Learning Outcomes:


The course content should be taught and implemented with an aim to develop different skills leading to the
achievement of the following competencies and course learning outcomes:
T1. To learn the data transfer and micro-operation in computer system
T2. To draw flowchart of instruction and interrupt cycle
T3. To understand computer instruction set
T4. To Identify various types of memory in computers.
T5. To interface CPU-IOP communication

The practical should be carried out in such a manner that students are able to acquire different learning out
comes in cognitive, psychomotor and affective domain to demonstrate course learning outcomes.

Course Content
Name of UNIT Unit Content Unit Learning Outcomes Marks Hrs
UNIT – 1 1.1 Register Transfer 1a. Define symbols for register 10 08
1.2 Bus Transfer Transfer
REGISTER 1.3 Memory Transfer 1b. Understand Bus Transfer and
TRANSFER AND 1.4 Arithmetic Micro-operations Memory Transfer
MICRO- 1.5 Logic Micro-operations 1b. Identify different types of
OPERATIONS 1.6 Shift Micro-operations Micro-operations
1.7 Arithmetic Logic Shift Unit
UNIT – 2 2.1 Computer Registers 2a. State the role of registers 15 11
2.2 Computer Instruction Formats 2b. Develop a control timing signals
COMPUTER 2.3 Timing and Control Unit 2c. List Memory and Input-Output
INSTRUCTION 2.4 Instruction Cycle Instructions
FORMAT 2.5 Memory Reference Instructions 2d. Draw flowchart of Instruction
2.6 I/O Reference Instructions Cycle and Interrupt Cycle
2.7 Interrupt Cycle
UNIT – 3 3.1 CPU Instruction Formats 3a. Interpret instruction format 10 08
3.2 Addressing Mode 3b. Classify types of instructions
COMPUTER 3.3 Data Transfer Instructions 3c. Understand operation of
INSTRUCTION 3.4 Arithmetic Instructions instruction set
SET 3.5 Logic Instructions
3.6 Shift Instructions
3.7 Program Control Instructions
3.8 Subroutine Call and Return
UNIT – 4 4.1 Memory Classifications 4a. Classify types of Memory 15 10
4.2 Main Memory 4b. Understand Memory Hierarchy
MEMORY 4.3 Memory Hierarchy 4c. Distinguish Auxiliary and
ORGANIZATION 4.4 Auxiliary Memory Associative memory
4.5 Associative Memory 4d. Describe Cache Mapping
4.6 Cache Memory Scheme and Virtual map table
4.7 Virtual memory
UNIT – 5 5.1 Input Output Interface Unit 5a. Draw I/O Interface Unit 10 08
5.2 Asynchronous Data Transfer 5b. List modes of data transfer
INPUT OUTPUT 5.3 Asynchronous Serial Transfer 5c. Draw flowchart of CPU-IOP
ORGANIZATION 5.4 Input-Output Processor (IOP) communication
5.5 CPU-IOP Communication

List of Practical
---

List of Instruments / Equipment / Trainer Board


---

List of Reference Books


No Title of Reference Books Authors Publication
1 Computer System Architecture M. Morris Mano Pearson
2 Computer Organisation and SmrutiRanjanSarangi McGrawHill
Architecture
3 Computer Architecture BehroozParhami Oxford

Link of Learning Web Resource


1 https://nptel.ac.in/courses/106103068/pdf/coa.pdf
2 https://lecturenotes.in/subject/9/computer-organisation-and-architecture-coa
3 https://lecturenotes.in/u/hiteshmomaya

You might also like