STA Solved Problems VLSI Interview 2021

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Static Timing Analysis Basics

Static timing analysis (STA) based questions asked in the written test of a digital
interview. STA Problems to calculate setup time and hold time and maximum operating or
clock frequency or minimum Time Period required.

Before starting to read this article try to understand the basics of static timing analysis
(STA) such as,

1. What is Static Timing Analysis (STA)?

2. Why Static Timing Analysis (STA)?

3. Where we use STA Static Timing Analysis?

4. What is setup time and how to avoid setup time violations?

5. What is hold time and how to avoid hold time violations?

6. How to calculate the maximum clock frequency fmax or minimum time period Tmin
required for the given sequential circuit.

Setup time (Tsetup_time)

Well Setup time in STA is the minimum amount of time for which the input data must be
held stable or steady before the occurrence of the clock cycle event.

This constraint is met so that the input data must be reliably or correctly sampled during
the clock cycle event or I mean to avoid setup time violations.

Table of Contents

Hold time (Thold_time)

The hold time in STA is the minimum amount of required time for which the input data
must be held steady or stable after the occurrence of the clock cycle event.
This constraint is met so that the input data must be reliably or correctly sampled during
the clock cycle event or I mean to avoid hold time violations.

The hold time requirements become crucial as they cause critical timing problems in the
chip design.

It is possible to have a flip flop with 0 hold time or negative hold time.

For example, if the hold time is -3 ns then it complies that we should not have any
change in the input data before 3ns of the clock event trigger.

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Clock Skew (Tclock_skew)
Clock skew in STA is a time parameter that occurs when the difference in the arrival times
of the clock to two or more flip-flops that are in the same clock domain.

Clock to Q or Clock to output delay (Tclock_q)

Clock to Q delay in STA is simple the time delay difference between the clock pin of a flip-
flop to the output pin or After the clock trigger of a flop, the time taken by the input data
signal to reach the flop or register output i.e. Q.

Minimum Time Period (Tminimum) or Maximum clock operating

frequency (fmaximum)
To decide the speed of a chip design clock cycle frequency is the main parameter. We all
want a high-speed chip or processor which means the clock frequency must be as high
as possible.
But we also know that clock frequency is inversely proportional to clock time period. So
here we will have to constrain on the minimum time period to be decided.

Setup time constraint

Tsetup_time + Tclock_Q + delay <= Tminimum

Which says the overall sum of flop setup time and clock to Q delay and other delays such
as jitter must be less than or equals to the minimum clock time period.

Hold time constraint

Thold_time <= Tclock_Q + delay

The hold time must be less than or equals to the sum of the clock to Q delay and other
delays such as clock jitter.

Note:

If a situation comes to have a choice between setup violation fix and hold violation fix
after the chip design is completed and fabricated, then it is a better option to chose hold
violation fix.

The reason is to fix the setup time violation we need to modify Tminimum. As we saw
above setup time constraint involves clock time period parameter which decides the
overall chip speed which cannot be modified after the chip come from the foundry.

Let us discuss STA Problems

STA Problem 1

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Given the following flip-flop circuit with a delay dly between input and output. And the
clock CLK is applied to the flip flop.

a. What will be the expression for the minimum time period (Tminimum) or maximum
clock frequency (fmaximum)? Derive it by considering clock to Q delay (Tclock_Q), setup
time (Tsetup_time), and hold time (Thold_time) of the flipflop.

b. If the value of dly = 0ns, and given three flipflop values as per the table below, Which of
the flip flops are a good fit when the minimum required time period is 5ns, 8ns, and 15ns.

Flip Flops FF1 FF2 FF3

Tclock_Q 5 6 8

Tsetup_time 3 4 2

Thold_time 2 1 1

STA Problem Solution

a. From the above-given circuit

1. The output Q will be changed only after the clock event and till the clock to Q delay
elapsed.
2. Also the input data has an external delay of dly will add up to Tclock_Q

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So the expression will be for minimum clock period will be as below,

Tminimum >= Tsetup_time + Tclock_Q + dly

b. By using the above Tminimum expression let us calculate the minimum time periods
for flip flops FF1, FF2, and FF3 respectively.

Tminimum for FF1 = Tsetup_time of FF1 + Tclock_Q of FF1 + dly

Tminimum for FF1 = 3ns + 5ns + 0ns
Tminimum for FF1 = 8ns

Tminimum for FF2 = Tsetup_time of FF2 + Tclock_Q of FF2 + dly

Tminimum for FF2 = 6ns + 4ns + 0ns
Tminimum for FF2 = 10ns

Tminimum for FF3 = Tsetup_time of FF3 + Tclock_Q of FF3 + dly

Tminimum for FF3 = 8ns + 2ns + 0ns
Tminimum for FF3 = 10ns

For the time period requirement of 5ns none of the above flops can be used, and for 8ns
flop FF1 alone can be used. Whereas for the time period requirement of 15ns any one of
the above flip flops can be used.

STA Problem 2
Given the data setup time of the flop is 6ns, the hold time of the flop is 2ns, and the clock
to Q delay is given as 10ns.

a. Calculate the minimum clock period required to handle the circuit by drawing a digital
logic circuit for function clock frequency divided by 2.

b. Also determine the status of hold time violation and give a proper reason.

STA Problem Solution

a. The logic diagram for clock frequency divided by 2 would be as shown below.

The waveform of fin and fin/2 are as shown below

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By using above discussed Tminimum expression let us calculate the minimum time
period,

Tminimum >= Tsetup_time + Tclock_Q + dly

Tminimum >= 6ns + 10ns + 0
Tminimum >= 16ns

fmaximum >= 1/16ns

fmaximum >= 62.5MHz is the maximum possible frequency of operation for an above
circuit with given timing requirements.

b. Let us check for the hold violation, we have the hold time constraint as discussed at the
starting of this article,
Thold_time <= Tclock_Q + delay
2ns <= 10ns + 0
2ns <= 10ns
As we are satisfying the above condition there is no hold time violation in the circuit as
per the given timing requirements.

STA Problem 3
Consider the circuit diagram and the timing requirement as shown for the flip flop. Two
clock buffers are added at the clock pin and the output pin. Also a combination delay of
dly = 0.2ns in the input to the output path.

Check for any violation in the circuit with the given timing requirements, and If there any
violation then what would be the updated value of dly? Also is there any effect on
fmaximum due to added clock buffers.

STA Problem Solution

1. Let us check for the hold violation in the circuit. We know the constraint to be checked
that is,
Thold_time <= Tclock_Q + delay

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2ns <= 1.5ns + 0.2ns
2ns <= 1.7ns, as the condition fails we can say there is a hold time violation in the circuit.

2. To remove the above hold violation we can vary the dly to

Thold_time <= Tclock_Q + delay
dly >= Thold_time – Tclock_Q
dly >= 2ns – 1.5ns
dly >= 0.5ns The dly must be greater than or equals to 0.5ns to avoid hold violation in the
above circuit.

3. The clock buffer delays do not affect the fmaximum of the circuit.

STA Problem 4
Consider the below flip flop pair logic diagram and the table with three different flip flops
FF1, FF2, and FF3 with their timing specifications.

Which combination of flip flops should be replaced in the below flip flop pair to get the
maximum clock frequency of operation.

Flip Flops FF1 FF2 FF3

Tclock_Q 5 6 8

Tsetup_time 3 4 2

Thold_time 2 1 1

STA Problem Solution

The hint here is to replace the first flop place with the flip flop which has the minimum
clock to Q (Tclock_Q) delay and replace the second flop place with the flip flop having the
minimum setup time (Tsetup_time) among all of them.
So FF1 and FF3 flip flop pairs can be used in the logic circuit to have the maximum
frequency of operation.

STA Problem 5
Consider the below logic circuit with delays dly1, dly2, and dly3 at different places shown
and determine the constraints to avoid setup time and hold violation.

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Also for the given timing specifications calculate the maximum clock frequency of
operation or minimum required clock time period.
dly2 = 0.5ns and dly3 = 3ns. and
Tclock_Q1 = Tclock_Q2 = 2.5ns.
Tsetup_time1 = Tsetup_time2 = 2ns
Thold_time1 = Thold_time2 = 1ns

STA Problem Solution

a. Assume timing parameters for FF1 and FF2 as Tclock_Q1, Tsetup_time1, Thold_time1
and Tclock_Q2, Tsetup_time2, Thold_time2 respectively.
Let us assume positive clock skew and calculate delta = dly2 – dly3.

The setup time constrain when a pair of flops circuits is given will be,

Tminimum >= Tsetup_time2 + Tclock_Q1 + dly1 – delta

**Note the setup time of the second flip flop will be considered here.

And the hold time constraint for the same will be,

Thold_time2 <= Tclock_Q1 + dly1 – delta

**Note that the hold time of the second flip flop is considered.

b. We must calculate delta and dly1 values first

delta = delta2 – delta3
delta = 3ns – 0ns
delta = 2.5ns

and the dly1 value by considering there is no hold violation. therefore

Thold_time2 <= Tclock_Q1 + dly1 – delta

dly1 >= Thold_time2 – Tclock_Q1 + delta
dly1 >= 1ns – 2.5ns + 2.5ns
dly1 >= 1ns

Now by using setup time constraint we can compute minimum required clock period,
Tminimum >= Tsetup_time2 + Tclock_Q1 + dly1 – delta

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Tminimum >= 2ns + 2.5ns + 1ns – 2.5ns
Tminimum >= 3ns
therefore
fmaximum = 1/3ns = 333.33MHz is the maximum frequency of operation.

STA Problem 6
Consider the following circuit and given timing specifications to check whether there are
any violations. If there is any violation vary the delay values accordingly and calculate the
required minimum clock period.

Given timing specifications,

Tclock_Q1 = Tclock_Q2 = 2ns
Tsetup_time1 = Tsetup_time2 = 3ns
Thold_time1 = Thold_time2 = 6ns
The inverters have a delay of 1ns each and the NAND gate propagation delay is given as
2ns.

STA Problem Solution

After comparing this problem with the previous one we can observe that,

dly1 = 3 NOT gate delay + 1 NAND gate delay

dly1 = 1ns + 1ns + 1ns + 2ns
dly1 = 5ns

dly2 = 2 NOT gate delay

dly2 = 2ns

dly3 = 0ns

delta = dly2 – dly3

delta = 2ns – 0ns
delta = 2ns

Substituting all the values in the setup time constraint equation,

Tminimum >= Tsetup_time2 + Tclock_Q1 + dly1 – delta

Tminimum >= 3ns + 2ns + 5ns – 2ns

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Tminimum >= 8ns

fmaximum <= 1/8ns

fmaximum <= 125MHz is the maximum possible operating frequency for the above circuit
as per the given timing constraints.

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