VLSI: Physical Design (PD P2) — Input Files for PD

medium.com/@Tomodachi_Kushagra/vlsi-physical-design-pd-p2-input-files-for-pd-7e8678afe795

List of input files

There are several files that we pass as inputs to various steps of Physical Design. All the
files and processes are regarding the ICC II tool only. All the files are:

Netlist
SDC (Synopsys Design Constraint)
.lib file (Library Timing File)
.lef file (Library Exchange Format)
.tf (Technology file)
TLU+ file
Scan def file
MMMC (Multi-Mode Multi Corner)
UPF file (Power Intent File)
Don’t touch and Don’t use

1/6
A.Netlist
It contains the connectivity information of gates, RTL file is converted into a technology-
dependent gate-level netlist through the process of synthesis.

It contains:

Logic gates.
Flip flops.
Interconnection details.
Standard cells and macros information like name and drive strengths.

This is an important file and is required at every step of the physical design process. It is
given by the synthesis team. It has the extension of .v file.

B. SDC

2/6
This file is Synopsys Design Constraints. In this file, the synthesis team writes the timing
constraints to meet the timing parameter.

It contains:

Create clock definition (Source clock).

Generated clock definition (Any generated clock from the source clock or another
generated clock).
Input/output delay
Min/max delay
Max transition, max capacitance, max fanout
Clock latency, clock uncertainty.

It also contains clock exceptions like:

Multi-cycle path
Half cycle path
Disable time arc
Case analysis
False path

We will look in detail for all the clock exceptions in another article. This file is saved with
the .sdc extension. This is written in TCL.

C. .lib file
It contains timing information of standard cells, soft macros, and hard macros. It contains
Functionality information of standard cells and soft macros. Timing information like cell
delay setup, hold, recovery, and removal are present.

The file contains units for time, voltage, leakage power, capacitive load, slew rate, and
rise and fall time. Design rules like max tran, max cap, max fanout, min cap are present

Cell-specific information related to cells:

Area of cell
Power of cell
Capacitance
For each pin direction and their capacitance.

This file is provided by the vendor of the tool. This file is saved with a .lib extension.

D. Library Exchange File (.lef)

It contains physical information on standard cells, macros, and pads.

The information it contains is:

3/6
 Information about pin line pin name, space between pins, the direction of the pin,
location of the pin, a layer of pins, height, and width of the pin, and cell.
Macro information like cell name, size, dimensions, layout, blockages, and
capacitance are defined.

This file is provided by the tool vendor and is saved with the .lef extension.

E. Technology file (.tf)

It is a technology file that contains information about the number of metal layers and vias
and their name and conventions.

Also, it contains the design rule for the metal layers:

Width of each metal layer.

Distance between two metal layers.

This is the file in ASCII format and saved with the .tf extension in Synopsys and contains
the following things:

Metal layer name.

Type of metal.
Resistance and capacitance of metal per unit area.
Pitch between two layers.
Spacing between metal layers.
Unit, precision, color, and pattern of metal layer and via.
Maximum current density is also present in the tech file.

This file is given by the foundry.

F. TLU+ (Timing Library Update Plus)

This file contains:

It is a table containing wire caps at different net lengths and spacing.

Contains RC coefficient for a specific technology.
Extracted R, C parasitics of metal per unit length.

To load the TLU+ we need to load three files:

TLU+
Min TLU+
Max TLU+

G. Scan def file

4/6
Contains scan chain information of the design DFT team creates the Scan DEF and gives
as input to the PD team. This file is important to ease the process of connectivity in the
routing stage.

H. MMMC file
Multi-mode multi-corner file is used to generate different analysis views based on different
delay corners. There are various library set files based on voltage and temperature
values.

What it is exactly about is that an actual chip is going to work in different temperatures
and voltage levels, and the chip behaves differently in such cases, so to simulate this
effect in simulations we need variables that can be varied like process (SS, FF, SF,
FS…), temperature (low temp — -40C, medium temp — 0C, and high temp — 125C),
voltage called as PVT.

Generally, there are 216 corners in total. But, we test nearly 30–40 corners in the MMMC
file.

We have to do timing analysis on all corners so that the chip can function properly. So,
using all corners the run time is very high for approximately 30 to 40 corners taken for
timing analysis.

I. UPF file
The power intent file describes which power rails should be routed to individual blocks. It
also contains information on multi-voltage domains/low power designs (voltage shifters
always on Buffers Retention cells).

UPF (Unified Power Format) — Synopsys

CPF (Common Power Format) — Cadence

J. Don’t touch and don’t use

Suppose during Synthethis there is one NAND gate we want to retain this NAND gate
throughout our design. Hence, we will use don’t touch nets

Don’t touch the NAND gate

If we don’t want to use some during physical flow we give don’t use files For example
LUTs we are removing the don’t touch attribute on the LUTs only after the post-route
stage.

——————————————————————————-

These are files that will be used as inputs to the physical design stage of ASIC flow. Other
files are generated immediately in a few steps and then they are used in other steps (For
example, DEF file). But the files mentioned above are files that are given directly.

5/6
What is a DEF file? It is a Data Exchange File written in ASCII format which is used
to transfer the design from one EDA tool to another EDA tool for further
implementation. It was developed by Cadence Design System. For example IR
analysis on PnR database or STA on PnR database we transfer the design
database in form of a DEF file.

6/6