UNIT 3

CHAPTER 1
PROCESSOR LOGIC DESIGN
A processor unit is that part of a digital system or a digital computer that implements the opera-
tions in the system. It is comprised of a number of registers and the digital functions that imple-
ment arithmetic, logic, shift, and transfer microoperations. The processor unit, when combined
with a control unit that supervises the sequence of microoperations, is called a central processor
unit or CPU.

Processor Organization
Bus Organization
A bus organization for four processor registers is shown in Fig. 9-1. Each register is connected
to two multiplexers (MUX) to form input buses A and B. The selection lines of each
multiplexer select one register for the particular bus. The A and B buses are applied to a
common arithmetic logic unit. The function selected in the ALU determines the particular
operation that is to be performed. The shift microoperations are implemented in the shifter.
The result of the microoperation goes through the output bus S into the inputs of all registers.
The destination register that receives the information from the output bus is selected by a
decoder. When enabled, this decoder activates one of the register load inputs to provide a
transfer path between the data on the S bus and the inputs of the selected destination register.
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The control unit that supervises the processor bus system directs the information flow
through the ALU by selecting the various components in the unit. For example, to perform
the microoperation:
R1 R2 + R3

the control must provide binary selection variables to the following selector inputs:

1. MUX A selector: to place the contents of R2 onto bus A.

2. MUX B selector: to place the contents of R3 onto bus B.
3. ALU function selector: to provide the arithmetic operation A + B.
4. Shift selector: for direct transfer from the output of the ALU onto output bus S (no
shift).
5. Decoder destination selector: to transfer the contents of bus S into R 1.

Scratchpad Memory
The registers in a processor unit can be enclosed within a small memory unit. When included
in a processor unit, a small memory is sometimes called a scratchpad memory. The use of a
small memory is a cheaper alternative to connecting processor registers through a bus system.
The difference between the two systems is the manner in which information is selected for
transfer into the ALU. In a bus system, the information transfer is selected by the multiplexers
that form the buses. On the other hand, a single register in a group of registers organized as
a small memory must be selected by means of an address to the memory unit. A memory
register can function just as any other processor register as long as its only function is to hold
binary information to be processed in the ALU.

Consider, for example, a processor unit that employs eight registers of 16 bits each. The
registers can be enclosed within a small memory of eight words of 16 bits each, or an 8 ´
16 RAM. The eight memory words can be designated R0 through R7, corresponding to
addresses 0 through 7, and constitute the registers for the processor.

Assume that the memory has eight words, so that an address must be specified with three
bits. To perform the operation:
R1 R2 + R3

the control must provide binary selection variables to perform the following sequence of
three microoperations:

T1: A M [010] read R2 into register A

T2: B M [011] read R3 into register B
T3: M [001] A + B perform operation in
ALU and transfer

result to R 1
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Arithmetic Logic Unit

An arithmetic logic unit (ALU) is a multioperation, combinational-logic digital function. It
can perform a set of basic arithmetic operations and a set of logic operations. The ALU has
a num- ber of selection lines to select a particular operation in the unit. The selection lines
are decoded within the ALU so that k selection variables can specify up to 2k distinct
operations.
Figure 9-5 shows the block diagram of a 4-bit ALU. The four data inputs from A are com-
bined with the four inputs from B to generate an operation at the F outputs. The mode-
select input s2 distinguishes between arithmetic and logic operations. The two function-select
inputs s1and s specify the particular arithmetic or logic operation to be generated. With three
selectionvariables, it is possible to specify four arithmetic operations (with s2 in one state)
and four logic operations (with s2 in the other state). The input and output carries have
meaning only during an arithmetic operation.
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The design of a typical ALU will be carried out in three stages.

First, the design of the arithmetic section will be undertaken.
Second, the design of the logic section will be considered.
Finally, the arithmetic section will be modified so that it can perform both arithmetic and
logic operations.

Design of Arithmetic Circuit

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A 4-bit arithmetic circuit that performs eight arithmetic operations is shown in Fig. 9-8,
The four full-adder (FA) circuits constitute the parallel adder. The carry into the first stage is
the input carry. The carry out of the fourth stage is the output carry. All other carries are
connected internally from one stage to the next. The selection variables are s1 s0, and Cin.
Variables s1 and s0 control all of the B inputs to the full-adder circuits as in Fig. 9-7. The A
inputs go directly to the other inputs of the full adders.
The values of the Y inputs to the full-adder circuits are a function of selection variables s1 and
s0. Add- ing the value of Y in each case to the value of A plus the Cin value gives the
arithmetic operation in each entry.
The eight operations listed in the table follow directly from the function diagrams illustrated
in Fig. 9-6.
The combinational circuit that must be inserted in each stage between the exter- nal inputs
Ai and Bi and the inputs of the parallel adder Xi and Yi is a function of the arithmetic
operations that are to be implemented. The arithmetic circuit of Fig. 9-8 needs a
combinational circuit in each stage specified by the Boolean functions:

Xi = Ai

Yi = Bis0 + Bisi i = 1, 2, .... n

where n is the number of bits in the arithmetic circuit. In each stage i, we use the same
common selection variables s1 and s0. The combinational circuit will be di erent if the
circuit generates di erent arithmetic operations.
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Design of Logic Circuit:

The simplest and most straightforward way to design a logic circuit is shown in Fig. 9-11.
The diagram shows one typical stage designated by subscript i. The circuit must be repeated
n times for an n-bit logic circuit. The Four gates generate the four logic operations OR. XOR,
AND, and NOT. The two selection variables in the multiplexer select one of the gates for the
out- put. The function table lists the output logic generated as a function of the two selection
variables.
The logic circuit can be combined with the arithmetic circuit to produce one arithmetic
logic unit. Selection variables s1 and s0 can be made common to both sections provided we
use a third selection variable, s2, to di erentiate between the two. This configuration is
illustrated in Fig. 9-12. The outputs of the logic and arithmetic circuits in each stage go through
a multiplexer with selection variable s2. When s2 = 0, the arithmetic output is selected, but
 UNIT 3

when s2 = 1, the logic output is selected. Although the two circuits can be combined in this
manner, this is not the best way to design an ALU.
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Design of Arithmetic Logic Unit

The steps involved in the design of an ALU are as follows:
1. Design the arithmetic section independent of the logic section.
2. Determine the logic operations obtained from the arithmetic circuit in step 1, assuming that
the input carries to all stages are 0.
3. Modify the arithmetic circuit to obtain the required logic operations.
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The final ALU is shown in Fig. 9-13. Only the first two stages are drawn, but the diagram
can be easily extended to more stages. The inputs to each full-adder circuit are specified by
the Boolean functions:

Xi = Ai + s2s1s0Bi + s2s1s0Bi
Yi = s0Bi + s1Bi

Zi = s2Ci

When s2 = 0, the three functions reduce to;

Xi = Ai

Yi = s0Bi + s1Bi

Zi = Ci
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Status Register:
Figure 9-14 shows the block diagram of an 8-bit ALU with a 4-bit status register. The four
status bits are symbolized by C, S, Z, and V. The bits are set or cleared as a result of an operation
performed in the ALU.
1. Bit C is set if the output carry of the ALU is 1. It is cleared if the output carry is 0.
2. Bit S is set if the highest-order bit of the result in the output of the ALU (the sign bit) is
1. It is cleared if the highest-order bit is 0.
3. Bit Z is set if the output of the ALU contains all 0’s, and cleared otherwise. Z = 1 if
the result is zero, and Z = 0 if the result is nonzero.
4. Bit V is set if the exclusive-OR of carries C8 and C9 is 1, and cleared otherwise. This
is the condition for overfl w when the numbers are in sign-2’s-complement
representation (see Section 8-6). For the 8-bit ALU, V is set if the result is greater than
127 or less than 128.

Consider the operation A B done with two unsigned binary numbers. The relative magni- tudes
of A and B can be determined from the values transferred to the C and Z status bits. If Z =
1, then we know that A = B, since A B = 0. If Z = 0, then we know that A ≠ B. From Table 9-
2, we have that C = 1 if A > B and C = 0 if A < B. These conditions are listed in Table 9-5. The
table lists two other conditions. For A to be greater than but not equal to B (A > B), we must have
C = 1 and Z = 0. Since C is set when the result is 0, we must check Z to ensure that the result
is not 0. For A to be less than or equal to B(A B), the C bit must be 0 (for A < B) or the Z bit
must be 1 (for A = B). Table 9-5 also lists the Boolean functions that must be satisfied for each
of the six relationships.
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Now consider the operation A B done with two signed binary numbers when negative
numbers are in 2’s-complement form. The relative magnitudes of A and B can be determined
from the values transferred to the Z, S, and V status bits. If Z = 1, then we know that A = B; when
Z = 0, we have that A≠ B. If S = 0, the sign of the result is positive, so A must be greater than
B.This is true if there was no overflow and V = 0. If the result overflows, we obtain an errone-
ous result. It was shown in Section 8-5 that an overflow condition changes the sign of the result.
Therefore, if S = 1 and V = 1, it indicates that the result should have been positive and therefore
A must be greater than B.

Design of Shifter
A combinational-logic shifter can be constructed with multiplexers as shown in Fig. 9-15.
The two selection variables, H1 and H0, applied to all four multiplexers select the type of
opera- tion in the shifter. With H1H0 = 00, no shift is executed and the signals from F go
directly to the S lines. The next two selection variables cause a shift-right operation and a
shift-left operation. When H1H0 = 11, the multiplexers select the inputs attached to 0 and
as a consequence the S outputs are also equal to 0, blocking the transfer of information from
the ALU to the output bus. Table 9-7 summarizes the operation of the shifter.
The diagram of Fig. 9-15 shows only four stages of the shifter. The shifter, of course, must
consist of n stages in a system with n parallel lines. Inputs IR and IL serve as serial inputs for
the last and first stages during a shift-right or shift-left, respectively. Another selection variable
 UNIT 3

may be employed to specify what goes into IR or IL during the shift. For example, a third
selection vari- able, H2, when in one state can select a 0 for the serial input during the shift.
When H2 is in the other state, the information can be circulated around together with the
value of the carry status bit. In this way, a carry produced during an addition operation can be
shifted to the right and into the most significant bit position of a register.
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Processor Unit
A block diagram of a processor unit is shown in Fig 9-16(a). It consists of seven registers R1
through R7 and a status register. The outputs of the seven registers go through two multiplex-
ers to select the inputs to the ALU. Input data from an external source are also selected by
the same multiplexers. The output of the ALU goes through a shifter and then to a set of
external output terminals. The output from the shifter can be transferred to any one of the
registers or to an external destination.
There are 16 selection variables in the unit, and their function is specified by a control word in
Fig. 9-16(b). The 16-bit control word, when applied to the selection variables in the processor,
specifies a given microoperation. The control word is partitioned into six fields, with each
field designated by a letter name. All fields, except Cin, have a code of three bits. The three
bits of A select a source register for the input to left side of the ALU. The B field is the same,
but it selects the source information for the right input of the ALU. The D field selects a
destination register. The F field, together with the bit in Cin, selects a function for the ALU.
The H field selects the type of shift in the shifter unit.
 UNIT 3

Design of Accumulator
The block diagram of an accumulator that forms a sequential circuit is shown in Fig. 9-17,
The A register and the associated combinational circuit constitute a sequential circuit. The
com- binational circuit replaces the ALU but cannot be separated from the register, since it is
only the combinational-circuit part of a sequential circuit. The A register is referred to as the
accumulator register and is sometimes denoted by the symbol AC. Here, accumulator refers to
both the A reg-ister and its associated combinational circuit. The external inputs to the
accumulator are the data inputs from B and the control variables that determine the
microoperations for the register. The next state of register A is a function of its present state
and of the external inputs.
UNIT 3
 UNIT 3

CHAPTER 2
CONTROL LOGIC DESIGN

Hardwired Control Unit:

The control hardware can be viewed as a state machine that changes from one state to another
in every clock cycle, depending on the contents of the instruction register, the condition codes,
and the external inputs. The outputs of the state machine are the control signals. The sequence
of the operation carried out by this machine is determined by the wiring of the logic elements
and hence named “hardwired”.

Fixed logic circuits that correspond directly to the Boolean expressions are used to generate
the control signals.
Hardwired control is faster than micro-programmed control.
A controller that uses this approach can operate at high speed.
RISC architecture is based on the hardwired control unit

Micro-programmed Control Unit –

The control signals associated with operations are stored in special memory units inaccessible
by the programmer as Control Words.
Control signals are generated by a program that is similar to machine language programs.
The micro-programmed control unit is slower in speed because of the time it takes to fetch
microinstructions from the control memory.
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Control of Processor Unit

The processor unit is included in the diagram to show its connection to the microprogram
control unit. The first 16 bits of the microinstruction select the microoperation for the
processor. The other 10 bits select the next address for the control address register. The status
bits from the processor are applied to the inputs of a multiplexer. Both the normal and
complement values are used, except for the overflow bit V. Input 0 of MUX 2 is connected to
a binary constant which is always 1. The load input to CAR is enabled when this input is
selected by bits 18, 19, and 20 in the microinstruction. This causes a transfer of information
from the output of MUX 1 into CAR. The input into CAR is a function of bit 17 in the
microinstruction. If bit 17 is 1, CAR receives the address field of the microinstruction. If bit
17 is 0, an external address is loaded into CAR. The external address is for the purpose of
initiating a new sequence of microinstructions which can be specified by the external
environment. The status bit (or its complement) selected by bits 18, 19, and 20 of the
microinstruction may be equal to 1 or 0. The input address is loaded into CAR if the selected
bit is 1, but CAR is incremented if the selected bit is 0.
To construct correct microprograms, it is necessary to specify exactly how the status
bits are affected by each microoperation in the processor. The S (sign) and Z (zero)
bits are affected by all operations. The C (carry) and V (overflow) bits do not change
after the following ALU operations:

1. The four logic operations OR, AND, XOR, and complement.

2. The increment and decrement operations.

For all other operations, the output carry from the ALU goes into the C bit of the status
register. The C bit is also a ected after a circular shift with carry operation.
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PLA Control
The design of a control unit with a PLA is very similar to the design using the sequence
register and decoder methods. In fact, the sequence register in both methods is the same. The
dif- ference in the methods is in the way the combinational-logic part of the control is
implemented. The PLA essentially replaces the decoder and all other decision logic circuits
required in the hard-wired implementation.
The block diagram of the PLA control is shown in Fig. 10-18(a). The PLA is connected to a
sequence register with two flip-flops G1 and G2. The inputs to the PLA are the values of
the present state of the sequence register and the three external inputs. The outputs of the PLA
pro- vide the next state for the sequence register and the control output variables. At any given
time, the present state of the sequence register, together with input conditions, determines the
output values and the next state for the sequence register. The next clock pulse initiates the
microopera- tions specified by the outputs and transfers the next state into the sequence
 UNIT 3

register. This provides a new control state and possible different input values. Thus, the PLA
acts as the combinational- logic part of a sequential circuit to provide the control outputs and
the next state values for the sequence register.

Microprogram Sequencer

A microprogram control unit should be viewed as consisting of two parts: the control memory
that stores the microinstructions and the associated circuits that control the generation of the
next address. The address-generation part is sometimes called a microprogram sequencer,
since it se- quences the microinstructions in control memory. A microprogram sequencer can
be constructed with MSI circuits to suit a particular application. However, just as general-
purpose processor units are available in IC packages, so are general-purpose sequencers suited
for the construction of microprogram control units.
A typical sequencer provides the following address-sequencing capabilities:
UNIT 3
 UNIT 3

Computer Design
The computer consists of a central processor unit, a memory unit, and a teletypewriter
input-output unit.
The configuration of the computer is shown in Fig. 11-1. Each block represents a register,
except for the memory unit, the master-clock generator, and the control logic. This
configuration is assumed to satisfy the final system structure. In a practical situation, the
designer starts with a tentative system configuration and constantly modifies it during the
design process. The name of each register is written inside the block, together with a symbolic
designation in parentheses. The master-clock generator is a common clock-pulse source,
usually an oscillator, which generates a periodic train of pulses. These pulses are fanned
out by means of amplifiers and distributed over the entire system. Each pulse must reach
every flip-flop and register at the same time. Phasing delays may be needed intermittently so
that the di erence in transmission delays is uniform throughout. The frequency of the pulses is
a function of the speed with which the system operates. We shall assume a frequency of 1
megahertz, which gives one pulse every microsecond. This pulse frequency is chosen for the
sake of having a round number and to avoid problems of circuit propagation delays.
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Memory Address and Memory Buffer Registers

The memory address register, MAR, is used to address specific memory locations. MAR is loaded
from PC when an instruction is to be read from memory, and from the 12 least significant bits
of the B register when an operand is to be read from memory. Memory buffer register B holds
the word read from or written into memory
Program Counter
Program counter PC holds the address of the next instruction to be read from memory. This reg-
ister goes through a step-by-step counting sequence and causes the computer to read successive
instructions previously stored in memory.
Accumulator Register
Accumulator register A is a processor register that operates on data previously stored in memory.
This register is used to execute most instructions and for accepting data from the input device
or transferring data to the output device
Instruction Register
Instruction register I holds the operation-code bits of the current instruction. This register has
only four bits since the operation-code of instructions is four bits long.
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Sequence Register
Sequence register G is a counter that produces the timing signals for the computer. The G register
is decoded to supply four timing variables for the control unit.
E, F, and S Flip-flops
Each of these flip-flops is considered a one-bit register. The E flip-flop is an extension of the
A register. It is used during shifting operations, receives the end carry during addition, and
otherwise is a useful flip-flop that can simplify the data processing capabilities of the computer.
Input and Output Registers
The input-output (I/0) device is not shown in the block diagram of Fig. 11-1. It is assumed to
be a teletypewriter unit with a keyboard and a printer. The teletypewriter sends and receives
serial information.
Output register U works in a similar fashion, but the direction of information flow is re-
versed. Initially, the output flag in U9 is set to 1
 UNIT 3

CHAPTER 3
MICROCOMPUTER SYSTEM DESIGN

Microcomputer Organization
A typical microcomputer system consists of a microprocessor plus memory and I/O interface.
The various components that form the system are linked through buses that transfer instructions,
data, addresses, and control information among the IC components. Figure 12-1 shows the block
diagram of a microcomputer system. Typically, the microcomputer has a single microprocessor.
If many processors are included, then we have a multiprocessor system—which is a valid pos-
sibility. A number of RAM and ROM chips are combined to form a given memory size. The
in- terface units communicate with various external devices through the I/O bus. At any given
time, the microprocessor selects one of the units through its address bus. Data are transferred
to and from the selected unit and the microprocessor via the data bus. Control information is
usually transferred through individual lines, each specifying a particular control function.
The purpose of the microprocessor is to provide a CPU which interprets instruction codes
received from memory and to perform arithmetic, logic, and control operations on data stored
in internal registers, memory words, or interface units. The microprocessor contains a number
of registers, an arithmetic logic unit, and timing and control logic. Externally, it provides a bus
system for transferring instructions, data, and control information to and from the modules
connected to it.
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The random-access memory is a read-write memory type and consists of a number of IC

packages connected together. The RAM is used to store data, variable parameters, and inter-
mediate results that need updating and are subject to change. The ROM consists of a number
of IC packages and is used for storing programs and tables of constants that are not subject
to change once the production of the microcomputer system is completed.
The interface units provide the necessary paths for transferring information between the
microprocessor and external input and output devices connected to the I/O bus.
The data bus transfers data to and from the microprocessor and the memory or interface
which is selected by the address bus. The data bus is bidirectional, which means that the binary
information can flow in either direction. A bidirectional data bus is used to save pins in the
IC package.

Microprocessor Organization
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The clock input is used by the microprocessor to generate multiphase clock pulses that pro- vide
timing and control for internal functions. Some microprocessors require an external clock
generator to supply the clock pulses.
The reset input is used to reset and start the microprocessor after power is turned on or any
time the user wants to start the process from the beginning.
The interrupt request into the microprocessor typically comes from an interface module to
inform the microprocessor that it is ready to transfer information. When the microprocessor
ac- knowledges the interrupt request, it suspends the execution of the current program and
branches to a program that services the interface module.
The bus-request control input is a request to the microprocessor to temporarily suspend its
operation and drive all buses into their high-impedance state. When the request is
acknowledged, the microprocessor responds by enabling the bus-granted control output
line.
The read and write are control lines that inform the component selected by the address bus of
the direction of transfer expected in the data bus. The read line informs the selected unit that
the data bus is in an input mode and that the microprocessor will accept data from the data
bus.
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Instructions and Addressing Modes

Basic Set of Microprocessor Instructions
Microprocessor instructions may be classified into three distinct types.

1. Transfer instructions that move data among registers, memory words, and interface
registers without changing the binary information content.
2. Operation instructions that perform operations on data stored in registers or memory
words.
3. Control instructions used to test status conditions in registers and, depending on
results, cause a change in program sequence.

Instructions for Microprocessor

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Addressing Modes

Implied mode
In this mode, the instruction contains an indirect definition of the operand. An example of an
implied mode instruction is CMA (complement accumulator). Here, the operand (complement)
is implicitly specified in the instruction.

Immediate addressing mode

In this mode, the instruction contains both the opcode and the operand. It can be said that an
instruction that uses the immediate addressing mode contains an operand field in place of an
address field. The operation, as well as the operands, are mentioned in the instruction. An
example of immediate addressing mode instruction is ADD 10. Here, ADD, which is the
operation, and 10, which is the operand, are specified.

Direct addressing mode

In this mode, the instruction specifies an address. This address is the address of the operand.
An example of a direct addressing mode instruction is:
AC = AC + [X]
This will add the operand stored at address X with the operand stored in the accumulator. This
mode is also referred to as absolute addressing mode.

Indirect addressing mode

In this mode, the instruction specifies an address. The memory location specified by the address
contains the address of the operand. An example of an indirect addressing mode instruction is:
AC = AC + [[X]]
This will add the operand stored at the address specified by the memory location X with the
contents of the accumulator.

Register mode
In this mode, the instruction specifies a register. This register stores the operand. An example
of register mode instruction is:
AC = AC + [R]
This will add the operand stored at register R to the operand stored in the accumulator.

Register indirect mode

In this mode, the instruction specifies a register. This register stores the effective address of the
operand. An instruction that uses register indirect addressing mode is:
AC = AC + [[R]]
Here, the contents which reside in the memory location specified by the register R will be added
to the contents of the accumulator.

Relative address mode

In this mode, the contents of the address field are added to the constant stored in the program
counter. The result of the addition gives the address of the operand. For example, suppose the
address field contains 850, and the program counter contains 20, then the operand will be at
memory location 850 + 20 = 870.
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Indexed addressing mode

In this mode, the address of the operand is determined by adding the contents of the address
field and the contents of the index register.

Base register addressing mode

In this mode, the address of the operand is determined by adding the contents of the address
field and the contents of the base register.

Subroutines
A subroutine is a self-contained sequence of instructions that performs a given task. During
normal execution of a program, a subroutine may be called to perform its function many
times at various points in the main program. Each time a subroutine is called, a branch is
executed to the beginning of the subroutine to start executing its set of instructions. .After the
subroutine has been executed, a branch is made back to the main program. Because branching
to a subroutine and returning to the main program is a common operation, all processors
provide special instruc- tions to facilitate subroutine entry and return.
Figure 12-9 demonstrates by example the process of subroutine call and return in an 8-bit
microprocessor. Three separate portions of memory are shown: the main program, a
subroutine program, and a memory stack. The computer is now executing the main program,
with PC point- ing at the instruction in location 3500. The subroutine program starts at
location 2673, and the top of the stack is specified by SP at address 7803. This is shown
in Fig. 12-9(a) with all ad- dresses having hexadecimal values. The call-subroutine
instruction has associated with it a two- byte address and each byte occupies one memory
location. The last instruction of the subroutine in location 2686 has the operation code of
the return-from-subroutine instruction. The top of the stack now contains a byte (designated
by hexadecimal 46), but this is not important for the pres- ent discussion.
The execution of the call-subroutine instruction in the main program is carried out as fol-
lows: (1) The address associated with the instruction (2673) is transferred to PC. (2) The
return address to the main program (3503) is pushed into the stack. The result of these two
operations is shown in Fig. 12-9(b). PC now points at location 2673, which is the address of
the first instruc- tion in the subroutine. Return address 3503 is pushed into the stack and
occupies two bytes of memory. The computer now continues by executing the instructions in
the subroutine program, since PC points at the first instruction of the subroutine.
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Interrupt
The concept of program interrupt is used to handle a variety of problems that arise out of normal
program sequence. Program interrupt refers to the transfer of control from a currently running
program to another service program as a result of an externally generated control signal.
A microprocessor may have single or multiple interrupt input lines. If there are more interrupt
sources than there are interrupt inputs in the microprocessor, two or more sources are ORed
together to form a common line for the microprocessor. An interrupt signal into a
microprocessor may originate at any time during program execution. To ensure that no
information is lost, the microprocessor acknowledges the interrupt only after the execution
of the current instruction is completed and if the state of the processor warrants it. Figure 12-
10 shows a possible vectored interrupt configuration. The diagram shows four sources ORed
to a single interrupt-request in- put. The microprocessor has within it an interrupt enable (IEN)
flip-flop that can be set or cleared with program instructions. When IEN is cleared, the
interrupt request is neglected. If IEN is set and the microprocessor is at the end of instruction
execution, the microprocessor acknowledges the interrupt by enabling 1NTACK. The interrupt
source responds to INTACK by placing an inter- rupt vector into DBUS. The program
controlled IEN flip-flop allows the programmer to decide whether to use the interrupt facility
or not. If an instruction to clear IEN has been inserted in the program, it means that the
programmer does not want the program to be interrupted. (IEN is also cleared with a reset
signal.) An instruction to set IEN indicates that the interrupt facility will be used while the
program is running. Some microprocessors use an interrupt mask bit in the status register
instead of a separate IEN flip-flop.
 UNIT 3

Assume that the interrupt vector supplied to the data bus is an 8-bit address. The microprocessor
responds to an interrupt request by performing the following operations:

SP SP + 1, M [SP] PC (H) push first byte of return address

SP SP + 1, M [SP] PC (L) push second byte of return address

1NTACK 1 enable interrupt acknowledge PC (H)

0, PC (L) DBUS transfer vector address to PC

IEN 0 disable further interrupts

Memory Organization
RAM and ROM Chips
The block diagram of a RAM chip suited for microcomputer applications is shown in Fig. 12-
11. The capacity of the memory is 128 words of 8 bits each. This requires a 7-bit address and
an 8-bit bidirectional data bus. The read and write inputs specify the memory operation, and
the two chip select (CS) control inputs are for enabling the chip only when it is selected by the
microprocessor. The availability of more than one control input to select the chip facilitates
the decoding of the address lines when multiple chips are used in the microcomputer. The
read and write inputs are sometimes combined into one line labeled R/W. When the chip is
selected, the two binary states in this line specify the two operations of read and write.
The function table listed in Fig. 12-11(b) specifies the operation of the RAM chip. The unit is
in operation only when CS1= 1 and CS 2 = 0. The bar on top of the second select variable indi-
cates that this input is enabled when it is 0. If the chip select inputs are not enabled, or if they
 UNIT 3

are enabled but the read and write inputs are not enabled, the memory is inhibited and its data
bus is in a high-impedance state. When CS1 = 1 and CS 2 = 0, the memory can be placed in a
write or read mode. When the WR input is enabled, the memory stores a byte from the data
bus into a location specified by the address input lines. When the RD input is enabled, the
contents of the selected byte are placed on the data bus. The RD and WR signals control the
memory operation as well as the bus bu ers associated with the bidirectional data bus.
A ROM chip is organized externally in a similar manner. However, since a ROM can only read, the
data bus can only be in an output mode. The block diagram of a ROM chip is shown in Fig. 12-12. For
the same-size chip, it is possible to have more bits of ROM than of RAM, because the internal binary
cells in ROM occupy less space than in RAM. For this reason, the diagram specifies a 512-byte ROM.
whereas the RAM has only 128 bytes.
 UNIT 3

Memory Address Map

The table, called a memory address map, is a pictorial representation of assigned address
space for each chip in the system. To demonstrate with an example, assume that a
microcomputer system needs 512 bytes of RAM and 512 bytes of ROM. The RAM and ROM
chips to be used are specified in Figs. 12-11 and 12-12. The memory address map for this
configuration is shown in Table 12-5. The compo- nent column specifies whether a RAM or a
ROM chip is used. The hexadecimal address column assigns a range of hexadecimal
equivalent addresses for each chip. The address bus lines are listed in the third column.
Although there are 16 lines in the address bus, the table shows only 10 lines because the
other 6 are not used in this example and are assumed to be zero. The small x’s under the
address bus lines designate those lines that must be connected to the address inputs in each
chip. The RAM chips have 128 bytes and need 7 address lines. The ROM chip has 512 bytes
and needs 9 address lines. The x’s are always assigned to the low-order bus lines—lines 1
through 7 for the RAM and lines 1 through 9 for the ROM. It is now necessary to distinguish
between four RAM chips by assigning to each a di erent address. For this particular example,
we choose bus lines 8 and 9 to represent four distinct binary combinations. Note that any other
pair of unused bus lines can be chosen for this purpose. The table clearly shows that the 9
low-order bus lines constitute a memory space for RAM equal to 29= 512 bytes. The
distinction between a RAM and ROM address is done with another bus line. For this purpose,
we choose line 10. When line 10 is 0, the microprocessor selects a RAM, and when this line
is 1, it selects the ROM.

Memory Connection to Microprocessor

RAM and ROM chips are connected to a microprocessor through the data and address buses.
The low-order lines in the address bus select the byte within the chips, and other lines in the
address bus select a particular chip through its chip select inputs. The connection of memory
chips to the microprocessor is shown in Fig 12-13. This configuration gives a memory
capacity of 512 bytes of RAM and 512 bytes of ROM. It implements the memory map of Table
12-5. Each RAM receives the 7 low-order bits of the address bus to select one of 128 bytes
possible.The particular RAM chip selected is determined from lines 8 and 9 in the address
bus. This is done through a 2 4 decoder whose outputs go to the CS1 inputs in each RAM
chip. Thus, when address lines 8 and 9 are equal to 00, the first RAM chip is selected. When
01, the second RAM chip is selected, and so on. The RD and WR outputs from the
 UNIT 3

microprocessor are applied to the inputs of each RAM chip.

 UNIT 3

Input-output Interface
Most LSI interface components can be programmed to accommodate a variety of combina-
tions of operating modes. The microprocessor, through program instructions, transfers a byte
to a control register inside the interface unit. This control information puts the interface in one
of the possible modes suitable for the particular device to which it is attached. By changing
the control byte, it is possible to change the interface characteristics. For this reason, LSI
interface units are often said to be programmable. The instructions that transfer control
information into a program- mable interface are included in the microcomputer program and
they initialize the interface for a particular mode of operation.
Manufacturers of microprocessors supplement their product with a set of interface chips
suitable for communication between the microprocessor and a variety of standard input and
out- put devices. Interface components are usually designed to operate with a particular
microproces- sor system bus with no additional logic besides address decoding. There are a
variety of interface components in commercial use and each can be classified to be in one of
four categories:

1. A parallel peripheral interface transfers data in parallel between the microprocessor

and a peripheral device.
2. A serial communication interface converts parallel data from the microprocessor into
serial data for transmission and converts incoming serial data into parallel data for recep-
tion by the microprocessor.
3. A special dedicated interface is constructed to communicate with one particular input-
output device, or can be programmed to operate with a particular device.
4. A direct memory access (DMA) interface is used for transferring data directly between
an external device and memory. The bus bu ers in the microprocessor are disabled and
go into a high-impedance state during DMA transfer.

Direct Memory Access

The transfer of data between a mass storage device, such as magnetic disk or magnetic tape,
and system memory is often limited by the speed of the microprocessor. Removing the
processor during such a transfer and letting the peripheral device manage the transfer
directly to memory would improve the speed of transfer and make the system more e cient.
This transfer technique is called DMA (direct memory access). During DMA transfer, the
processor is idle; so it no lon- ger has control of the system bus. A DMA controller takes over
the buses to manage the transfer directly between the peripheral device and memory.
Figure 12-18 shows the block diagram of a typical DMA controller. The unit
communicates with the microprocessor via the data bus and control lines. The
registers in the DMA are selected by the microprocessor through its address lines
by enabling CS (chip select) and RS (register select). The RD and WR lines in the
DMA are bidirectional. With BG = 0, the microprocessor communicates with the
DMA register through the data bus to read from or write into the DMA registers.
When BG = 1, DMA can communicate directly with the memory by specifying an
ad- dress in the address bus and activating its RD or WR control. The DMA
 UNIT 3

communicates with an external peripheral device through the request and

acknowledge lines.

The microprocessor initializes the DMA by sending the following information

through the data bus:

1. The starting address of the memory block where data are available (for read)
or where data are to be stored (for write).
2. The byte count, which is the number of bytes in the memory block.
3. Control bits to specify a read or write transfer.
4. A control bit to start the DMA.
UNIT 3
 UNIT 3

Input-Output Processor
The Input-Output Processor (IOP) is just like a CPU that handles the details of I/O operations.
It is more equipped with facilities than those available in a typical DMA controller. The IOP
can fetch and execute its own instructions that are specifically designed to characterize I/O
transfers. In addition to the I/O-related tasks, it can perform other processing tasks like
arithmetic, logic, branching, and code translation. The main memory unit takes a pivotal role.
It communicates with the processor by means of DMA.
The Input-Output Processor is a specialized processor which loads and stores data in memory
along with the execution of I/O instructions. It acts as an interface between the system and
devices. It involves a sequence of events to execute I/O operations and then store the results
in memory.

Features of an Input-Output Processor

Specialized Hardware: An IOP is equipped with specialized hardware that is optimized for
handling input/output operations. This hardware includes input/output ports, DMA
controllers, and interrupt controllers.
DMA Capability: An IOP has the capability to perform Direct Memory Access (DMA)
operations. DMA allows data to be transferred directly between peripheral devices and
memory without going through the CPU, thereby freeing up the CPU for other tasks.
Interrupt Handling: An IOP can handle interrupts from peripheral devices and manage them
independently of the CPU. This allows the CPU to focus on executing application programs
while the IOP handles interrupts from peripheral devices.
Protocol Handling: An IOP can handle communication protocols for different types of
devices such as Ethernet, USB, and SCSI. This allows the IOP to interface with a wide range
of devices without requiring additional software support from the CPU.
Buffering: An IOP can buffer data between the CPU and peripheral devices. This allows the
 UNIT 3

IOP to handle large amounts of data without overloading the CPU or the peripheral devices.
Command Processing: An IOP can process commands from peripheral devices
independently of the CPU. This allows the CPU to focus on executing application programs
while the IOP handles peripheral device commands.
Parallel Processing: An IOP can perform input/output operations in parallel with the CPU.
This allows the system to handle multiple tasks simultaneously and improve overall system
performance.
Advantages of Input-Output Processor
The I/O devices can directly access the main memory without the intervention of the processor
in I/O processor-based systems.
It is used to address the problems that arise in the Direct memory access method.
Reduced Processor Workload: With an I/O processor, the main processor doesn’t have to
deal with I/O operations, allowing it to focus on other tasks. This results in more efficient use
of the processor’s resources and can lead to faster overall system performance.
Improved Data Transfer Rates: Since the I/O processor can access memory directly, data
transfers between I/O devices and memory can be faster and more efficient than with other
methods.
Increased System Reliability: By offloading I/O tasks to a dedicated processor, the system
can be made more fault-tolerant. For example, if an I/O operation fails, it won’t affect other
system processes.
Scalability: I/O processor-based systems can be designed to scale easily, allowing for
additional I/O processors to be added as needed. This can be particularly useful in large-scale
data centres or other environments where the number of I/O devices is constantly changing.
Flexibility: I/O processor-based systems can be designed to handle a wide range of I/O
devices and interfaces, providing more flexibility in system design and allowing for better
customization to meet specific requirements.

Difference between Input and Output devices/Characteristics

Input Device Output Device

It is a hardware device and is used to key in It is a hardware component, and it uses the data
the data, instructions or commands, into the that is has received from the computer to carry out
computer a task

It can transfer data to another device, but Can obtain data from another device and can also
cannot receive any from it produce output from it. However, cannot transfer
data to another device

Necessary for the computer to receive user Required if a computer has to share its results.
commands and data to process They also help to prompt the users for additional
information and commands
 UNIT 3

These are user controlled Computer manages it

Complex coding is used Users need to only see the results and so are not
required to learn the process

Examples: Keyboard, webcam, microphone, Examples: LCD Projection panels, printer,

joystick and so on monitor, speaker and more