o Date: 06/11/24

o compile directives
guildines to the compiler
ex: model sim,questa, vcs

list of compiler directives

o `include - used to include a verilog file to another verilog file
o `define - used for defining the macros
o `timescale
o `if
o `elseif
o `else
o `endif

o defining the macro

`define SIZE 20
reg [`SIZE-1:0]a;
o macros can also have arguments
we can have same macros with diffrent reqirements

ex:
`define SIZE 20
`define SIZE 15// we cannot write teh same macro with
doffrent values
reg [`SIZE-1:0]a;
reg [`SIZE-1:0]b;

o it is possible to use same macro with diffrent values

`define SIZE(MSB,LSB) reg [MSB+LSB-1:LSB]

`SIZE(19,0) a;//we want size of a is 20

`SIZE(14,0) b;//we want size of b is 15

o diffrence between parameter and macro ?

o `timescale
giving guildines to compiler how the simulation events to be executed

`timescale timestep /presion

for ex:
it timestep is 10 ns
event execution interval is 10ns
o timestep
specifs the base unit of time for
each delay in the module
o timepresion
specifs the presion or the smallest
step of the time that can be simulated
 for ex:
`timescale 1ns/1ps
#5; // defaukt time scale ,is 1ns
i.e 5 * 1ns
timeunit/timestep
every delay is interuppeted in ns

timeprecision
if the time precision is set to 1ps ,any delay
less than 1 ps will be roudeed of to zero , other cas eif it is larger than
1ps ,is roudeed to the nearest ps

o default timescale is `timescale 1ns/1ns

o we can also give our own time scale

o possible timescsles
- `timescale 1ns/1ps
- `timescale 10ns/10ps
- `timescale 1ns/10ps
o we ca nspecify the doiffrent timescale for each file

o `if ,`else `elsif ,`endif

the macros provides the flexibitlky to implement the diifrent

requirments of a piece of code in same file
o in compile time we can choose which specific code can be exeuted
which not be exeuted

ex:
// example for 2x1 mux in all abstraction levels(ecept switch level )
module compile_direct(i0,i1,s,y);
input i0,i1,s;
`ifdef BEHAV
output reg y;
`else
output y;
`endif
`ifdef BEHAV// bhv
always @(*)begin
y=s?i1:i0;
end
`elsif DATA//data
assign y=s?i1:i0;
`else
//gate
not g1(n1,s);
and g2(n2,n1,i0);
and g3(n3,s,i1);
or g4(y,n2,n3);
`endif
endmodule

in compile time we decide whic h abstraction level toi be executed

vlog compile_direct.v +define=BEHAV

o task and function

 => diffrences
o task
-> task executes in either delay time or in zero time
-> task can enable(call) other task and function
-> task can have either no arguments or both inputs and ouput arguments
-> task doent return any value
-> syntax
task task_name (i/p and o/p arguments );
begin
// statments
end
endtask

o function
-> function must be executes in zero time only
-> function can enable(call) other function but not task
-> function can have only input arguments , and alleast one argument
-> function can return any value
-> syntax
function return_type func_name(i/p arguments );
begin
// statments
func_name=expression;
end
endfunction

=> guildines
-> decalaration must be outside the procedural block
-> call must be done from in procedural block
-> logic must be present between begin and end

o write a logic to get alu operation for two operands based on 2 bit control
signal using function

function integer alu (input integer a,b ,reg [1:0]c);

begin
case (c)
0:alu=a+b;
1:alu=a-b;
2:alu=a/b;
3:alu=a*b;
end
endfunction
always @(*)begin
out= alu(a,b,c);
end

o automatic/static task and function

o Automatic
- if same task/ function is called multiple time ,executes happens in
diffrent memory location
- Generally used for where recursive function /task is required
o Static
- if same task/ function is called multiple time ,executes happens in same
memory location,existing values gets overriden
 o by default task and functions are in static in nature in verilog
o to get automatic task/function we use automatic keyword in decaration

Q. if task doesnt conatains any delay ,then is this called in function ?

- YES
Q. is tasks and functions are synthasizable ?
-YES(if only task doesnt conatains any delay )

Q . fork join
statements inside procedural block executes sequentilly
all procedural will be executes in parallel
all procedural will be starts at zero time

ex:
#5;
initial begin
#5 a=10;
$display("");
end
o how many proceses?
-2
o how many statements inside proceses?
-2
o at what time display statements will executes?\
- 5 ns
o at what time a value is assigned ?
- 0ns
ex:
#5;
initial begin
fork
#5 a=10;
$display("");
join
end:P1
initial begin
fork
#5; b=10;
$display("");
join
end:P2
initial begin
fork
begin
#5;
end
b=10;
$display("");
join
end:P3
o at what time display statements will executes?\
- 0 ns
o at what time a value is assigned ?
- 5 ns
o at what time b value is assigned ?
- 0 ns
o how many statements inside p2?
-3
o what is the total time taken by p2?
- 5ns
o how many statements inside p3?
-3
o what is the total time taken by p3?
- 5ns
o how many proceses in p3?
-3