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AugustSeptember 2021

This document outlines the examination structure for the B. Tech II Year II Semester in Digital Electronics at Jawaharlal Nehru Technological University Hyderabad. It includes a list of topics and questions covering Boolean algebra, logic families, circuit design, flip-flops, counters, D/A converters, and PLAs. Students are required to answer any five questions, with equal marks for each.

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7 views1 page

AugustSeptember 2021

This document outlines the examination structure for the B. Tech II Year II Semester in Digital Electronics at Jawaharlal Nehru Technological University Hyderabad. It includes a list of topics and questions covering Boolean algebra, logic families, circuit design, flip-flops, counters, D/A converters, and PLAs. Students are required to answer any five questions, with equal marks for each.

Uploaded by

debbekrishna
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Code No: 154AN R18

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD


B. Tech II Year II Semester Examinations, August/September - 2021
JN
DIGITAL ELECTRONICS
(Electrical and Electronics Engineering)
Time: 3 Hours Max. Marks: 75
TU
Answer any five questions
All questions carry equal marks
---
H
1.a) Write the Properties/Laws of Boolean algebra?
b) A 12-bit Hamming code word containing 8 bits of data and 4 parity bits is read from
memory. What is the original 8 bit word if the 12 bit read out is 1010 1001 1101. [8+7]
us
2.a) Compare different logic families.
b) Realize 2-input NAND gate using CMOS logic. [7+8]
ed
3.a) Find F in POS form for F (A, B, C, D) = Π (1, 3, 7, 11, 15) + d (0, 2, 5).
b) Simplify the function F (A, B, C, D) = Σ (0, 1, 3, 4, 6, 8, 15) using K-Map. [7+8]
pa
4.a) Design a full adder and implement it using multiplexer.
b) Design a 3 to 8 decoder circuit using 2 to 4 decoder circuits. [8+7]

5.a) What is the difference between edge triggering and level triggering? Explain about edge
pe
triggered D flip-flop with a neat diagram.
b) Draw the schematic circuit of J-K flip-flop and explain its operation with the help of
truth table. [7+8]
rs
6.a) Design a Modulo-7 synchronous counter using J K Flip-Flop. Draw its state diagram and
Timing Waveforms.
Se
b) Implement a 3-bit down counter using D flip flop. [8+7]

7.a) Explain the weighted resistor type D/A converter with neat block diagram.
b) A dual slope ADC uses a 16-bit counter and a 4 MHz clock rate. The Maximum input
p2
voltage is =10V. The maximum integrator output voltage should be -8V when the
counter has cycled through 2n counts. The capacitor used in the integrator is 0.1μF.
Find the value of the resistor R of the integrator. If the analog signal is = 4. 129 V, find
the corresponding binary number. [8+7]
02
8.a) What are the draw backs of PLAs? How PLAs are used to implement combinational
and sequential logic circuits?
1
b) Explain the detailed logic configurable Block Architecture of FPGA. [7+8]

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