Document 90
Document 90
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2. Explain the working principle of a static RAM cell with proper diagram?
1. Write Operation:
a. The word line (WL) activates, enabling access transistors.
b. The bit lines (BL and BL') carry the data to overwrite the latch's state.
c. The latch retains the written value when WL is deactivated.
2. Read Operation:
a. WL activates, allowing the latch to drive the bit lines.
b. The stored value is read as the voltage difference between BL and BL'.
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4. Explain the difference between three address, two address, one address and zero
address instruction using suitable example?
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5. Given a non-pipelined processor with 15ns clock period. How many stages of the
pipelined version of
the processor are required to achieve a clock period of 4 ns? Assume the interface latch
has delay of 0.5 ns?
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6. Briefly describe the following addressing modes with an example: a)implied b)direct
c)immediate
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7. Explain Flynn’s Classification with Diagrammatic representation?
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features such as:
1. Narrow Access: The cache allows faster access to small blocks of data,
reducing delays compared to accessing main memory.
2. Increased Speed: Cache memory speeds up processing by storing
frequently accessed data.
3. Non-Volatile: In some configurations, cache memory retains data for a
brief period even when the system is powered off (in the case of certain
types of cache like NVRAM).
4. Efficient: The cache is designed to hold frequently used data, which
improves overall efficiency and performance of the CPU.
5. Not All Data Cached: Not all data is stored in the cache; only data that
is frequently used or recently accessed is kept.
6. Exclusive: Cache memory is often exclusive to certain operations,
making data retrieval more efficient.
7. Encryption/Compression: Some caches apply encryption or
compression methods to secure or reduce the amount of data being
stored, enhancing performance.
8. Evolving Technology: Cache memory technologies continuously evolve
to address the increasing demands of processors, including larger and
faster cache designs.
9. Next-Level Performance: The ultimate goal of cache memory is to
achieve next-level performance by reducing the latency in fetching data.
Cache Coherence:
11. A Computer has 512 KB cache memory and 2 MB main memory. If the
block size is 64 bytes, then find out the subfield for
Subfields:
Tag: 2 bits
Index: 13 bits
Block offset: 6 bits
b. Associative Cache:
Subfields:
Tag: 15 bits
Block offset: 6 bits
c. 8-way Set Associative Cache:
Subfields:
Tag: 5 bits
Index: 10 bits
Block offset: 6 bits
12. A five-stage pipeline has stage delays as 150, 120, 160,130, and 140 ns
respectively. Registers are used between the stages, with a delay of 5 ns each.
Assuming a constant clocking rate, what will be the total time to process 1000
data items on the pipeline?
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