Sequential Logic Circuits:

Flip-Flops

By
Dr.Shwan Ch. Abdullah
 Contents

• Combinational circuits vs sequential circuits

• Types of latches and flip-flops

(SR, JK, D and T )

• Applications of flip-flops(examples)
 Combinational circuits

• Combinational logic
output depends on
the input levels of the
circuit.

• Example:
 Sequential circuits

• Sequential logic
output depends on
both current input
levels and past output
levels of a circuit.

• Example:
 Flip-Flops
A flip-flop is a bi-stable device: a circuit having 2
stable conditions (0 or 1).
The flip-flop stores one bit only (0 or 1)

• 3 classes of flip-flops
– Latches: outputs respond immediately while
enabled (no timing control)
– Level-triggered flip-flops: outputs responds to
the triggering level (pulse)
– Edge-triggered flip-flops: outputs response to
the triggering edge
 Conventions
• The circuit is set means output = 1
• The circuit is reset means output = 0
• Flip-flops have two output Q and Q’ or (Q
and Q)
• Due to time related characteristic of the flip-
flop, Q and Q’ (or Q) are usually represented
as followed:
– Qt or Q: present state
– Qt+1 or Q+: next state
 Level-Triggered Flip-Flops
These circuits respond to their inputs on either the
positive or negative Level of the clock.
 Edge-Triggered Flip-Flops
These circuits respond to their inputs on either the rising or falling
edge of the clock — a precise point in time rather than an interval.

Positive edge triggered Negative edge triggered

rising edge of clock falling edge of clock

D Q D Q
additional of a circle
wedge shows positive
means that there is
edge triggering
negative edge triggering
Q Q
 Types of Flip-Flops
SR Flip-Flops JK Flip-Flops
S R Qt+1 Q’t+1 J K Qt+1 Q’t+1

0 0 Qt Q’t 0 0 Qt Q’t

0 1 0 1 0 1 0 1

1 0 1 0 1 0 1 0

1 1 Prohibited 1 1 Q’t Qt

D Flip-Flops T Flip-Flops
D Qt+1 Q’t+1 T Qt+1 Q’t+1
0 0 1 0 Qt Q’t

1 1 0 1 Q’t Qt
 SR Latch
An SR (or Set-Reset) latch consists of
– S (Set) input: sets the circuit
– R (Reset) input: resets the circuit
– Q and Q’ output: output of the SR latch in normal and
complement form
Gated SR Flip-Flop
 SR Flip-Flop

Characteristics Table Truth Table

Excitation Table
 SR Flip-Flop

State diagram of SR flip-flop:

Gated D (Data) Flip-Flop

(a) (b)

(c)
 D Flip-Flop
Characteristics Table Truth Table

Excitation Table
 D flip-Flop

State diagram of D f/f:

 Gated JK Latch

(a) (b)

(c)
 JK Flip-Flop
Characteristics Table Truth Table

Excitation Table
 JK Flip-Flop

State diagram of JK f/f:

Gated T (Toggle) Latch

(b)
(a)

(c)
 T Flip-Flop
Characteristics Table Truth Table

Excitation Table
 T Flip-Flop

State diagram of T f/f:

 Asynchronous Inputs of the
Flip-Flop
PRESET (PRE) and CLEAR(CLR):
Asynchronous Inputs of the Flip-Flop
• The action of these inputs are as follows:

• PRE=CLR=1: Inputs are inactive, so the

synchronous inputs with clock determine the
state.

• PRE=0, CLR=1: Q=1 (set), regardless of clock,

J, K.

• PRE=1, CLR=0: Q=0 (cleared) regardless of

clock, J, K.

• PRE=CLR=0: Ambiguous state, to be avoided.

 Example: Time Diagram of Gated D
latch
D D Q
output remains constant:
C output follows input input ‘latched’ C

Q
Q

D D Q
output remains constant:
C' output follows input input ‘latched’ C

Q
Q
Example: Time Diagram of Edge-Triggered D
Flip-Flop

D Q
C

D Q

The input D can change at any time because it comes from other parts of the
system —it is not necessarily synchronized to the clock (it may be from a switch
on the front panel, for instance). However, the flip-flop only changes its output
when the clock pulse rises.
Example: Asynchronous Inputs of F/F

• EX: For the JK shown, determine

the output (Q).
Example: Asynchronous Inputs of F/F

• Solution:
 Applications of Flip-Flops

Flip-flops are used to design:

• Asynchronous Counters
• Synchronous Counters.
• Shift Registers
• Sequence detectors
• Finite State Machine
Any Questions ?