8086 microprocessor

Unit 1
Introduc on to microprocessor and microcomputer:
C:\Users\91885\OneDrive\Documents\8086 0.1

Microprocessor-Based Personal Computer

Systems
Microprocessor-Based Personal Computer Systems are the systems that
are built using microprocessors.

Fig.- Microprocessor Bassed Personal Computer System

There are four parts of microprocessor bussed system-

-Microprocessor Unit
-I/O Devices
-Memory
-System Bus

Microprocessor Unit
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microprocessor unit is the brain of the microprocessor bassed computer
systems. In This unit is the unit in which all the operations are performed.
Any type of command is run in this unit and gives us output. There are
many types of operations in a computer such as arithmetic operations,
logical. All these operations are performed in the microprocessor unit.
Operation and Decision Making Operation

Microprocessor unit has three segments-

1. Arithmetic and Logic Unit
2. Register Array
3. Control Unit

Arithmetic and Logic Unit

Different types of functions are performed in ALU. For example -

Arithmetic operation like addision, subtraction.
Logic operation like AND, OR, EX-OR etc.

Register Array

These register are primarily used to store data temporarily during the
execution of a program.

There are two types of registers -

1. User accesible - User Accesible Registers can be accessed by user
through instruction or program.
2. Internal - Internal Register can not be accessed by the user. These
register is used only by microprocessor.

Control Unit

A control unit (CU) is an integrated circuit in a processor that controls

inputs and outputs. It receives instructions from a program, then passes
them to the Arithmetic Logic Unit (ALU). The ALU performs the appropriate
calculations and sends the resulting values back to the control unit.

I/O(Input/Output) Unit

Microprocessor communicates with ouside world with help of I/O

(Input/Output) Devices.
These I/O (Input/Output) devices (including memory) are also known as
peripherals.
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The Input Devices such as keyboard switches, A/D converters, transfer
binary information (data and instruction) from the outside world to the
microprocessor.

The Output Devices transfer data from the microprocessor to the outside
world.
Output Devices - LEDs, CRT or video screen, D/A converter etc.

Memory Unit

Momory stores binary information such as instruction and data.

To execute programs, the microprocessor read instruction and data from
memory. Than microprocessor perfoms the computing operation in its ALU
section.
after execution results are either results are either transferred to the
output device for display or stored in the memory for later use.

There are two types of memory which are used -

1. ROM (Read-Only Memory)-
THe ROM is used to store programs that do not need alterations. For
example system programs, moniter programs etc. Programs stored in the
ROM can only be read, they cannot be altered.

2. Ram (Random-Access Memory) also known as Read/Write Memory

The Read/Write Memory is also known as user memory. it used to store
user programs and data.

System Bus

The bus which is a group of wires is one by which information is

transferred. All peripheral devices are connected to the microprocessor
through the bus.

There are three types of buses in a microprocessor:-

1. Address Bus
2. Data Bus
3. Control Bus
 8086 microprocessor
block diagram of microprocessor based personal computer system:

 The microprocessor is a semiconductor device (Integrated Circuit) manufactured

by the VLSI (Very Large Scale Integration) technique. It includes the ALU, register
arrays and control circuit on a single chip.
 A system designed using a microprocessor as its CPU is called a microcomputer.
The Microprocessor based system (single board microcomputer) consists of
microprocessor as CPU, semiconductor memories like EPROM and RAM, input
device, output device and interfacing devices.
 The memories, input device, output device and interfacing devices are called
peripherals. The popular input devices are keyboard and floppy disk and the
output devices are printer, LED/LCD displays, CRT monitor, etc.
 In the µP based system, the microprocessor is the master and all other peripherals
are slaves. The master controls all the peripherals and initiates all operations. The
work done by the processor can be classified into the following three groups.
 Work done internal to the processor
 Work done external to the processor
 Operations initiated by the slaves or peripherals.
 The work done internal to the processors are addition, subtraction, logical
operations, data transfer operations, etc.
 The work done external to the processor are reading/writing the memory and
reading/writing the I/O devices or the peripherals. If the peripheral requires the
attention of the master then it can interrupt the master and initiate an operation.
 The microprocessor is the master, which controls all the activities of the system. To
perform a specific job or task, the microprocessor has to execute a program stored
in memory. The program consists of a set of instructions. It issues address and
control signals and fetches the instruction and data from memory.
 8086 microprocessor
 BUSES:
The buses are group of lines that carries data, address or control signals.

 The CPU Bus has multiplexed lines, i.e., same line is used to carry different signals
 The CPU interface is provided to demultiplex, the multiplexed lines, to generate
chip select signals and additional control signals.
 The system bus has separate lines for each signal.
All the slaves in the system are connected to the same system bus. At any time
instant communication takes place between the master and one of the slaves.

PERIPHERAL DEVICES:

 The EPROM memory is used to store permanent programs and data.

 The RAM memory is used to store temporary programs and data.
 The input device is used to enter the program, data and to operate the system.
 The output device is used for examining the results.
Since the speed of I/O devices does not match with the speed of microprocessor,
an interface device is provided between system bus and I/O devices. Generally I/O
devices are slow devices.

modern computer memory map, I/O space

As a CPU needs to communicate with the various memory and input-

output devices (I/O) as we know data between the processor and
these devices flow with the help of the system bus. There are three
ways in which system bus can be allotted to them :
1. Separate set of address, control and data bus to I/O and memory.
2. Have common bus (data and address) for I/O and memory but
separate control lines.
3. Have common bus (data, address, and control) for I/O and
memory.
In first case it is simple because both have different set of address
space and instruction but require more buses.
 8086 microprocessor

Advantages of Memory-Mapped I/O:

Faster I/O Operations: Memory-mapped I/O allows the CPU to
access I/O devices at the same speed as it accesses memory. This
means that I/O operations can be performed much faster compared
to isolated I/O.
Simplified Programming: Memory-mapped I/O simplifies
programming as the same instructions can be used to access
memory and I/O devices. This means that software developers do not
have to use specialized I/O instructions, which can reduce
programming complexity.
Efficient Use of Memory Space: Memory-mapped I/O is more
memory-efficient as I/O devices share the same address space as
the memory. This means that the same memory address space can
be used to access both memory and I/O devices.
Disadvantages of Memory-Mapped I/O:
Limited I/O Address Space: Memory-mapped I/O limits the I/O
address space as I/O devices share the same address space as the
memory. This means that there may not be enough address space
available to address all I/O devices.
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Slower Response Time: If an I/O device is slow to respond, it can
delay the CPU’s access to memory. This can lead to slower overall
system performance.

Applications:
Memory-mapped I/O applications:
Graphics processing: Memory-mapped I/O is often used in graphics
cards to provide fast access to frame buffers and control registers.
The graphics data is mapped directly to memory, allowing the CPU to
read from and write to the graphics card as if it were accessing
regular memory.
Network communication: Network interface cards (NICs) often
utilize memory-mapped I/O to transfer data between the network and
the system memory. The NIC registers are mapped to specific
memory addresses, enabling efficient data transfer and control over
network operations.
Direct memory access (DMA): DMA controllers employ memory-
mapped I/O to facilitate high-speed data transfers between devices
and system memory without CPU intervention. By mapping the DMA
controller registers to memory, data can be transferred directly
between devices and memory, reducing CPU overhead.

Bus
Connection lines used to connect the internal parts of the
microprocessor chip is called bus. There are three types of buses
in a microprocessor −

 Data Bus − Lines that carry data to and from memory are
called data bus. It is a bidirectional bus with width equal to
word length of the microprocessor.
 Address Bus − It is a unidirectional responsible for carrying
address of a memory location or I/O port from CPU to
memory or I/O port.
 8086 microprocessor
 Control Bus − Lines that carry control signals like clock
signals, interrupt signal or ready signal are called control bus.
They are bidirectional. Signal that denotes that a device is
ready for processing is called ready signal. Signal that
indicates to a device to interrupt its process is called
an interrupt signal.

ASCII and UNICODE:

ASCII and UNICODE are the two most extensively used character encoding
schemes in computer systems. The most basic difference between ASCII and
UNICODE is that ASCII is used to represent text in form of symbols, numbers,
and character, whereas UNICODE is used to exchange, process, and store text
data in any language.

What is ASCII?
ASCII stands for American Standard Code for Information Interchange. It is a
standard developed for character encoding in electronic communication. ASCII
was first published in 1963. In computers and other electronic systems, it is
used for representing text as symbols, characters, and numbers.

In ASCII, each letter is assigned a particular value between 0 and 127. Thus,
ASCII can be used to represent 128 characters. Most computer systems use
ASCII encoding scheme that makes the interchange of data among different
devices simple.

The following table shows some of the symbols and their ASCII values.

Name Symbol ASCII Binary

Value Code

Null char NUL 0 00000000

Start of Heading SOH 1 00000001

Substitute SUB 26 00011010

Escape ESC 27 00011011

File Separator FS 28 00011100

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Group Separator GS 29 00011101

Record Separator RS 30 00011110

Unit Separator US 31 00011111

Space 32 00100000

Exclamation mark ! 33 00100001

Double quotes " 34 00100010

Number # 35 00100011

Dollar $ 36 00100100

Procenttecken % 37 00100101

Ampersand & 38 00100110

Single quote ' 39 00100111

Left parenthesis ( 40 00101000

Right parenthesis ) 41 00101001

Asterisk * 42 00101010

Plus + 43 00101011

Comma , 44 00101100

Hyphen - 45 00101101

Period or Dot or Full . 46 00101110

stop

Slash or divide / 47 00101111

Zero 0 48 00110000

One 1 49 00110001

Two 2 50 00110010

Eight 8 56 00111000
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Nine 9 57 00111001

Colon : 58 00111010

Semicolon ; 59 00111011

Less than < 60 00111100

Equals = 61 00111101

Greater than > 62 00111110

Question mark ? 63 00111111

At symbol @ 64 01000000

Uppercase A A 65 01000001

Uppercase B B 66 01000010

Uppercase C C 67 01000011

Uppercase D D 68 01000100

Uppercase X X 88 01011000

Uppercase Y Y 89 01011001

Uppercase Z Z 90 01011010

Opening square [ 91 01011011

bracket

Backslash \ 92 01011100

Closing square ] 93 01011101

bracket

Caret - circumflex ^ 94 01011110

Underscore _ 95 01011111

Grave accent ` 96 01100000

Lowercase a a 97 01100001

Lowercase b b 98 01100010
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Lowercase c c 99 01100011

Lowercase d d 100 01100100

Lowercase e e 101 01100101

Lowercase v v 118 01110110

Lowercase w w 119 01110111

Lowercase x x 120 01111000

Lowercase y y 121 01111001

Lowercase z z 122 01111010

Opening curly brace { 123 01111011

Vertical bar (Pipe) | 124 01111100

Closing curly brace } 125 01111101

Equivalency sign ~ 126 01111110

(tilde)

Delete 127 01111111

What is UNICODE?
UNICODE stands for Universal Character Set. UNICODE is an encoding scheme
whose standards are maintained by UNICODE Consortium. The greatest
advantage of UNICODE is that we can uniquely define every character in every
language by giving a different number.

UNICODE represents a wide range of characters, formulae, texts,

mathematical symbols, emojis, greek letters, etc. from different languages.
Therefore, UNICODE is the one of the most popular encoding scheme to encode
many of the globally used characters.

UNICODE encoding schemes are classified into several types depending on the
number of bits used. These UNICODE encoding schemes are UTF-7 (7-bit
encoding scheme), UTF-8 (8-bit encoding scheme), UTF-16 (16-bit encoding
scheme), and UTF-32 (32-bit encoding scheme). Here, UTF stands for
 8086 microprocessor
UNICODE Transformation Format, which is a type of UNICODE encoding
scheme.

The main objective of the use of UNICODE is localization and

internationalization of computer applications and software. UNICODE is also
used for programming of operating systems, java applications, XML, etc.

Difference Between ASCII and UNICODE

The following highlights all the important differences between ASCII and
UNICODE −

Parameter ASCII UNICODE

Full form ASCII stands for UNICODE stands

American for Universal
Standard Code for Character Set.
Information
Interchange.

Mutual ASCII is a subset UNICODE is a

Relationship of UNICODE superset of ASCII.
encoding scheme.

Supporting ASCII supports UNICODE supports

Characters only 128 a wide range of
characters using characters. It
7-bit encoding supports 154
scheme. It written scripts.
contains codes
representing
English
characters, digits,
and standard
special symbols.

Bits Per ASCII uses 7-bit UNICODE uses

Character or 8-bits mainly four
(Extended ASCII) character encoding
to represent schemes namely
different UTF-7 (7-bit),
characters. UTF-8 (8-bit),
 8086 microprocessor
UTF-16 (16-bit),
and UTF-32 (32-
bit).

Memory ASCII consumes UNICODE

Consumption less memory. consumes more
memory as
compared to
ASCII.

Characters ASCII can UNICODE can

Represented represent only represent a large
English letters, range characters,
digits, certain special symbols,
mathematical formulae, etc.
symbols, and from different
some grammatical languages such as
symbols, etc. English, Latin,
Greek, etc.

First Edition The first edition of The first edition of

Release ASCII was UNICODE was
released in 1963. released in 1991.

Applications ASCII encoding UNICODE is used

scheme is used in by IT industries for
computers and encoding and
other electronic character
devices for representation in
exchange of data. computers.
It is also used in
programming
languages like
HTML.

Conclusion
Both ASCII and UNICODE are the character encoding schemes used in
electronic communication. From the above comparison of ASCII and UNICODE,
we can state the most significant difference between them that is, ASCII is a
basic encoding scheme that represents 128 characters in 7-bit encoding,
whereas UNICODE is a vast ocean of text, numbers, mathematical symbols,
 8086 microprocessor
emojis, formulae, etc. that can be mapped in different bit sizes. However,
ASCII is a proper subset of UNICODE, hence UNICODE can represent all the
characters in ASCII.

BCD or Binary Coded Decimal

Binary Coded Decimal, or BCD, is another process for converting decimal

numbers into their binary equivalents.

 It is a form of binary encoding where each digit in a decimal number is

represented in the form of bits.
 This encoding can be done in either 4-bit or 8-bit (usually 4-bit is
preferred).
 It is a fast and efficient system that converts the decimal numbers into
binary numbers as compared to the existing binary system.
 These are generally used in digital displays where is the manipulation of
data is quite a task.
 Thus BCD plays an important role here because the manipulation is done
treating each digit as a separate single sub-circuit.

The BCD equivalent of a decimal number is written by replacing each decimal

digit in the integer and fractional parts with its four bit binary equivalent.the
BCD code is more precisely known as 8421 BCD code , with 8,4,2 and 1
representing the weights of different bits in the four-bit groups, Starting from
MSB and proceeding towards LSB. This feature makes it a weighted code ,
which means that each bit in the four bit group representing a given decimal
digit has an assigned weight.
Many decimal values, have an infinite place-value representation in binary but
have a finite place-value in binary-coded decimal. For example, 0.2 in binary
is .001100… and in BCD is 0.0010. It avoids fractional errors and is also used
in huge financial calculations.

Consider the following truth table and focus on how are these represented.

Truth Table for Binary Coded Decimal

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DECIMAL NUMBER BCD

0 0000

1 0001

2 0010

3 0011

4 0100

5 0101

6 0110

7 0111

8 1000

9 1001

In the BCD numbering system, the given decimal number is segregated into
chunks of four bits for each decimal digit within the number. Each decimal digit
is converted into its direct binary form (usually represented in 4-bits).

For example:

1. Convert (123)10 in BCD

From the truth table above,

1 -> 0001
2 -> 0010
3 -> 0011
 8086 microprocessor
thus, BCD becomes -> 0001 0010 0011

2. Convert (324)10 in BCD

(324)10 -> 0011 0010 0100 (BCD)

Again from the truth table above,

3 -> 0011
2 -> 0010
4 -> 0100
thus, BCD becomes -> 0011 0010 0100

This is how decimal numbers are converted to their equivalent BCDs.

 It is noticeable that the BCD is nothing more than a binary

representation of each digit of a decimal number.
 It cannot be ignored that the BCD representation of the given decimal
number uses extra bits, which makes it heavy-weighted.
 8086 microprocessor
Unit 2
Microprocessor and it’s architecture:

8086 internal architecture:

Introduction :
 The 8086 microprocessor is an 8-bit/16-bit
microprocessor designed by Intel in the late 1970s.
It is the first member of the x86 family of
microprocessors, which includes many popular
CPUs used in personal computers.
 The architecture of the 8086 microprocessor is
based on a complex instruction set computer
(CISC) architecture, which means that it supports a
wide range of instructions, many of which can
perform multiple operations in a single instruction.
The 8086 microprocessor has a 20-bit address bus,
which can address up to 1 MB of memory, and a
16-bit data bus, which can transfer data between
the microprocessor and memory or I/O devices.
 The 8086 microprocessor has a segmented
memory architecture, which means that memory is
divided into segments that are addressed using
both a segment register and an offset. The
segment register points to the start of a segment,
while the offset specifies the location of a specific
byte within the segment. This allows the 8086
microprocessor to access large amounts of
memory, while still using a 16-bit data bus.
 8086 microprocessor
 The 8086 microprocessor has two main execution
units: the execution unit (EU) and the bus interface
unit (BIU). The BIU is responsible for fetching
instructions from memory and decoding them, while
the EU executes the instructions. The BIU also
manages data transfer between the microprocessor
and memory or I/O devices.
 The 8086 microprocessor has a rich set of
registers, including general-purpose registers,
segment registers, and special registers. The
general-purpose registers can be used to store
data and perform arithmetic and logical operations,
while the segment registers are used to address
memory segments. The special registers include
the flags register, which stores status information
about the result of the previous operation, and the
instruction pointer (IP), which points to the next
instruction to be executed.
 A Microprocessor is an Integrated Circuit with all
the functions of a CPU. However, it cannot be used
stand-alone since unlike a microcontroller it has no
memory or peripherals.
 8086 does not have a RAM or ROM inside it.
However, it has internal registers for storing
intermediate and final results and interfaces with
memory located outside it through the System Bus.
 In the case of 8086, it is a 16-bit Integer
processor in a 40-pin, Dual Inline Packaged IC.
 8086 microprocessor
 The size of the internal registers(present within the
chip) indicates how much information the processor
can operate on at a time (in this case 16-bit
registers) and how it moves data around internally
within the chip, sometimes also referred to as the
internal data bus.
 8086 provides the programmer with 14 internal
registers, each of 16 bits or 2 bytes wide. The main
advantage of the 8086 microprocessor is that it
supports Pipelining.

 8086 Architecture
 Memory segmentation:
 In order to increase execution speed and fetching
speed, 8086 segments the memory.
 Its 20-bit address bus can address 1MB of
memory, it segments it into 16 64kB segments.
 8086 microprocessor
 8086 works only with four 64KB segments within
the whole 1MB memory.
 The internal architecture of Intel 8086 is divided
into 2 units: The Bus Interface Unit (BIU),
and The Execution Unit (EU). These are
explained as following below.
 1. The Bus Interface Unit (BIU):
 It provides the interface of 8086 to external memory
and I/O devices via the System Bus. It performs
various machine cycles such as memory read, I/O
read, etc. to transfer data between memory and I/O
devices.
 BIU performs the following functions are as follows:
 It generates the 20-bit physical address for memory
access.
 It fetches instructions from the memory.
 It transfers data to and from the memory and I/O.
 Maintains the 6-byte pre-fetch instruction
queue(supports pipelining).
 BIU mainly contains the 4 Segment registers,
the Instruction Pointer, a pre-fetch queue, and
an Address Generation Circuit.
 Instruction Pointer (IP):
 It is a 16-bit register. It holds offset of the next
instructions in the Code Segment.
 IP is incremented after every instruction byte is
fetched.
 IP gets a new value whenever a branch instruction
occurs.
 8086 microprocessor
 CS is multiplied by 10H to give the 20-bit physical
address of the Code Segment.
 The address of the next instruction is calculated by
using the formula CS x 10H + IP.
 Example:
 CS = 4321H IP = 1000H
 then CS x 10H = 43210H + offset = 44210H
 Here Offset = Instruction Pointer(IP)
 This is the address of the next instruction.
 Code Segment register: (16 Bit register): CS
holds the base address for the Code Segment. All
programs are stored in the Code Segment and
accessed via the IP.
 Data Segment register: (16 Bit register): DS
holds the base address for the Data Segment.
 Stack Segment register: (16 Bit register): SS
holds the base address for the Stack Segment.
 Extra Segment register: (16 Bit register): ES
holds the base address for the Extra Segment.
 Please note that segments are present in memory
and segment registers are present in
Microprocessor.
Segment registers store starting address of each
segments in memory.

 Address Generation Circuit:

 The BIU has a Physical Address Generation
Circuit.
 8086 microprocessor
 It generates the 20-bit physical address using
Segment and Offset addresses using the formula:
 In Bus Interface Unit (BIU) the circuit shown by the
Σ symbol is responsible for the calculation unit
which is used to calculate the physical address of
an instruction in memory.
 Physical Address = Segment Address x 10H +
Offset Address
 6 Byte Pre-fetch Queue:
 It is a 6-byte queue (FIFO).
 Fetching the next instruction (by BIU from CS)
while executing the current instruction is called
pipelining.
 Gets flushed whenever a branch instruction occurs.
 The pre-Fetch queue is of 6-Bytes only because
the maximum size of instruction that can have in
8086 is 6 bytes. Hence to cover up all operands
and data fields of maximum size instruction in 8086
Microprocessor there is a Pre-Fetch queue is 6
Bytes.
 The pre-Fetch queue is connected with the control
unit which is responsible for decoding op-code and
operands and telling the execution unit what to do
with the help of timing and control signals.
 The pre-Fetch queue is responsible for pipelining
and because of that 8086 microprocessor is called
fetch, decode, execute type microprocessor. Since
there are always instructions present for decoding
 8086 microprocessor
and execution in this queue the speed of execution
in the microprocessor is gradually increased.
 When there is a 2-byte space in the instruction
pre-fetch queue then only the next instruction
will be pushed into the queue otherwise if only a
1-byte space is vacant then there will not be any
allocation in the queue. It will wait for a spacing of 2
bytes in subsequent queue decoding operations.
 Instruction pre-fetch queue works in a sequential
manner so if there is any branch condition then in
that situation pre-fetch queue fails. Hence to avoid
chaos instruction queue is flushed out when any
branch or conditional jumps occur.
 2.prefetch unit:
 The Prefetch Unit in the 8086 microprocessor is a
component responsible for fetching instructions
from memory and storing them in a queue. The
prefetch unit allows the 8086 to perform multiple
instruction fetches in parallel, improving the overall
performance of the microprocessor.
 The prefetch unit consists of a buffer and a
program counter that are used to fetch instructions
from memory. The buffer stores the instructions
that have been fetched and the program counter
keeps track of the memory location of the next
instruction to be fetched. The prefetch unit fetches
several instructions ahead of the current
instruction, allowing the 8086 to execute
 8086 microprocessor
instructions from the buffer rather than from
memory.
 This parallel processing of instruction fetches helps
to reduce the wait time for memory access, as the
8086 can continue to execute instructions from the
buffer while it waits for memory access to
complete. This results in improved overall
performance, as the 8086 is able to execute more
instructions in a given amount of time.
 The prefetch unit is an important component of the
8086 microprocessor, as it allows the
microprocessor to work more efficiently and
perform more instructions in a given amount of
time. This improved performance helps to ensure
that the 8086 remains competitive in its
performance and capabilities, even as technology
continues to advance.
 3. The Execution Unit (EU):
 The main components of the EU are General
purpose registers, the ALU, Special purpose
registers, the Instruction Register and Instruction
Decoder, and the Flag/Status Register.
 Fetches instructions from the Queue in BIU,
decodes, and executes arithmetic and logic
operations using the ALU.
 Sends control signals for internal data transfer
operations within the microprocessor.(Control Unit)
 Sends request signals to the BIU to access the
external module.
 8086 microprocessor
 It operates with respect to T-states (clock cycles)
and not machine cycles.
 8086 has four 16-bit general purpose registers AX,
BX, CX, and DX which store intermediate values
during execution. Each of these has two 8-bit parts
(higher and lower).
 AX register: (Combination of AL and
AH Registers)
It holds operands and results during multiplication
and division operations. Also an accumulator
during String operations.

 BX register: (Combination of BL and

BH Registers)
It holds the memory address (offset address) in
indirect addressing modes.

 CX register: (Combination of CL and

CH Registers)
It holds the count for instructions like a loop,
rotates, shifts and string operations.

 DX register: (Combination of DL and

DH Registers)
It is used with AX to hold 32-bit values during
multiplication and division.

 Arithmetic Logic Unit (16-bit): Performs 8 and

16-bit arithmetic and logic operations.
 8086 microprocessor
 Special purpose registers (16-bit): Special
purpose registers are called Offset registers also.
Which points to specific memory locations under
each segment.
 We can understand the concept of segments as
Textbook pages. Suppose there are 10 chapters in
one textbook and each chapter takes exactly 100
pages. So the book will contain 1000 pages. Now
suppose we want to access page number 575 from
the book then 500 will be the segment base
address which can be anything in the context of
microprocessors like Code, Data, Stack, and Extra
Segment. So 500 will be segment registers that are
present in Bus Interface Unit (BIU). And 500 + 75 is
called an offset register through which we can
reach on specific page number under a specific
segment.
 Hence 500 is the segment base address and 75 is
an offset address or (Instruction Pointer, Stack
Pointer, Base Pointer, Source Index, Destination
Index) any of the above according to their segment
implementation.
 Stack Pointer: Points to Stack top. Stack is in
Stack Segment, used during instructions like
PUSH, POP, CALL, RET etc.
 Base Pointer: BP can hold the offset addresses of
any location in the stack segment. It is used to
access random locations of the stack.
 8086 microprocessor
 Source Index: It holds offset address in Data
Segment during string operations.
 Destination Index: It holds offset address in Extra
Segment during string operations.
 Instruction Register and Instruction Decoder:
 The EU fetches an opcode from the queue into the
instruction register. The instruction decoder
decodes it and sends the information to the control
circuit for execution.
 Flag/Status register (16 bits): It has 9 flags that
help change or recognize the state of the
microprocessor.
 6 Status flags:
 Carry flag(CF)
 Parity flag(PF)
 Auxiliary carry flag(AF)
 Zero flag(Z)
 Sign flag(S)
 Overflow flag (O)
 Status flags are updated after every arithmetic and
logic operation.
 3 Control flags:
 Trap flag(TF)
 Interrupt flag(IF)
 Direction flag(DF)
 These flags can be set or reset using control
instructions like CLC, STC, CLD, STD, CLI, STI,
etc. The Control flags are used to control certain
operations.
 8086 microprocessor
 4.Decode unit:
 The Decode Unit in the 8086 microprocessor is a
component that decodes the instructions that have
been fetched from memory. The decode unit takes
the machine code instructions and translates them
into micro-operations that can be executed by the
microprocessor’s execution unit.
 The Decode Unit works in parallel with the Prefetch
Unit, which fetches instructions from memory and
stores them in a queue. The Decode Unit reads the
instructions from the queue and translates them
into micro-operations that can be executed by the
microprocessor.
 The Decode Unit is an important component of the
8086 microprocessor, as it allows the
microprocessor to execute instructions efficiently
and accurately. The decode unit ensures that the
microprocessor can execute complex instructions,
such as jump instructions and loop instructions, by
translating them into a series of simple micro-
operations.
 The Decode Unit is responsible for decoding
instructions, performing register-to-register
operations, and performing memory-to-register
operations. It also decodes conditional jumps, calls,
and returns, and performs data transfers between
memory and registers.
 The Decode Unit helps to improve the performance
of the 8086 microprocessor by allowing it to
 8086 microprocessor
execute instructions quickly and accurately. This
improved performance helps to ensure that the
8086 remains competitive in its performance and
capabilities, even as technology continues to
advance.
 5.control unit :
 The Control Unit in the 8086 microprocessor is a
component that manages the overall operation of
the microprocessor. The control unit is responsible
for controlling the flow of instructions through the
microprocessor and coordinating the activities of
the other components, including the Decode Unit,
Execution Unit, and Prefetch Unit.
 The Control Unit acts as the central coordinator for
the microprocessor, directing the flow of data and
instructions and ensuring that the microprocessor
operates correctly. It also monitors the state of the
microprocessor, ensuring that the correct sequence
of operations is followed.
 The Control Unit is responsible for fetching
instructions from memory, decoding them,
executing them, and updating the microprocessor’s
state. It also handles interrupt requests and
performs system management tasks, such as
power management and error handling.
 The Control Unit is an essential component of the
8086 microprocessor, as it allows the
microprocessor to operate efficiently and
accurately. The control unit ensures that the
 8086 microprocessor
microprocessor can execute complex instructions,
such as jump instructions and loop instructions, by
coordinating the activities of the other components.
 The Control Unit helps to improve the performance
of the 8086 microprocessor by managing the flow
of instructions and data through the
microprocessor, ensuring that the microprocessor
operates correctly and efficiently. This improved
performance helps to ensure that the 8086 remains
competitive in its performance and capabilities,
even as technology continues to advance.
 The 8086 microprocessor uses three different
buses to transfer data and instructions between
the microprocessor and other components in a
computer system. These buses are:
 1.Address Bus: The address bus is used to send
the memory address of the instruction or data being
read or written. The address bus is 16 bits wide,
allowing the 8086 to address up to 64 kilobytes of
memory.
 2.Data Bus: The data bus is used to transfer data
between the microprocessor and memory. The
data bus is 16 bits wide, allowing the 8086 to
transfer 16-bit data words at a time.
 3.Control Bus: The control bus is used to transfer
control signals between the microprocessor and
other components in the computer system. The
control bus is used to send signals such as read,
write, and interrupt requests, and to transfer status
 8086 microprocessor
information between the microprocessor and other
components.
 The buses in the 8086 microprocessor play a
crucial role in allowing the microprocessor to
access and transfer data from memory, as well as
to interact with other components in the computer
system. The 8086’s ability to use these buses
efficiently and effectively helps to ensure that it
remains competitive in its performance and
capabilities, even as technology continues to
advance.
 Execution of whole 8086 Architecture:
 All instructions are stored in memory hence to fetch
any instruction first task is to obtain the Physical
address of the instruction is to be fetched. Hence
this task is done by Bus Interface Unit (BIU) and by
Segment Registers. Suppose the Code segment
has a Segment address and the Instruction pointer
has some offset address then the physical address
calculator circuit calculates the physical address in
which our instruction is to be fetched.
 After the address calculation instruction is fetched
from memory and it passes through C-Bus (Data
bus) as shown in the figure, and according to the
size of the instruction, the instruction pre-fetch
queue fills up. For example MOV AX, BX is 1 Byte
instruction so it will take only the 1st block of the
queue, and MOV BX,4050H is 3 Byte instruction
so it will take 3 blocks of the pre-fetch queue.
 8086 microprocessor
 When our instruction is ready for execution,
according to the FIFO property of the queue
instruction comes into the control system or control
circuit which resides in the Execution unit. Here
instruction decoding takes place. The decoding
control system generates an opcode that tells the
microprocessor unit which operation is to be
performed. So the control system sends signals all
over the microprocessor about what to perform and
what to extract from General and Special Purpose
Registers.
 Hence after decoding microprocessor fetches data
from GPR and according to instructions like ADD,
SUB, MUL, and DIV data residing in GPRs are
fetched and put as ALU’s input. and after that
addition, multiplication, division, or subtraction
whichever calculation is to be carried out.
 According to arithmetic, flag register values change
dynamically.
 While Instruction was decoding and executing
from step-3 of our algorithm, the Bus interface
Unit doesn’t remain idle. it continuously fetches
an instruction from memory and put it in a pre-
fetch queue and gets ready for execution in a
FIFO manner whenever the time arrives.
 So in this way, unlike the 8085 microprocessor,
here the fetch, decode, and execution process
happens in parallel and not sequentially. This is
called pipelining, and because of the instruction
 8086 microprocessor
pre-fetch queue, all fetching, decoding, and
execution process happen side-by-side. Hence
there is partitioning in 8086 architecture like Bus
Interface Unit and Execution Unit to support
Pipelining phenomena.
 Advantages of Architecture of 8086:
 The architecture of the 8086 microprocessor
provides several advantages, including:
 Wide range of instructions: The 8086
microprocessor supports a wide range of
instructions, allowing programmers to write
complex programs that can perform many different
operations.
 Segmented memory architecture: The segmented
memory architecture allows the 8086
microprocessor to address large amounts of
memory, up to 1 MB, while still using a 16-bit data
bus.
 Powerful instruction set: The instruction set of the
8086 microprocessor includes many powerful
instructions that can perform multiple operations in
a single instruction, reducing the number of
instructions needed to perform a given task.
 Multiple execution units: The 8086 microprocessor
has two main execution units, the execution unit
and the bus interface unit, which work together to
efficiently execute instructions and manage data
transfer.
 8086 microprocessor
 Rich set of registers: The 8086 microprocessor has
a rich set of registers, including general-purpose
registers, segment registers, and special registers,
allowing programmers to efficiently manipulate data
and control program flow.
 Backward compatibility: The architecture of the
8086 microprocessor is backward compatible with
earlier 8-bit microprocessors, allowing programs
written for these earlier microprocessors to be
easily ported to the 8086 microprocessor.
 Dis-advantages of Architecture of 8086:
 The architecture of the 8086 microprocessor has
some disadvantages, including:
 Complex programming: The architecture of the
8086 microprocessor is complex and can be
difficult to program, especially for novice
programmers who may not be familiar with the
assembly language programming required for the
8086 microprocessor.
 Segmented memory architecture: While the
segmented memory architecture allows the 8086
microprocessor to address a large amount of
memory, it can be difficult to program and manage,
as it requires programmers to use both segment
registers and offsets to address memory.
 Limited performance: The 8086 microprocessor
has a limited performance compared to modern
microprocessors, as it has a slower clock speed
and a limited number of execution units.
 8086 microprocessor
 Limited instruction set: While the 8086
microprocessor has a wide range of instructions, it
has a limited instruction set compared to modern
microprocessors, which can limit its functionality
and performance in certain applications.
 Limited memory addressing: The 8086
microprocessor can only address up to 1 MB of
memory, which can be limiting in applications that
require large amounts of memory.
 Lack of built-in features: The 8086 microprocessor
lacks some built-in features that are commonly
found in modern microprocessors, such as
hardware floating-point support and virtual memory
management.
Real Mode: (Memory addressing)
When the 80386 is turned on for the first time, the Real mode is its default operating
mode. Software created for the 8086 and 8088 processors will work on the 80386
without needing to be modified because it is fully backward-compatible with these
older CPUs. The 80386 has a 20-bit address space in Real mode, giving it access to
1MB of memory. The memory is separated into 64K segments, and a 16-bit segment
register can be used to access each section. The processor uses segment-based
memory addressing while operating in this mode and is not given access to
sophisticated memory management and security functions. Real mode likewise has a
constrained set of instructions and does not support protected or virtual memory.
Protected Mode:
A 32-bit address space is available in protected mode, a sophisticated operating mode
that gives users access to up to 4GB of memory. Additionally, it offers sophisticated
memory management and security features including segmentation and paging. Pages
are fixed-size units of memory that can be moved in and out of physical memory as
needed. Paging enables this. Memory can be separated into logical units called segments
through segmentation, which can be used to restrict access to particular memory
locations. The 80386 also has access to a number of privileged instructions and registers
in a protected mode that are not present in regular mode. The protected mode also
supports virtual memory which allows the system to use more memory than the physical
memory available by swapping memory pages to and from the disk.

Memory Segmenta on in 8086 Microprocessor

 8086 microprocessor

Segmenta on is the process in which the main memory of the

computer is logically divided into different segments and each
segment has its own base address. It is basically used to
enhance the speed of execu on of the computer system, so
that the processor is able to fetch and execute the data from
the memory easily and fast.
Need for Segmenta on –
The Bus Interface Unit (BIU) contains four 16 bit special
purpose registers (men oned below) called as Segment
Registers.
 Code segment register (CS): is used for addressing
memory loca on in the code segment of the memory,
where the executable program is stored.
 Data segment register (DS): points to the data segment
of the memory where the data is stored.
 Extra Segment Register (ES): also refers to a segment in
the memory which is another data segment in the
memory.
 Stack Segment Register (SS): is used for addressing stack
segment of the memory. The stack segment is that
segment of memory which is used to store stack data.
The number of address lines in 8086 is 20, 8086 BIU will send
20bit address, so as to access one of the 1MB memory
loca ons. The four segment registers actually contain the
upper 16 bits of the star ng addresses of the four memory
segments of 64 KB each with which the 8086 is working at that
instant of me. A segment is a logical unit of memory that may
be up to 64 kilobytes long. Each segment is made up of
 8086 microprocessor
con guous memory loca ons. It is an independent, separately
addressable unit. Star ng address will always be changing. It
will not be fixed.
Note that the 8086 does not work the whole 1MB memory at
any given me. However, it works only with four 64KB
segments within the whole 1MB memory.
Below is the one way of posi oning four 64 kilobyte segments
within the 1M byte memory space of an 8086.

Types Of Segmenta on –
1. Overlapping Segment – A segment starts at a par cular
address and its maximum size can go up to 64kilobytes.
But if another segment starts along with this 64kilobytes
loca on of the first segment, then the two are said to
be Overlapping Segment.
 8086 microprocessor
2. Non-Overlapped Segment – A segment starts at a
par cular address and its maximum size can go up to
64kilobytes. But if another segment starts before this
64kilobytes loca on of the first segment, then the two
segments are said to be Non-Overlapped Segment.
Rules of Segmenta on Segmenta on process follows some
rules as follows:
 The star ng address of a segment should be such that it
can be evenly divided by 16.
 Minimum size of a segment can be 16 bytes and the
maximum can be 64 kB.

Advantages of the Segmenta on The main advantages of

segmenta on are as follows:
 It provides a powerful memory management
mechanism.
 Data related or stack related opera ons can be
performed in different segments.
 Code related opera on can be done in separate code
segments.
 It allows to processes to easily share data.
 It allows to extend the address ability of the
processor, i.e. segmenta on allows the use of 16 bit
registers to give an addressing capability of 1
Megabytes. Without segmenta on, it would require
20 bit registers.
 8086 microprocessor
 It is possible to enhance the memory size of code
data or stack segments beyond 64 KB by allo ng
more than one segment for each area.
Pin diagram of 8086 microprocessor
Pin diagram of 8086 microprocessor is as given below:

Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40

pin DIP chip. It uses a 5V DC supply for its opera on. The 8086
uses a 20-line address bus. It has a 16-line data bus. The 20
lines of the address bus operate in mul plexed mode. The 16-
low order address bus lines have been mul plexed with data
and 4 high-order address bus lines have been mul plexed with
status signals.
 8086 microprocessor
AD0-AD15: Address/Data bus. These are low order address
bus. They are mul plexed with data. When AD lines are used
to transmit memory address the symbol A is used instead of
AD, for example A0-A15. When data are transmi ed over AD
lines the symbol D is used in place of AD, for example D0-D7,
D8-D15 or D0-D15.
A16-A19: High order address bus. These are mul plexed with
status signals.
S2, S1, S0: Status pins. These pins are ac ve during T4, T1 and
T2 states and is returned to passive state (1,1,1 during T3 or
Tw (when ready is inac ve). These are used by the 8288 bus
controller for genera ng all the memory and I/O opera on)
access control signals. Any change in S2, S1, S0 during T4
indicates the beginning of a bus cycle.

S2 S1 S0 Characteris cs

0 0 0 Interrupt acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory
 8086 microprocessor
S2 S1 S0 Characteris cs

1 1 1 Passive state

A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines

are mul plexed with corresponding status signals.

A17/S4 A16/S3 Func on

0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

HE’/S7: Bus High Enable/Status. During T1 it is low. It is used

to enable data onto the most significant half of data bus, D8-
D15. 8-bit device connected to upper half of the data bus use
BHE (Ac ve Low) signal. It is mul plexed with status signal S7.
S7 signal is available during T2, T3 and T4.
RD’: This is used for read opera on. It is an output signal. It is
ac ve when low.
READY : This is the acknowledgement from the memory or
slow device that they have completed the data transfer. The
signal made available by the devices is synchronized by the
8284A clock generator to provide ready input to the
microprocessor. The signal is ac ve high(1).
 8086 microprocessor
INTR : Interrupt Request. This is triggered input. This is
sampled during the last clock cycles of each instruc on for
determining the availability of the request. If any interrupt
request is found pending, the processor enters the interrupt
acknowledge cycle. This can be internally masked a er
resul ng the interrupt enable flag. This signal is ac ve high(1)
and has been synchronized internally.
NMI : Non maskable interrupt. This is an edge triggered input
which results in a type II interrupt. A subrou ne is then
vectored through an interrupt vector lookup table which is
located in the system memory. NMI is non-maskable internally
by so ware. A transi on made from low(0) to high(1) ini ates
the interrupt at the end of the current instruc on. This input
has been synchronized internally.
INTA : Interrupt acknowledge. It is ac ve low(0) during T2, T3
and Tw of each interrupt acknowledge cycle.
MN/MX’ : Minimum/Maximum. This pin signal indicates what
mode the processor will operate in.
RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by
local bus masters used to force the microprocessor to release
the local bus at the end of the microprocessor’s current bus
cycle. Each of the pin is bi-direc onal. RQ’/GT0′ have higher
priority than RQ’/GT1′.
LOCK’ : Its an ac ve low pin. It indicates that other system bus
masters have not been allowed to gain control of the system
bus while LOCK’ is ac ve low(0). The LOCK signal will be ac ve
un l the comple on of the next instruc on.
 8086 microprocessor
TEST’ : This examined by a ‘WAIT’ instruc on. If the TEST pin
goes low(0), execu on will con nue, else the processor
remains in an idle state. The input is internally synchronized
during each of the clock cycle on leading edge of the clock.
CLK : Clock Input. The clock input provides the basic ming for
processing opera on and bus control ac vity. Its an
asymmetric square wave with a 33% duty cycle.
RESET : This pin requires the microprocessor to terminate its
present ac vity immediately. The signal must be ac ve high(1)
for at least four clock cycles.
Vcc : Power Supply( +5V D.C.)
GND : Ground
QS1,QS0 : Queue Status. These signals indicate the status of
the internal 8086 instruc on queue according to the table
shown below:

QS1 QS0 Status

0 0 No opera on

0 1 First byte of op code from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

M/IO’: This signal is used to dis nguish between memory and

I/O opera ons. The M Signal is Ac ve high whereas the IO’
 8086 microprocessor
Signal is Ac ve Low. When this Pin is High, the memory
opera ons takes place. On the other hand, when the Pin is low,
the Input/Output opera ons from the peripheral devices takes
place.
=DT/R : Data Transmit/Receive. This pin is required in
minimum systems, that want to use an 8286 or 8287 data bus
transceiver. The direc on of data flow is controlled through the
transceiver.
DEN: Data enable. This pin is provided as an output enable for
the 8286/8287 in a minimum system which uses transceiver.
DEN is ac ve low(0) during each memory and input-output
access and for INTA cycles.
HOLD/HOLDA: HOLD indicates that another master has been
reques ng a local bus .This is an ac ve high(1). The
microprocessor receiving the HOLD request will issue HLDA
(high) as an acknowledgement in the middle of a T4 or T1 clock
cycle.
ALE : Address Latch Enable. ALE is provided by the
microprocessor to latch the address into the 8282 or 8283
address latch. It is an ac ve high(1) pulse during T1 of any bus
cycle. ALE signal is never floated, is always integer.
(In short)
The Intel 8086 microprocessor is a 16-bit HMOS CPU that
played a pivotal role in the development of personal
computers. Here's a breakdown of its pinout and pin func ons:
Power and Ground:
 8086 microprocessor
 Pin 1 & 20: VSS - Ground connec on (0V)
 Pin 40: VCC - Power supply (+5V)
Clock Signal:
 Pin 19: CLK - Clock input signal that synchronizes the
processor's opera ons. The frequency varies depending
on the model (e.g., 5MHz, 8MHz, 10MHz).
Address/Data Bus:
 Pin 2-16 & 39: AD0-AD15 - Mul plexed address/data bus.
o AD0-AD7: Lower order address lines (ac ve during

the first clock cycle of a memory or I/O opera on)

o AD8-AD15: Higher order address lines (ac ve during

the first clock cycle) or data lines (used for data

transfer a er the address phase)
High-Order Address/Status Lines:
 Pin 35-38: A16/S3-A19/S6 - These four lines provide the
highest order address bits (A16-A19) during the first clock
cycle of a memory opera on. They can also carry status
signals depending on the opera on being performed.
Control Signals:
 Pin 21: INTR - Interrupt request signal from external
devices.
 Pin 24: INTA - Interrupt acknowledge signal (output) sent
by the processor to the reques ng device. It's ac ve low.
 Pin 25: ALE - Address Latch Enable (output) indicates the
validity of the address on the address bus.
 8086 microprocessor
 Pin 26: DEN - Data Enable (output) controls the data
transceiver (external chip) to separate data from the
address/data bus.
 Pin 27: DT/R - Data Transmit/Receive (output) specifies
the direc on of data flow on the data bus (high for
output, low for input).
 Pin 32: RD - Read signal (output) indicates a read
opera on from memory or I/O devices.
 Pin 33: MN/MX - Minimum/Maximum mode select. This
pin configures the opera ng mode of the processor.
 Pin 34: BHE/S7 - Bus High Enable/Status 7 (output). This
signal enables the upper half of the data bus (AD15-AD8).
It can also carry a status signal.
Bus Control Signals:
 Pin 6, 12 & 18: GND - Addi onal ground connec ons
 Pin 9, 10, 11, 13, 14, 15 & 17: Not connected
 Pin 22: INTR - Interrupt acknowledge (input) (alterna ve
to pin 21)
 Pin 23: NMI - Non-Maskable Interrupt (input) - Highest
priority interrupt that cannot be disabled by so ware.
 Pin 28-31: RQ/GT - Request/Grant signals (bidirec onal)
used for local bus arbitra on between the 8086 and other
bus masters.
 Pin 37: LOCK - Lock signal (output) - Indicates that the
processor has exclusive control of the bus.

Unit 3
Addressing modes:
 8086 microprocessor
Data Addressing modes in 8086 microprocessor
Prerequisite – Addressing modes, Addressing modes in 8085 microprocessor
The way of specifying data to be operated by an instruc on is known
as addressing modes. This specifies that the given data is an immediate data or
an address. It also specifies whether the given operand is register or register
pair.
Types of addressing modes:
1. Register mode – In this type of addressing mode both the operands are
registers.
Example:
2. MOV AX, BX
3. XOR AX, DX
ADD AL, BL
4. Immediate mode – In this type of addressing mode the source operand
is a 8 bit or 16 bit data. Des na on operand can never be immediate
data.
Example:
5. MOV AX, 2000
6. MOV CL, 0A
7. ADD AL, 45
AND AX, 0000
Note that to ini alize the value of segment register an register is required.
MOV AX, 2000
MOV CS, AX
8. Displacement or direct mode – In this type of addressing mode the
effec ve address is directly given in the instruc on as displacement.
Example:
9. MOV AX, [DISP]
MOV AX, [0500]
 8086 microprocessor
10.Register indirect mode – In this addressing mode the effec ve address is
in SI, DI or BX.
Example: Physical Address = Segment Address + Effec ve Address
11.MOV AX, [DI]
12.ADD AL, [BX]
MOV AX, [SI]
13.Based indexed mode – In this the effec ve address is sum of base
register and index register.
14.Base register: BX, BP
Index register: SI, DI
The physical memory address is calculated according to the base register.
Example:
MOV AL, [BP+SI]
MOV AX, [BX+DI]
15.Indexed mode – In this type of addressing mode the effec ve address is
sum of index register and displacement.
Example:
16.MOV AX, [SI+2000]
MOV AL, [DI+3000]
17.Based mode – In this the effec ve address is the sum of base register
and displacement.
Example:
MOV AL, [BP+ 0100]
18.Based indexed displacement mode – In this type of addressing mode
the effec ve address is the sum of index register, base register and
displacement.
Example:
MOV AL, [SI+BP+2000]
19.String mode – This addressing mode is related to string instruc ons. In
this the value of SI and DI are auto incremented and decremented
 8086 microprocessor
depending upon the value of direc onal flag.
Example:
20.MOVS B
MOVS W
21.Input/Output mode – This addressing mode is related with input output
opera ons.
Example:
22.IN A, 45
OUT A, 50
23.Rela ve mode –
In this the effec ve address is calculated with reference to instruc on
pointer.
Example:
24.JNZ 8 bit address
IP=IP+8 bit address

Program Memory Addressing Mode

The program memory addressing mode is used in branch instructions. These
branch instructions are instructions which are responsible for changing the
regular flow of the instruction execution and shifting the control to some
other location. In 8086 microprocessor, these instructions are usually JMP and
CALL instructions.

Types of Program Memory Addressing Mode

The program memory addressing mode contains further three addressing
modes within it. They are:

1. Direct Program memory Addressing

2. Indirect Program memory Addressing
3. Relative Program memory Addressing

Let us study each of them in detail about their instructions and the way of
processing by the microprocessor while executing them.
 8086 microprocessor
1) Direct Program Memory Addressing
In this addressing mode, the offset address where the control is to be shifted
is defined within the instruction. This mode is called direct addressing mode
because the required address is directly present in the instruction rather than
being stored in some register.

Example:

JMP 4032H

Here, the working of the above instruction will be as follows:

The current value of IP which holds the address of next instruction to be

executed will be stored in the TOP OF THE STACK. Now, the IP will be
replaced by the mentioned value, i.e. IP <- 4032H

Now, the Memory address is calculated as: (Contents of CS) X 10H +

(contents of IP)

2) Indirect Program Addressing mode

As the name suggests, in this addressing mode, the offset address is not
present directly in the instruction. It is rather stored in any of the CPU registers
(Internal Register). So, the contents of the Instruction Pointer (IP) will be
replaced by the contents of that register.

Example:

JMP BX

Working:

Suppose that the content of the BX register is 0003H. So, the working of the
microprocessor for executing the above instruction will be as follows:

IP <- contents of BX
i.e. IP <- 0003H

And the required memory address is calculated in a similar way as in Direct

Addressing mode: (Contents of CS) X 10H + (contents of IP)
 8086 microprocessor
3) Relative Program Memory Addressing
In this Addressing mode, the offset address is equal to the content of the
Instruction Pointer (IP) plus the 8 or 16-bit displacement. For the 8 bit
displacement, SHORT is used and for 16-bit displacement, LONG is used. This
type of displacement will only be intra-segment, i.e. within the segment.

Example:

JMP SHORT OVER

Here, SHORT is used to represent the 8-bit displacement and OVER is the
Label defined for any particular memory location.

Stack memory addressing mode:

In computer architecture, stack memory addressing mode is a way for
instruc ons to reference operands (data to be operated on) that are located on
the stack. The stack is a special area of memory that behaves like a Last-In-First-
Out (LIFO) data structure.

Here's how it works:

 A register, called the Stack Pointer (SP), always keeps track of the top of
the stack (TOS).
 Instruc ons use the value in the SP as the base address for accessing data.
 There are typically two main instruc ons used with the stack:
o PUSH: This instruc on pushes data onto the stack, essen ally
decremen ng the SP and storing the data at the new TOS.
o POP: This instruc on retrieves data from the stack, incremen ng
the SP and returning the data that was previously at the TOS.

Benefits of stack addressing mode:

 Efficient func on calls: It simplifies func on calls by providing a

mechanism to store func on arguments, local variables, and the return
address.
 Interrupt handling: The stack is used to save the processor state when an
interrupt occurs, allowing the system to resume from where it le off a er
handling the interrupt.
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 Dynamic memory alloca on: Func ons can allocate memory on the fly by
pushing the desired size onto the stack and using the SP to access the
allocated memory.

Here are some addi onal points to consider:

 Stack addressing mode doesn't require specifying the full memory address
in the instruc on itself. It relies on the SP to determine the loca on.
 This mode is o en used in conjunc on with other addressing modes for
more complex memory access pa erns.
 8086 microprocessor
Unit 4
MOV revisited:
Opcode, short for opera on code, is the fundamental building block of a
machine language instruc on. It essen ally tells the processor what specific task
to perform.

Here's a deeper dive into opcodes:

 Func on: An opcode acts like a verb in a sentence, dicta ng the ac on the
processor needs to take. These ac ons can be basic arithme c opera ons
(add, subtract), logical opera ons (compare, test), data transfer, or control
flow (jumps, loops).
 Representa on: Opcodes are represented in binary code (0s and 1s) for
the processor to understand efficiently. For human readability, they might
also be shown in hexadecimal (base-16) format.
 Instruc on Set Architecture (ISA): Each processor has its own set of
opcodes defined by its Instruc on Set Architecture (ISA). This set
determines the available opera ons and the corresponding opcode for
each.
 Operands: Opcodes typically work together with operands, which specify
the data the instruc on operates on. Imagine the opcode as saying "add,"
and the operands telling the processor which numbers to add.
 Beyond CPUs: Opcodes aren't limited to CPUs. They are also used in
bytecode for so ware interpreters, where the bytecode is interpreted by
a virtual machine instead of a physical processor.
 8086 microprocessor
PUSH and POP in 8086 Assembly Language
The PUSH and POP instruc ons are fundamental for working with the stack in
8086 assembly language. Here's a breakdown of their func onality:

PUSH

 Pushes a value onto the stack.

 Decrements the Stack Pointer (SP) register by 2 (16-bit architecture).
 Copies the specified value onto the new top of the stack (memory loca on
pointed to by SP).

POP

 Retrieves a value from the stack.

 Increments the SP register by 2.
 Copies the value from the top of the stack (memory loca on pointed to by
SP) into the des na on register or memory loca on.

Key Points:

 The stack operates in a Last-In-First-Out (LIFO) manner.

 PUSH adds data, POP removes data.
 PUSH and POP maintain the stack pointer to keep track of the top element.

Common Uses:

 Saving registers: Before calling a subroutine or procedure that might modify

registers, you can PUSH them onto the stack to preserve their values. After
the subroutine execution, you can POP them back to restore the original
values.
 Passing arguments: Procedures can receive arguments by pushing them
onto the stack before the call.
 Temporary storage: You can use the stack for temporary storage of data
during calculations.
In 8086 assembly language, the stack itself doesn't require specific initialization in
machine language instructions. The stack works based on the Stack Pointer (SP)
register, which needs to be set before using PUSH and POP operations.

Here's why initialization isn't directly done in machine code:

 8086 microprocessor
 Stack is a Memory Segment: The stack resides in a designated memory
segment. You typically configure this memory allocation during program
setup, not with machine code instructions for PUSH and POP.
 Dynamic Growth: The stack grows and shrinks as you use PUSH and POP.
There's no fixed size to initialize.
However, you can initialize the SP register using machine code instructions like MOV.
Here's a basic example:
Code snippet
; Set stack segment register (optional, depends on your memory
allocation)
mov ss, segment_address ; segment_address is a defined label

; Set stack pointer register (SP) to a starting memory location within

the stack segment
mov sp, top_of_stack ; top_of_stack is a defined label for the
stack's highest address

This code sets the Stack Segment (SS) register (optional, depends on your memory
setup) and the SP register. SP points to the topmost usable location in the stack
(initially empty).

Now, you can use PUSH and POP instructions to manipulate data on the stack:

Code snippet
; Push a value onto the stack (example: value in register AX)
push ax

; Pop a value from the stack into register DX

pop dx

Remember, these are just basic examples. Stack management in assembly involves
understanding memory allocation, handling potential stack overflow/underflow
situations, and using PUSH and POP effectively in your program.

Data transfer instructions in 8086 microprocessor

Introduction :

Data transfer instructions in the 8086 microprocessor are used to move data
between memory locations, registers, and input/output (I/O) devices. These
 8086 microprocessor
instructions are essential for manipulating data within a program, as well as for
communicating with external devices.

Data transfer instructions are a fundamental part of programming in the 8086

microprocessor, and are used extensively in applications ranging from simple data
manipulation to complex I/O device communication and string processing.

Data transfer instructions are the instructions which transfers data in the
microprocessor. They are also called copy instructions.

OPCODE OPERAND EXPLANATION EXAMPLE

MOV D, S D=S MOV AX, [SI]

PUSH D pushes D to the stack PUSH DX

POP D pops the stack to D POP AS

PUSHA none put all the registers into the stack PUSHA

gets words from the stack to all

POPA none POPA
registers

XCHG [2050],
XCHG D, S exchanges contents of D and S
AX

IN D, S copies a byte or word from S to D IN AX, DX

OUT D, S copies a byte or word from D to S OUT 05, AL

translates a byte in AL using a table in

XLAT none XLAT
the memory
 8086 microprocessor
OPCODE OPERAND EXPLANATION EXAMPLE

loads AH with the lower byte of the

LAHF none LAHF
flag register

stores AH register to lower byte of the

SAHF none SAHF
flag register

copies the flag register at the top of

PUSHF none PUSHF
the stack

copies a word at the top of the stack

POPF none POPF
to the flag register

Here D stands for des na on and S stands for source.

D and S can either be register, data or memory address.

Arithme c instruc ons in 8086 microprocessor

Arithme c Instruc ons are the instruc ons which perform basic arithme c
opera ons such as addi on, subtrac on and a few more. Unlike in 8085
microprocessor, in 8086 microprocessor the des na on operand need not be
the accumulator.

Following is the table showing the list of arithme c instruc ons:

OPCODE OPERAND EXPLANATION EXAMPLE

ADD AX,
ADD D, S D=D+S
[2050]

ADC D, S D = D + S + prev. carry ADC AX, BX

SUB D, S D=D–S SUB AX, [SI]

 8086 microprocessor
OPCODE OPERAND EXPLANATION EXAMPLE

SBB [2050],
SBB D, S D = D – S – prev. carry
0050

MUL 8-bit register AX = AL * 8-bit reg. MUL BH

MUL 16-bit register DX AX = AX * 16-bit reg. MUL CX

8 or 16 bit
IMUL performs signed mul plica on IMUL CX
register

AX = AX / 8-bit reg. ; AL = quo ent

DIV 8-bit register DIV BL
; AH = remainder

DX AX / 16-bit reg. ; AX = quo ent

DIV 16-bit register DIV CX
; DX = remainder

8 or 16 bit
IDIV performs signed division IDIV BL
register

INC D D=D+1 INC AX

DEC D D=D–1 DEC [2050]

CBW none converts signed byte to word CBW

converts signed byte to double

CWD none CWD
word

NEG D D = 2’s compliment of D NEG AL

DAA none decimal adjust accumulator DAA

 8086 microprocessor
OPCODE OPERAND EXPLANATION EXAMPLE

decimal adjust accumulator a er

DAS none DAS
subtrac on

ASCII adjust accumulator a er

AAA none AAA
addi on

ASCII adjust accumulator a er

AAS none AAS
subtrac on

ASCII adjust accumulator a er

AAM none AAM
mul plica on

ASCII adjust accumulator a er

AAD none AAD
division

Here D stands for des na on and S stands for source.

D and S can either be register, data or memory address.