Tessent® Scan and ATPG

Lab
Debugging Simulation Mismatches

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 Table of Contents
Before you Begin ......................................................................................................4

Lab Debugging Simulation Mismatches ................................................................6

Exercise 1: Automated Debugging of Simulation Mismatches.............................7
Exercise 2: (Optional) Manual Simulation Mismatch Debug .............................12

Appendix: Answers to Questions ..........................................................................39

Exercise 1 .............................................................................................................39
Exercise 2 (Optional) ...........................................................................................41
 Before you Begin

If this is the first time you are launching this VM (Virtual Machine), you must
download and extract the lab data as described in the "Obtaining Lab Data
Caution
section below.

Whenever you are using the VM for lab exercises and are finished with your
session, please use the "Disconnect" feature of the Desktop Viewer before the
VM times out to preserve the data from one session to the next. Failure to do
so will remove the VM, and its contents.

If the VM was removed, you will be presented with a new VM requiring you
to follow the download and extract process. This allows you to "refresh" the
lab data so you can go through the labs again with a new database.

Setting Environment Variables

The environment uses bash and is ready to use for the labs with all needed
environment variables already setup.

Obtaining Lab Data

If the atpg_data directory, with lab subdirectories, is located in the home

directory (e.g. cd ~), please proceed to the lab exercises as you have already set
up the lab database on this VM.

If this is the first time you are starting a session for this VM, the atpg_data
directory will not be in the home directory and you will need to download and
extract it using the following instructions.

1. Double click on the Desktop icon Download_lab_data, . This launches a

web browser.

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 2. On the resulting web page, select the file named
tessent_atpg_data_v2020.1_20200611.tgz,

3. In the resultant window, select the Download button, enable the Save File
button, then select the OK button to download the file.

Move the file in the Downloads directory to the home directory. If you are using
the terminal (Applications>Favorites>Terminal) you can use the following
command:

mv ./Downloads/tessent_atpg_data_v2020.1_20200611.tgz .

4. In a terminal window, extract the files from the compressed tar file using the
command:

tar xzvf ./tessent_atpg_data_v2020.1_20200611.tgz

You should now have a directory named atpg_data in your $HOME directory.
That directory contains all the files you need to perform the exercises, in this
learning path.

You are now ready to proceed with lab exercises.

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 Lab
Debugging Simulation Mismatches

Introduction
In this lab, you learn to use the automated simulation mismatch tools in Tessent
Shell. You will then manually debug a simulation mismatch.

Objectives
Upon completing this lab, you should be able to:

 Run the automated simulation mismatch tools in Tessent Shell

 Use Tessent Visualizer and ModelSim to debug a simulation mismatch

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 Debugging Simulation Mismatches

Exercise 1: Automated Debugging of Simulation

Mismatches
In this exercise, you will debug simulation mismatches using the simulation
mismatch analysis flow and Tessent Visualizer.

You can analyze simulation mismatches either automatically or manually. In the

automatic flow, the command analyze_simulation_mismatches –auto is
executed. Refer to the section “Automatically Analyzing Simulation Mismatches”
in the Tessent Scan and ATPG User’s Manual for more information on this flow
and the manual flow. The automatic flow is used in this exercise to analyze
simulation mismatches.

Setup Instructions

1. Log in to your workstation if you are not already logged in.

2. Change to the $ATPG_LABS/Lab11/Exercise1 directory.
shell> cd $ATPG_LABS/Lab11/Exercise1

Creating and Simulating Test Patterns

The following steps and dofiles will guide you through the process of creating
test patterns and verifying them through simulation from within Tessent Shell.
There are several dofiles, which you will execute, which contain the commands
necessary to create the patterns and the associated Verilog testbenches for
verification.

3. Review the script generate_patterns_nomismatch. Notice that this script

calls the dofile solutions/setup_tessent_shell_nomismatch.do. Review
this dofile. Notice it performs the standard setups, creates, and writes

4. patterns in several different formats, including the Verilog test bench. It

also sets up the workspace for ModelSim and compiles the parallel test
bench for validation simulations.

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 Debugging Simulation Mismatches

5. Run the script generate_patterns_nomismatch.

The next step is to perform an analysis to see if there were any simulation
mismatches. During this step, the tool uses the Tessent Shell command,
analyze_simulation_mismatches –auto, to run the simulation mismatch
analysis. Also, the top-level design and Verilog library were compiled in the
work directory when the script in step 4 was run. ModelSim is the default
simulator used to perform the analysis.

The analyze_simulation_mismatches -auto and

report_mismatch_sources commands are found in the dofile,
solutions/debug_mismatch.do. If there are no simulation mismatches found,
the automatic simulation mismatch analysis stops and informs the user that
no mismatches were found.

6. Enter the following command:

ANALYSIS> dofile solutions/debug_mismatch.do

Question:
How many steps are automatically taken when the command
analyze_simulation_mismatches executed?
_____________
Are there any simulation mismatches? _____________

7. Exit Tessent Shell.

Generate and Debug a Simulation Mismatch

In this activity, you again save patterns and perform automatic analysis of
simulation mismatch. However, this time, the internal connections in the aoi22
library cell are changed to cause a simulation mismatch.

8. Review the script generate_patterns_mismatch. Notice that this script calls

the dofile solutions/setup_tessent_shell_mismatch.do. Review this dofile.

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 Debugging Simulation Mismatches

Notice it performs the standard setups, generates, and writes patterns. It also
sets up the workspace for ModelSim and compiles the parallel test bench for
validation simulations.

Question:
What is the one difference between this dofile and the one used for the
no mismatch run? ________________________________________

9. Run the script generate_patterns_mismatch.

10.Enter the following command:

ANALYSIS> dofile solutions/debug_mismatch.do

This time, analysis takes a while because there is a simulation mismatch.

When you examined the dofile, you may have noticed the
report_mismatch_sources command. The first instance tells the tool to
list all of the mismatch sources. These are displayed both in the transcript
tab of the Tessent Visualizer and in the shell window where you are running
the tool. The second instance tells the tool to load ID #1 of the reported
mismatches into the flat schematic tab of Tessent Visualizer.

What does report_mismatch_sources -all display? Look in the

Console window to find out.
_____________________________________________________________

What is causing simulation mismatches for ID #1? ____________________

_____________________________________________________________
Look at the information in the Transcript and Flat Schematic windows.
When you are finished.

Figure 11-1 Simulation Mismatch Source in Tessent Visualizer

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 Debugging Simulation Mismatches

Figure 11-2. Source of Mismatch Viewed in the Flat Schematic

11.Exit Tessent Shell

ANALYSIS> exit -f

12.Using a text editor of your choice, compare the two DFT library models and
the Verilog model located in $ATPG_LABS/libs.

adk.atpg adk.atpg_e

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 Debugging Simulation Mismatches

adk.v Verilog model:

What is the difference between the two DFT library models?

_____________________________________________________________

This concludes exercise1. Proceed to exercise2, time permitting.

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 Debugging Simulation Mismatches

Exercise 2: (Optional) Manual Simulation Mismatch

Debug

Introduction

The purpose of the lab exercise is to allow you to experience how to debug a
clock skew issue in a design. You will notice, depending on the amount of clock
skew and the hold requirement of the affected device, that this could also result in
a hold time violation due to the clock skew. For this exercise, the clock skew
issue was introduced for the purpose of demonstrating how to debug clock skew
issues in a parallel testbench.

Lab File Structure Overview

In order to allow you to focus on the debug flow and techniques for each lab
rather the Tessent and ModelSim statements, scripts have been provided with a
numerical prefix indicating the order in which they are to be run during the
exercise. These scripts will create patterns, write the patterns in ASCII format
and the Verilog test bench, save a flat model, and run the Verilog simulation test
bench. You will extract pertinent debug information for the mismatches from the
log files.

Once the mismatches have been identified from the log files, additional scripts
are provided to load the design and patterns back into Tessent Shell and
ModelSim so you can proceed with your debug effort.

Scripts and Files

You will first review the scripts and the directory structure. As you use the scripts,
and this structure, you should see how keeping data organized will help make the
start of your mismatch debug much easier.

How you choose to organize your data will depend on the internal processes used
at your home office.

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 Debugging Simulation Mismatches

1. Make Lab11/Exercise2 the current directory by executing the Linux cd

command and review the directory structure.

$ cd $ATPG_LABS/Lab11/Exercise2

2. Using your favorite text editor, review each of the scripts taking note of the
commands which perform the functionality described in the summaries below.

o 0.start: This script deletes any previous work that was done in the lab
directory and then run scripts for pattern generation (1.pattern_generation)
and Verilog simulation (2.verilog_simulation)

o 1.pattern_generation: This script invokes Tessent Shell, loads the design

and libraries, performs any required setup, generates patterns and writes
the files required for pattern validation and debugging simulation
mismatches. It also demonstrates the recommendation of writing the flat
model immediately after generating patterns to ensure design and pattern
file consistency.

o 2.verilog_simulation: This script compiles the Verilog testbench, libraries

and design netlist, then performs the pattern verification simulations saving
the results to a simulation logfile and waveform database.
o 3.debug_atpg: This script invokes Tessent Shell, loads the flat model and
reads the saved ASCII patterns.
o 4.debug_verilog: This script invokes ModelSim, reads in the waveform
database created during pattern validation, and runs an additional script
that pre populates some of the Mentor simulation debug information into
the waveform viewer.

o clean: A stand-alone utility that deletes any previous lab work.

Setting up for Debug and Directory Structures

You will now generate patterns using Tessent Shell and run pattern verification
using ModelSim. As you perform each step, you will also explore the directories

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 Debugging Simulation Mismatches

to find the source files, identify the files which are created, and the directories to
which they are written.

Pattern Generation
3. Execute the “clean” script to initialize the lab directory (e.g. delete files
generated by the scripts previously run, etc.).

$ clean

4. Explore the contents of the following directories:

o design: This directory contains the EDT inserted netlist, as well as SDF files
that can be applied to the netlist.

o edt: This directory contains the Tessent generated EDT “dofile” and test
procedure file that are to be used by Tessent Shell.
o libs: Contains the ATPG and simulation libraries.

o logs: Will contain the logfiles generated during the pattern creation, pattern
verification simulation, and debug sessions.

o sim: Currently contains a script that will add debug waveforms to the
ModelSim wave window. It will contain the Verilog testbench, the ASCII
pattern file and ATPG flat model.

5. Execute the generate patterns script to generate the patterns for the design.

$ 1.pattern_generation

Verify that the following files were created:

o logs/1.pattern_generation.log: This is one of the most important files used
for simulation mismatch debug.
Every time you invoke Tessent Shell, you should create a logfile of the
session. Without a logfile, there are many things you’ll have to do in order
Note to understand how the patterns were created, making the process a bit
cumbersome.

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 Debugging Simulation Mismatches

o sim/netlist.flat.gz: This is the flat model that was generated by Tessent Shell
command, set_system_mode analysis. While not required for
simulation mismatch debug, it allows the debug process to work much
faster since you do not have to setup the design and run DRCs.

You should always save a flat model at the same time you save patterns.

o sim/pat.ascii: These are the patterns that were generated and then saved in
the Tessent ASCII format. This file loads very quickly into Tessent Shell.
You can also choose to save a binary file, that contains the same information.
The binary version of the file is not human readable, and takes up much less
disk space. You would use the –binary argument in place of the –ascii.

o sim/pat.v – Verilog testbench.

o sim/pat.v.0.vec – These are the patterns that will be simulated.

o sim/pat.v.cfg - This file manages the .vec file(s).

Larger pattern sets will have multiple pat.v.<>.vec files. For example
pat.v.0.vec, pat.v.1.vec, pat.v.2.vec…

o sim/pat.v.chain.name - A HEX encoded file defining scan chains.

o sim/pat.v.po.name - A HEX encoded file defining the design primary
outputs.

Pattern Validation

You will now perform pattern validation using ModelSim.

6. Run the Verilog testbench that was created by Tessent Shell to determine if
there are any simulation mismatches.
$ 2.verilog_simulation

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 Debugging Simulation Mismatches

Beginning with ModelSim 10.7e, the -novopt switch has been

deprecated and is no longer a valid argument for the vsim
Note command. Usage results in an error and simulation run failure.

This class uses the -voptargs="+acc=npr" switch with the vsim

command. Scripts and dofiles written for pre 10.7e ModelSim
releases, using the -novopt argument, need to be updated by
replacing the -novopt switch with the -voptargs="+acc=npr".

See the ModelSim documentation and support.sw.siemens.com

for the latest details.
Notice that there are simulation mismatches being reported to the transcript. Also
notice that the file sim/verilog_simulation.wlf was created. We will use this
waveform database for debugging.

The next step is to start debugging the mismatches.

Simulation Mismatch Data Gathering

The following flow chart from the lecture outlines the process you will be
following for the remainder of this lab.

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 Debugging Simulation Mismatches

Figure 11-3. Manual Debug Process Steps

As with any debugging task, the best practice is to gather as much data about the
issue as possible, and record it in a logical manner. By taking the time gather and
record the information in one place, you will be able to determine many things
about the mismatch.

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 Debugging Simulation Mismatches

Figure 11-4. Sample blank Debug Table

The usage model for the tables is to complete the ATPG Information and the
Verilog Information sections using log files from your tool sessions you just
completed.

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 Debugging Simulation Mismatches

Extracting information from log files

7. Using your favorite text editor, open the file logs/1.pattern_generation.log and
complete the ATPG Information table.
How can you tell if the patterns were generated for an EDT design, or
bypass / FastScan design? ________________________________________

What command should you look for in the logfile to see if there are any
internally defined clocks or pins? __________________________________

C6, D1, K and T24 DRC violations will often cause simulation mismatches. We
suggest that in your pattern generation scripts, you add the command
report_drc_rules after set_system_mode analysis so you have one place
to look to see what DRC violations were reported.

Special tool setting is asking if the script set any of the tool settings that would
modify how the ATPG simulations run by default.

We suggest for clarity that you specify switches for write_patterns instead of
depending on default values for the command. Since simulation mismatch debug
is something you may not do every day, it’s much easier to have everything
documented in the logfile. This saves you time looking in the manual for the
command defaults.

We also suggest that if you add any simulation parameters to the Verilog
testbench, that those be added the command line, and not in a parameter file. The
contents of the parameter file are not captured to the log file.

Additionally, adhering to a file naming convention which allows one to quickly

identify the ASCII patterns and Verilog Testbench which are consistent with a
specific flattened model helps minimize the possibility of using a wrong pattern
set and/or test bench with a flattened model.

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 Debugging Simulation Mismatches

This lab was qualified using the Tessent 2020.1 and ModelSim
2020.2 releases.
Note

8. Open logs/2.verilog_simulation.log and complete the Verilog Information

portion of the table.

o The Verilog timing (sdfmin / sdfmax /...) will be specified in the

invocation script
o By generating a waveform file, debugging can be performed with a
viewer license instead of a full simulation license.

o Right before you see simulation results, the transcript will report the
name of the Verilog testbench. Make sure this name matches the name
that you extracted from the ATPG log.
o In general, if there is both a pin and cell showing as a mismatch location,
choose the cell.

o The time and cycle number reported is when the mismatch was observed.
As such, you will typically be looking in the prior pattern.

o Use the instance name that is reported in the logfile.

o You will not generally need the complete pathname for this table.

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 Debugging Simulation Mismatches

Figure 11-5. Portions of a ModelSim Logfile

For the purpose of this lab, you will explore the mismatch on chain3 at
1490nS. These entries have been pre-populated in the table for you.

Note
The portion of the table you just completed should look something like this:
(Remember, the failing times, pattern number, cell pathname,... may be different
for your design).

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 Debugging Simulation Mismatches

Figure 11-6. ATPG and Verilog Information

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 Debugging Simulation Mismatches

Setting up Tessent Shell for Debug

Refering back to figure 11-3 of this exercise, you will note that you have
completed steps 1 and 2 and are now progressing into step 3.
9. Run the script 3.debug_atpg. This invokes Tessent Shell, sets the context to
patterns -scan and reads the ASCII pattern file.
$ 3.debug_atpg

What pattern buffer does read_patterns place the patterns into:

Internal or External?____________________________________
The read_patterns command places the patterns into the external pattern
buffer. Be sure that when issuing commands to query or display these patterns,
you specify the external pattern buffer
10. Determining the pattern type and capture clock(s) for the mismatched pattern.
ANALYSIS> report_patterns -external -pattern_index 10

Keep in mind that the failing pattern number may be different, as

discussed previously.
Note

Figure 11-7. Report Pattern on Failing Pattern

What type of pattern is this pattern? _________________

What is the capture clock sequence? _________________

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 Debugging Simulation Mismatches

11.Display the failing scan cell in Tessent Visualizer using the command
report_scan_cells <chain_name> <cell_id> -display
ANALYSIS> report_scan_cell chain3 9 –display \

Keep in mind that the failing chain name and cell number may be
different, as discussed previously.
Note

Look at the Tessent Visualizer transcript and answer the following questions:

Figure 11-8. Report Scan Chain for Failing Cell

What is the name of the shift_clock? _____________________________

Is this clock reported in the capture clock sequence? _______________

If the clock names do not match verify you have the correct pattern number
and chainID / CellID. If you are confident about that information, you may
have set up a clock controller incorrectly. (Not the issue here).
Note
What is the instance name? ______________________________________
Does this match the name reported in the simulation logfile? ________
What are the scan chain connections for this scan chain? _____ and ____

12.In the Tessent Visualizer, show the ATPG pattern on the displayed scan cell by
selecting the Open Gate Report Settings dialog, , icon in the lower left of
the Tessent Visualizer window to open the Gate Report Settings dialog window,
select the Pattern Index, External and Scan test radio buttons, then enter the
pattern number, 10, as demonstrated in the following graphic.

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 Debugging Simulation Mismatches

Figure 11-9. Menu Selection to Display Pattern Data

Remember, the results of read_patterns loads patterns into the External
buffer. This pattern set is the Scan Test patterns.

Note

Keep the Tessent Visualizer window available as we set up ModelSim so we can

compare the ATPG expected and simulation results.

Setting Up ModelSim for Debug

1. Open a new terminal window and change to the Lab11/Exercise2 directory.

2. Run the script 4.debug_verilog to invoke the ModelSim wave reader, read in
the waveform database, and display a set of debug waveforms.
$ 4.debug_verilog &

Notice the added debug waveforms. These were added by the script,
sim/wave.do, that was called when the commands in the 4.debug_verilog script
invoked ModelSim.

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 Debugging Simulation Mismatches

These added waveforms include system clocks, procedures, pattern numbers,

cycle counts, and flags where simulation to expected value comparison is
performed, loading the parallel pattern, and releasing the parallel load.

3. You will now investigate the simulation results of the failing cell graphically
by adding the failing scan cell connections to the ModelSim wave window.
a. In the Tessent Visualizer, select the scan cell and open the pop up menu by
right clicking on select the scan cell, then copy the hierarchical instance
name by left-clicking on the last menu item (Copy name) to place the
name of the failing cell into the copy buffer.
Figure 11-10. Copy Instance Name

b. In ModelSim window, Left-click in the ModelSim

verilog_simulation_parallel - Default window, press Ctrl-F to open the
Find: box, located at the bottom-left of the window, then paste the name of
the cell copied from the Tessent Visualizer using the RMB pop-up menu or
Ctrl-v.

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 Debugging Simulation Mismatches

Figure 11-11. ModelSim Search Results

c. Double click on the resultant name (i.e. the grey string in Search results
pane) and the instance will be displayed and selected in the navigation
pane.
d. Drag and drop the instance into the Wave window to add the input/output
waveforms of the scan cell to the waveform window.

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 Debugging Simulation Mismatches

Figure 11-12. ModelSim Setup

e. To complete the initial setup for debug, add a cursor to the waveform
window at the time that the mismatch was reported. Cursor management is
located under the list of displayed signals. You can also add them, zoom on
a cursor, between two cursors, etc. using the toolbar icons. Grey time
indicates delta t between the cursors.

Figure 11-13. Cursor Management Area

f. Cursor 1 is automatically displayed. Right-click on the time to activate it

for editing, type in 1490ns (your mismatch time may be different), press
Enter, then lock the cursor in this location, by clicking the the “lock” icon
(it will have a red background when it is locked once the cursor is moved).

g. Zoom in to the cursor location and verify that the cursor is also located
during the reported failing cycle. Remember, in our current example, we
have specified the first for which a mismatch is reported for chain3, which
occurred in cycle 37 (actual cycle number can be software release
dependent). Your screen should resemble that of Figure 11-14.

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 Debugging Simulation Mismatches

Figure 11-14. ModelSim Setup Complete; Highlighting Compare Event

Remember, the failing time and cycle number are reported at the “compare
simulated to expected value” event. This compare happens during the Load
procedure for the pattern after the failing pattern, for example, 11 when we
Note are looking at 10.

Debugging the Simulation Mismatch

You have just set up a debug environment which includes the following:
o Compressed patterns (TestKompress design)
o Parallel testbench

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 Debugging Simulation Mismatches

o Scan test
o Tessent Visualizer displaying the failing cell and the ATPG pattern
o ModelSim displaying the time the mismatch was recorded and the
connections to the failing cell.

Referencing Figure 11-3, we see the next step is to determine if the mismatch
occurred during parallel shift or Capture.

Looking at Figure 11-15, you’ll see some debug suggestions. Notice that this
specifies that, based on the data you entered, there is an issue with parallel shift
or capture, and the mismatch is occurring at the reported failing cell.

Figure 11-15. Debug Suggestions

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 Debugging Simulation Mismatches

Determining if Failure is in Parallel Shift

First, we need to ensure the parallel data loaded was shifted correctly. In order to
determine if the mismatch occurred during parallel shift, you will need to verify
that the shift values match between ATPG and ModelSim.

4. Verifying the shift values in ModelSim.

a. Add another cursor at the transition between SHIFT and

LAUNCH_CAPTURE during pattern 10.

b. Zoom in, and move the cursor so it is just to the right of the parallel pattern
release, indicated by the event release_frc_chain1_sibus icon, .

5. Compare the ATPG first clock frame of the first capture cycle to the simulation
value right after the parallel load release event.

ATPG Simulation
D ___________ ___________
CLK ___________ ___________
QB ___________ ___________

You will find it easier to acquire the correct clock frame values in the
ModelSim Wave viewer by doing two things.
Hint 1) Reorder the waveforms using the “drag and drop” in the Wave panel
containing the part-pin numbers such that they are in the same order
as the tables.
2) Declutter the viewer by deleting the signals which are not of concern.
Here, SI, SE, R and Q are not needed.

We see from the table that the ATPG and simulation values for the first clock
frame for all three pins match. This tells us the mismatch did not occur due to a
problem in the parallel shift procedure.

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 Debugging Simulation Mismatches

Failure During Capture

Since the simulated and expected values for the parallel shift match, the source of
the mismatch must be during capture.

Just as a quick review, the three clock frames seen in the Tessent Visualizer are
the values after parallel load, after the leading edge of the capture clock, and after
the trailing edge of the capture clock.

The following graphic exemplifies the three clock frames.

Figure 11-16. Capture Clock Frame Defined

Value after
Leading
Value after edge
Value after
parallel load trailing edge

D 0 1 1

6. Move your cursor until it is right before the clock pulse during
LAUNCH_CAPTURE.

What system-level clock is driving the scan cell clock? ______

Is it the same clock reported as the capture_clock_sequence for this pattern?

______
7. Document all three clock frames of the first capture cycle for both the ATPG
and simulation for the connections to the scan cell.

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 Debugging Simulation Mismatches

ATPG Simulation
D ___________ ___________
CLK ___________ ___________
QB ___________ ___________

Figure 11-17. Capture Verification; chain3, cell 9, Pattern 10

It appears there are two mismatches, one at the D input (100 vs 000), which would
be shift issue, and the QB output (100 vs 111). We have already confirmed that
the issue is a capture issue, not a shift issue.

This being the case, let’s examine the timing relationship of the D input and the
clocks, clk1 and the clk at the register input.

Determining Cause of Simulation Mismatch.

During the lecture, the causes of mismatches were discussed. It was stated that
the majority of mismatch issues are caused by timing issues with Timing
representing about 60% of the mismatch issues.

You might have noticed that in simulation in the second clock frame, the data (D)
changed but, QB did not change. This could be a clock skew issue.

8. Investigate this to see if there is a clock skew issue in the design.

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 Debugging Simulation Mismatches

a. Drag and drop /clk1 so it is either above the D pin of the failing cell as this
will make any clock skew issue more obvious.

b. Move the cursor to the rising edge of /clk1, during the

LAUNCH_CAPTURE procedure of pattern 10.

c. Zoom in such that you can see any time differences between signal edges
transitioning at about the same time.

d. Notice this sequence of events:

i. /clk1 goes active

ii. D changes state to 0
iii. Then reg_sum_0_ix9/CLK goes active

iv. QB remains 1 (and causes the mismatch).

Skew between clk1

register clk pin

Delayed clock at register pin

fails to capture state at D

Figure 11-18. Identifying the Clock Skew Issue

If there were no clock skew issues, D = 0 in the first clock frame would have
been captured, and QB would be equal to 1.
The skew between clocks is longer than it should be.

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 Debugging Simulation Mismatches

Determining the Source of the Skew

Now that a skew has been identified, let’s take a look at what is causing the skew
using the Tessent Visualizer to identify the instances involved and the ModelSim
Wave viewer to view the simulated delays. Both these windows should still be
open from earlier in the exercise. If not, issue the Tessent Shell command
report_scan_cell chain1 1 -display, then add the pattern index data for pattern 17
using the Data menu to open, and setup the visualizer. Execute the
4.verilog_debug script to relaunch ModelSim.

9. Trace back from the CLK pin to the /clk1 instance by clicking on the CLK pin
of reg_sum_0_ix9, then on one of the “diamonds” with a plus sign to reveal the
two inverters.

Figure 11-19. Tracing the Clock

10. Add the instances of the two inverters to the ModelSim wave viewer and
organize them such that they have the same order as the visualizer schematic.

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 Debugging Simulation Mismatches

Figure 11-20. Viewing the Clock Path

Zero
Delay
300pS
Delay

We can see, in this case, that there is no delay through the ix210 inverter and a
rather large delay through the ix216 inverter. To further investigate, we will need
to open the SDF file which was loaded for the design.
11. Open the SDF file, design/netlist.sdf in a text editor of your choice.
a. Search for top_design_i/block1/ix210, taking note that there is no entry.
As such, a zero delay is assigned to that instance.
b. Search for top_design_i/block1/ix216, taking note the entry has a 300 pS
delay assigned to it.

c. Peruse several other instances, taking note that the delays assigned to these
elements are only 100 pS.

We now see that the delay assigned to instance top_design_i/block1/ix216 is 3

times the delay assigned to the other instances in the design, which actually have
delays assigned.

If a proper SDF file was used for this design with the proper delays assigned to
the instances, you would follow the same process of tracing back looking for the
offending instance, or instances, to determine if the skew was introduced
structurally or some other mechanism.

12.Exit Tessent Shell and ModelSim.

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 Debugging Simulation Mismatches

Review
 List the steps you would take to troubleshoot areas of low coverage
Setup Tessent shell and your design and libraries

Identify Black Box Undefined Modules

Examine ATPG Untestable (AU) faults statistically and graphically

Debug Controllability and Observability issues

Again debug additional DRC rule violations

Debug the design netlist

Run ATPG and compare results for improvement in test coverage

 What are some of the things that cause low coverage?

Black boxes and undefined modules

ATPG untestable (AU) faults

Observability and controllability issues for a fault at a site/cell/gate

Incomplete netlist definitions/missing modules definitions in designs etc.

 What command do you use to analyze faults?

analyze_fault <pin_pathname> <-stuck_at {0|1} | -Rise | -Fall> -display

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 Debugging Simulation Mismatches

 What are some potential causes of simulation mismatches? (Hint: Refer to

“Potential Causes of Simulation Mismatches” in the Tessent Scan and ATPG
User’s Manual.)

DRC Issues

Shadow Cells

Library Problems

Timing Violations

 What command is used to automatically analyze simulation mismatches?

analyze_simulation_mismatches –auto

 What command is used when to graphically display mismatch sources?

report_mismatch_sources -all –display
This is the end of exercise2 and Lab 11.

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Tessent Scan and ATPG – Lab Answers

Appendix: Answers to Questions

These labs were qualified using Tessent 2020.1 and ModelSim 2020.2, if
other Tessent versions were used, results contained in tables in these labs
Note may differ slightly from those shown in this Lab Answers section.

Exercise 1

Create and Simulate Test Patterns

Step 5
 How many steps are automatically taken when the command
analyze_simulation_mismatches executed?

Seven steps were executed.

 Are there any simulation mismatches?

No

Generate and Debug a Simulation Mismatch

Step 7
What is the one difference between this dofile and the one used for the no
mismatch run?

The ATPG library used. The library used for the mismatch is
adk.atpg_e, for “error” which we inserted for demonstration
purposes.

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Tessent Scan and ATPG – Lab Answers

Step 9
What does report_mismatch_sources -all display? Look in the Console
window to find out.

Displays/reports all instance and their gate IDs with the mismatch
and the reason for the mismatch

What is causing simulation mismatches for ID #1?

Incorrect library cell "aoi22" is causing the mismatch

Step 11
What is the difference between the two DFT library models?

The difference between two DFT library models is that: ‘adk.atpg’:

defines input B1 to be a input of the primitive gate that defines the
cell “aoi22” and hence avoiding mismatch however ‘adk.atpg_e’:
ignores B1 or does not consider it as input to primitive gates that
defines the cell “aoi22”. Hence it leads to the mismatch or even
error in the data/waveform.

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Tessent Scan and ATPG – Lab Answers

Exercise 2 (Optional)

Lab11; Ex2
File Locations

Debug files ATPG log file logs/1.pattern_generation.log

Verilog simulation log file logs/2.verilog_simulation.log

flattened design sim/netlist.flat.gz

ASCII/binary pattern sim/pat.ascii

waveform database sim/verilog_simulation.wlf

ATPG Information

ATPG log compressed or bypass? Compressed

internal pins/clocks No

DRC (C6/D1/K/T24) No

special tool settings No

Verilog pattern name sim/pat.v

chain test or scan test scan test

parallel or serial Parallel

PRE shift number 0

POST shift number 0

ASCII/binary pattern sim/pat.ascii

flattened design sim/netlist.flat.gz

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Tessent Scan and ATPG – Lab Answers

Verilog Information

Verilog log timing sdfmax

waveform database sim/verilog_simulation.wlf

Verilog pattern name sim/pat.v

pin/cell Cell

Time / cycle 1490/37

pattern number 10

chain name chain3

cell number 9

pin pathname /top_design_i/block1/reg_sum_0_ix9.QB

Simulated/Expected 1/0

Extracting information from log files

Step 7
How can you tell if the patterns were generated for an EDT design, or
bypass / FastScan design?

Two ways:
1. From the command “set_edt_instances -edt..”

2. During the system mode, set to analysis/[run DRC] due to

presence of EDT logic, there is a EDT pattern generation phase

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Tessent Scan and ATPG – Lab Answers

What command should you look for in the logfile to see if there are any
internally defined clocks or pins?

Look for the add_clocks command in the logfile for internally

defined clocks or pins.

Setting up Tessent Shell for Debug

Step 9
What pattern buffer does read_patterns place the patterns into: Internal or
External?

The read_patterns command places patterns in the External buffer.

Step 10
What type of pattern is this pattern?

The pattern is a clock sequential pattern.

What is the capture clock sequence?

[clk1][clk2]

Step 11
What is the name of the shift_clock?

clk1
Is this the same clock that was reported for the capture clock sequence?

Yes
What is the instance name of the scan cell?

/top_design_i/block1/reg_sum_0_ix9
Does this match the name reported in the simulation logfile?

Yes

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Tessent Scan and ATPG – Lab Answers

What are the scan chain connections for this scan chain?
SI and QB

Determining if failure is in Parallel Shift

Step 5
ATPG Simulation
D 1 1
CLK 0 0
QB 1 1

Failure during Capture

Step 6
What system-level clock is driving the scan cell clock?

clk1
Is it the same clock reported as the capture_clock_sequence for this pattern?

Yes.

Step 7
ATPG Simulation
D 100 000
CLK 010 010
QB 100 111

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