DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION

UNIT 5

1. What is meant by address mapping?

The correspondence between the main memory blocks and those in the cache is specified by
address mapping. There are three commonly used methods to translate main memory addresses to cache
memory addresses. They are:
 Direct mapping
 Associative mapping
 Set-associative mapping
2. What is cache memory?
A Cache memory is a small and very fast temporary storage memory. It is designed to speed up
the transfer of data and instructions. It is faster than RAM and the data/instructions that are most
recently or most frequently used by CPU are stored in cache.
3. Define memory hierarchy.
In computer architecture, the memory hierarchy separates computer storage into a hierarchy
based on response time. Since response time, complexity, and capacity are related, the levels may also
be distinguished by their performance and controlling technologies.

4. State the advantages of virtual memory.

 Virtual memory allows processes whose aggregate memory requirement is greater than
the amount of physical memory, as infrequently used pages can reside on the disk
 Virtual memory allows speed gain when only a particular segment of the program is required
for the execution of the program
 It is very helpful in implementing multiprogramming environment.

5. What are the various memory technologies?

 SRAM (Static Random Access Memory)
 DRAM (Dynamic Random Access Memory)
 ROM (Read Only Memory)
 Flash Memory
 Magnetic Disk
 6. Point out how DMA can improve I/O speed.
DMA allow the peripherals to directly communicate with each other using the memory buses,
removing the intervention of the CPU. During DMA the CPU is idle and it has no control over the
memory buses. So, the DMA controller takes control over the buses to manage the transfer directly
between the I/O devices and the memory unit for improving the speed.

7. Define memory interleaving.

Memory interleaving is the technique used to increase the throughput. The memory system is
split into independent banks, which can answer read or write requests independents in parallel. There are
two- address format for memory interleaving the address space. They are:
 Low order interleaving
 High order interleaving
8. Summarize the sequence of events involved in handling an interrupt request from a
single device.
 The device raises an interrupt request.
 The processor interrupts the program currently being executed.
 Interrupts are disabled by changing the control bits in the Processor Status Register.
 The device is informed that its request has been recognized, and in response, it deactivates
the interrupt-request signal.
 The action requested by the interrupt is performed by the interrupt-service routine.
 Interrupts are enabled and execution of the interrupted program is resumed.

10. What is the purpose of dirty/modified bit in cache memory?

A dirty bit or modified bit is a bit that is associated with a block of computer memory and
indicates whether or not the corresponding block of memory has been modified. Dirty bits are used by
the CPU cache and in the page replacement algorithms of an operating system.

11. What is virtual memory?

Virtual memory is a memory management technique that is implemented using both hardware
and software and it uses main memory as a cache for secondary storage. Techniques that automatically
move program and data blocks into the physical main memory when they are required for execution are
called virtual memory techniques.

12. How many total bits are required for a direct mapped cache with 16KB of data and 4-word
blocks, assuming a 32bit address?
No. of cache lines= data memory size of cache /data size of 1 cache line
12
= 16KB/4B = 16x1024/4 = 4096 = 2 lines
12
No. of bits needed to represent cache line = log2 (2 ) = 12
bits No. of bits needed to represent a word in a line = log24 =
2 bits No. of bits needed for tag = 32-12-2 = 18 bits
12
Size of tag memory = No. of tag bits * No. of lines = 18 * 2 bits = 72K
bits Size of data memory = 16 KB = 16 x 8 = 128K bits
Total memory needed for cache = 128 K bits + 72K bits = 200Kbits

13. Define hit ratio.

The hit ratio is the fraction of accesses which are a hit. The miss ratio is the fraction of accesses
which are a miss. It holds that miss rate = 1 − hit rate. The (hit/miss) latency (also known as access time)
is the time it takes to fetch the data in case of a hit/miss.
14. Define hit rate and miss rate.
The fraction of memory accesses found in a level of the memory hierarchy is called hit rate. The
fraction of memory accesses not found in a level of the memory hierarchy is called miss rate.
15. What is TLB?
Translation Look-aside Buffer (TLB) is a cache that keeps track of recently used address
mapping which tries to avoid an access to the page table.
16. What are the methods used to improving cache performance?
There are two different techniques available for improving cache performance:
 Reducing the miss penalty by adding an additional level to the hierarchy.
 Reducing the miss rate by reducing the probability that two different memory blocks
will content for the same cache location.

17. Define interrupts.

Interrupt is a process that causes a CPU to temporarily transfer control from its current program
to another program. It improves the computer’s IO performance.

18. What are the two I/O interfacing techniques?

The two I/O interfacing techniques are
 Memory mapped I/O
 I/O mapped I/O

19. Mention the various TYPES of Pipelining.

The various types of pipelining are
 Instruction pipeline
 Operation pipeline
 Multi-issue pipeline
20. Mention the various phase in executing an
instruction.
The various phases in executing an instruction are
 Fetch
 Decode
 Execute
 Memory Access
 Write Back

21. What is meant by pipeline bubble?

Pipeline bubble or pipeline stall is a delay in execution of an instruction which occurs in an
instruction pipeline inorder to resolve a hazard. A bubble is represented in the execution stage as a
NOP instruction, which has no effect other than to stall the instructions being executed in the
pipeline.

22. What is a data path?

A datapath is a collection of functional units such as arithmetic logic units or multipliers that
perform dataprocessing operations, registers, and buses. It composes the central processing unit
(CPU) along with the control unit.
23. What are the advantages of pipelining?
The cycle time of the processor is reduced and it increases the instruction throughput.
If pipelining is used, the CPU arithmetic logic unit can be designed faster.

24. What is exception?

Exceptions are internally generated unscheduled events that disrupt program execution and
they
are used to detect overflow. Examples for exception are arithmetic overflow, invoking the
operating system from user program and using an undefined instruction.

25. What is a hazard? What are its types?

Any situation that prevents the next instruction in the instruction stream from executing
during its designated cycle is called a hazard. Various types of hazard are: Structural hazard, Data
hazard and Control hazard.

26. What is a branch prediction buffer?

 Branch prediction buffer also called branch history table.
 It is a small memory that is indexed by the lower portion of the address of the
branch instruction.
 It contains one or more bits indicating whether the branch was recently taken or not.
27. What are R-Type instructions?

28. Name the control signals required to perform arithmetic operations.

29. Define data hazard. Give an example for data hazard.

Data hazards occur when the pipeline changes the order of read/write accesses to operands so
that the order differs from the order seen by sequentially executing instructions on the un-pipelined
 machine.
Example: ADD R1, R2, R3
SUB R4, R1,
R5 AND R6,
R1, R7 OR R8,
R1, R9 XOR
R10, R1, R11

PART: B
1. What is cache memory? Discuss Mapping and Replacement Algorithms in detail.
2. Discuss DMA controller with block diagram
3. Discuss the steps involved in the address translation of virtual memory with necessary block diagram.

4. Explain in detail about virtual memory.

5. Explain in detail the operation of the data path and its control.
6. Explain the pipeline hazard in detail.