Release Notes For ModelSim Altera 10.

4e

Apr 08 2016
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_______________________________________________________________________

* How to Get Support

ModelSim Altera is supported by Altera Corporation
+ World-Wide-Web Support
[1]http://www.altera.com/mySupport
_______________________________________________________________________

Index to Release Notes

* [2]Key Information
* [3]Release Announcements in 10.4e
* [4]Base Product Specifications in 10.4e
* [5]Compatibility Issues with Release 10.4e
* [6]General Defects Repaired in 10.4e
* [7]User Interface Defects Repaired in 10.4e
* [8]SystemVerilog Defects Repaired in 10.4e
* [9]VHDL Defects Repaired in 10.4e
* [10]SystemC Defects Repaired in 10.4e
* [11]User Interface Enhancements in 10.4e
* [12]SystemVerilog Enhancements in 10.4e
_______________________________________________________________________

Key Information
* The following lists the supported platforms:
+ win32aloem - Windows 7, Windows 8
 + linuxaloem - RedHat Enterprise Linux 5 and 6, SUSE Linux
Enterprise Server 10 and 11
_______________________________________________________________________

Release Announcements in 10.4e

* [nodvtid] -
[10.4] Support for Windows XP and Windows Vista has been
discontinued.
[10.4] Licensing Information
There is no licensing change between release 10.3 and 10.4.
However if you are migrating to 10.4 from a release like 10.2 and
older, please note the following:
+ Starting 10.3, it uses FLEXnet v11.11.1.1. The vendor daemons
and lmgrd that are shipped with this release will be FLEXnet
version 11.11.1.1.
+ For floating licenses it will be necessary to verify that the
vendor daemon (i.e., mgcld) and the license server (i.e.,
lmgrd) have FLEXnet versions equal to or greater than
11.11.1.1. If the current FLEXnet version of your vendor
daemon and lmgrd are less than 11.11.1.1 then it will be
necessary to stop your license server and restart it using the
vendor daemon and lmgrd contained in this release.
+ If you use node locked licenses you don't need to do anything.
[10.3b] OVL is upgraded to v2.8.1.
[10.3b] The VHDL OSVVM (Open Source VHDL Verification Methodology)
library, sources and documentation have been updated to version
2014.01. Dependency checks in vopt and vsim will force
recompilation of designs that use the osvvm library. If
optimization is performed using vopt, the optimizer will
automatically generate new optimized design units. Without the
optimization step, vsim will detect dependency errors.
[10.3] Support for RedHat Enterprise Linux (RHEL) 4.0 has been
discontinued.
[10.2] Support for Solaris SPARC and Solaris x86 has been
discontinued. All Solaris OS platforms are not supported.
[10.2] Support for RedHat Enterprise Linux (RHEL) 3.0 and Novell
SUSE Linux Enterprise (SLES) 9 has been discontinued.
[10.1] Support for GCC versions
gcc-4.1.2-sunos510/gcc-4.1.2-sunos510x86 has been discontinued.
[10.0] Support for Solaris 8 and Solaris 9 has been discontinued.
_______________________________________________________________________

Base Product Specifications in 10.4e

* [nodvtid] -
[Supported Platforms]
Linux RHEL 5 x86/x86-64
Linux RHEL 6 x86/x86-64
Linux RHEL 7 x86/x86-64
Linux SLES 10 x86/x86-64
Linux SLES 11 x86/x86-64
Windows 7 x86/x64
Windows 8 x86/x64
[Supported GCC Compilers (for SystemC)]
gcc-4.7.4-linux/gcc-4.7.4-linux_x86_64
gcc-4.5.0-linux/gcc-4.5.0-linux_x86_64
gcc-4.3.3-linux/gcc-4.3.3-linux_x86_64
gcc-4.2.1-mingw32vc9
[OVL (shipped with product)]
v2.8.1
 [VHDL OSVVM (shipped with product)]
v2014.07
[Licensing]
FLEXnet v11.11.1.1
MSL v2013_3
MGLS v9.10_7.2
PCLS v9.10.7.2
_______________________________________________________________________

Compatibility Issues with Release 10.4e

SystemVerilog Compatibility
* dvt73179 - (results) Fix an improper vopt optimization when DPI
import call is involved in an always block.
* dvt84015 - (results) The non-standard feature of System Verilog
"force" and "release" statements that target a select of a variable
(as opposed to a net) do not fully support a non-constant rhs. A
warning is issued to this effect, and the resulting behavior may
not match the expected behavior for force and release semantics
involving a non-constant rhs. The behavior has been changed in this
release such that the rhs is evaluated just once at the time the
force is executed and is applied as though it is constant and does
not update forced value subsequently when any of the rhs variables
change value. Previously, the forced value would be updated when
the rhs variables change value, but any subsequent force or release
on the same target would not cancel the force. This old behavior
can be selected by specifying the vsim -reevalvarbitforces option.
* dvt84871 - (results) vsim crashed when annotating SDF to a full
specify path ( "*>") with path selects on source and destination
terminals. This happened only when the specify block contained more
than 64 paths and the width of the source and destination
part-selects were different. E.g. (a[17:9] *> y[36:18]) = (0);
* dvt83391 - (results) In some situations, a performance optimization
for FSDB dumping caused pli errors: # ** Error: (vsim-PLI-3532)
acc_vcl_add(): The object_handle parameter is not a handle to a
register, net, variable, port, terminal, or event. # ** Error:
(vsim-PLI-3494) acc_fetch_size(): The object_handle parameter is
not a handle to a net, register, or port, or a bit-select thereof.
setting the env variable MTI_OPT_FSDB=0 will also workaround this
problem.
* dvt66421 - (results) When vsim was run with any "-radix" other than
"binary", UVM backdoor functions uvm_hdl_deposit and uvm_hdl_force
didn't deposit/force the correct value into VHDL data objects.

SystemC Compatibility
* [nodvtid] - (results) sccom would invoke scparse with the '--c++0x'
option by default, which would enable the c++11 standard. The
enabling of the c++11 standard by default would lead to scparse
compilation errors in certain cases, while the g++ compilation
would run fine. sccom has been fixed not to pass '--c++0x' by
default. If a design has c++11 constructs, sccom needs to be
invoked with the '-std=c++11' option so that both, g++ and scparse
will run with the c++11 standard enabled during compilation.
_______________________________________________________________________

General Defects Repaired in 10.4e

* dvt84629 - [ModelSim Microsemi] Wrong license feature name
'actelmsimvlog' mentioned in licensing error message for expired
licenses. Should have been 'microsemimsim'.
 _______________________________________________________________________

User Interface Defects Repaired in 10.4e

* dvt83573 - The Wave window view will jump to the end time when
selecting items in the Structure window. This issue as been fixed.
To work around the problem in existing releases, set
PrefWave(ScrollOnRunComplete) 0, however, with this option
disabled, the Wave window will not scroll to the end after a run
either.
* dvt74842 - When saving a window image on Windows, the error
"expected integer but got "-x"" is reported. This problem has been
fixed.
* dvt86473 - Objects window will mis-sort items when the Active time
is inactive.
_______________________________________________________________________

SystemVerilog Defects Repaired in 10.4e

* dvt73179 - (results) Fix an improper vopt optimization when DPI
import call is involved in an always block.
* dvt84015 - (results) The non-standard feature of System Verilog
"force" and "release" statements that target a select of a variable
(as opposed to a net) do not fully support a non-constant rhs. A
warning is issued to this effect, and the resulting behavior may
not match the expected behavior for force and release semantics
involving a non-constant rhs. The behavior has been changed in this
release such that the rhs is evaluated just once at the time the
force is executed and is applied as though it is constant and does
not update forced value subsequently when any of the rhs variables
change value. Previously, the forced value would be updated when
the rhs variables change value, but any subsequent force or release
on the same target would not cancel the force. This old behavior
can be selected by specifying the vsim -reevalvarbitforces option.
* dvt84871 - (results) vsim crashed when annotating SDF to a full
specify path ( "*>") with path selects on source and destination
terminals. This happened only when the specify block contained more
than 64 paths and the width of the source and destination
part-selects were different. E.g. (a[17:9] *> y[36:18]) = (0);
* [nodvtid] - Extended Mac OS new-line warning message to cover line
comments when the line comments is the first text found within a
source file.
* dvt84189 - Inline randomization constraints with type casts would
sometimes generate compilation errors like:
** Error: test.sv(10): Illegal field 'my_type'
* dvt83391 - (results) In some situations, a performance optimization
for FSDB dumping caused pli errors: # ** Error: (vsim-PLI-3532)
acc_vcl_add(): The object_handle parameter is not a handle to a
register, net, variable, port, terminal, or event. # ** Error:
(vsim-PLI-3494) acc_fetch_size(): The object_handle parameter is
not a handle to a net, register, or port, or a bit-select thereof.
setting the env variable MTI_OPT_FSDB=0 will also workaround this
problem.
* dvt85773 - vsim crashed with "+bitblast" when a module contained a
wide port in $setuphold (or $recrem) but not corresponding delayed
nets. For example, "$setuphold(posedge CLK, posedge A,
0,0,notify);" where A is a wide port. In comparison,
"$setuphold(posedge CLK, posedge A, 0,0,notify,,, dCLK, dA);",
which has the delayed nets specified, did not crash.
* dvt66421 - (results) When vsim was run with any "-radix" other than
"binary", UVM backdoor functions uvm_hdl_deposit and uvm_hdl_force
 didn't deposit/force the correct value into VHDL data objects.
_______________________________________________________________________

VHDL Defects Repaired in 10.4e

* dvt82810 - A function containing a nested function called to
initialize a subtype of an object declared in the outer function
could cause the design to crash when loaded.
* dvt83738 - Incorrect code was generated for constant-index signal
assignments when the array elements are generic types. As a result,
the simulator could crash.
* dvt81426 - If an array-valued signal has only constant-index signal
assignments in a particular process, and the process contains an
expression involving either the 'driving or 'driving_value
attribute, incorrect code was generated for the attribute
expression. As a result, the simulator could crash during
evaluation of the expression.
* dvt85740 - The compiler (vcom) would issue an Internal error
message when an array aggregate expression was associated with a
port of a direct instantiation (ENTITY) when that port was of an
array-of-unconstrained array type and the port subtype was fully
constrained at the inner array and the constraint depended on
generics of the ENTITY, different from the ENTITY of the design
unit that contains the direct instantiation statement.
* dvt86029 - The simulator would crash when a port map associated an
array subelement of a record type signal with an array type port,
when the array subelement was defined as an unconstrained array
(i.e, the record type was record-with-unconstrained array
subelement).
_______________________________________________________________________

SystemC Defects Repaired in 10.4e

* [nodvtid] - (results) sccom would invoke scparse with the '--c++0x'
option by default, which would enable the c++11 standard. The
enabling of the c++11 standard by default would lead to scparse
compilation errors in certain cases, while the g++ compilation
would run fine. sccom has been fixed not to pass '--c++0x' by
default. If a design has c++11 constructs, sccom needs to be
invoked with the '-std=c++11' option so that both, g++ and scparse
will run with the c++11 standard enabled during compilation.
_______________________________________________________________________

User Interface Enhancements in 10.4e

* dvt21036 - The Search bar options such as Exact Match and Case
Sensitive, have been made persistent between sessions.
_______________________________________________________________________

SystemVerilog Enhancements in 10.4e

* [nodvtid] - Added a vlog and vopt -svext=tzas option that runs a
top-blocking always @* at time zero, same as is done for an
always_comb, meaning that the always block will behave as though
triggered at time zero even if none of the variables and nets in
the implied sensitivity change value at time zero.
* [nodvtid] - vlog's -E output would not emit `line directives with
anything other than '0' for the "level" parameter. Valid values for
the "level" parameter are 0, 1 or 2.