Release Notes For ModelSim Altera 10.

4b

May 26 2015
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_______________________________________________________________________

* How to Get Support

ModelSim Altera is supported by Altera Corporation
+ World-Wide-Web Support
[1]http://www.altera.com/mySupport
_______________________________________________________________________

Index to Release Notes

* [2]Key Information
* [3]Release Announcements in 10.4b
* [4]Base Product Specifications in 10.4b
* [5]Compatibility Issues with Release 10.4b
* [6]User Interface Defects Repaired in 10.4b
* [7]SystemVerilog Defects Repaired in 10.4b
* [8]VHDL Defects Repaired in 10.4b
* [9]General Enhancements in 10.4b
* [10]SystemVerilog Enhancements in 10.4b
* [11]Coverage Enhancements in 10.4b
_______________________________________________________________________

Key Information
* The following lists the supported platforms:
+ win32aloem - Windows 7, Windows 8
+ linuxaloem - RedHat Enterprise Linux 5 and 6, SUSE Linux
 Enterprise Server 10 and 11
_______________________________________________________________________

Release Announcements in 10.4b

* [nodvtid] -
[10.4] Support for Windows XP and Windows Vista has been
discontinued.
[10.4] Licensing Information
There is no licensing change between release 10.3 and 10.4.
However if you are migrating to 10.4 from a release like 10.2 and
older, please note the following:
+ Starting 10.3, it uses FLEXnet v11.11.1.1. The vendor daemons
and lmgrd that are shipped with this release will be FLEXnet
version 11.11.1.1.
+ For floating licenses it will be necessary to verify that the
vendor daemon (i.e., mgcld) and the license server (i.e.,
lmgrd) have FLEXnet versions equal to or greater than
11.11.1.1. If the current FLEXnet version of your vendor
daemon and lmgrd are less than 11.11.1.1 then it will be
necessary to stop your license server and restart it using the
vendor daemon and lmgrd contained in this release.
+ If you use node locked licenses you don't need to do anything.
[10.3b] OVL is upgraded to v2.8.1.
[10.3b] The VHDL OSVVM (Open Source VHDL Verification Methodology)
library, sources and documentation have been updated to version
2014.01. Dependency checks in vopt and vsim will force
recompilation of designs that use the osvvm library. If
optimization is performed using vopt, the optimizer will
automatically generate new optimized design units. Without the
optimization step, vsim will detect dependency errors.
[10.3] Support for RedHat Enterprise Linux (RHEL) 4.0 has been
discontinued.
[10.2] Support for Solaris SPARC and Solaris x86 has been
discontinued. All Solaris OS platforms are not supported.
[10.2] Support for RedHat Enterprise Linux (RHEL) 3.0 and Novell
SUSE Linux Enterprise (SLES) 9 has been discontinued.
[10.1] Support for GCC versions
gcc-4.1.2-sunos510/gcc-4.1.2-sunos510x86 has been discontinued.
[10.0] Support for Solaris 8 and Solaris 9 has been discontinued.
_______________________________________________________________________

Base Product Specifications in 10.4b

* [nodvtid] -
[Supported Platforms]
Linux RHEL 5 x86/x86-64
Linux RHEL 6 x86/x86-64
Linux RHEL 7 x86/x86-64
Linux SLES 10 x86/x86-64
Linux SLES 11 x86/x86-64
Windows 7 x86/x64
Windows 8 x86/x64
[Supported GCC Compilers (for SystemC)]
gcc-4.7.4-linux/gcc-4.7.4-linux_x86_64
gcc-4.5.0-linux/gcc-4.5.0-linux_x86_64
gcc-4.3.3-linux/gcc-4.3.3-linux_x86_64
gcc-4.2.1-mingw32vc9
[OVL (shipped with product)]
v2.8.1
[VHDL OSVVM (shipped with product)]
 v2014.07
[Licensing]
FLEXnet v11.11.1.1
MSL v2013_3
MGLS v9.10_7.2
PCLS v9.10.7.2
_______________________________________________________________________

Compatibility Issues with Release 10.4b

VHDL Compatibility
* dvt77769 - (results) A type conversion from a floating point type
to an integer type will now produce an Error message if the
floating point value is outside the range of a signed 32-bit
integer. Also, a type TIME expression involving a floating point
expression will produce an Error message if the result is outside
the range of a 64-bit signed integer; in this case, the lower bound
is -9223372036854775807, which is the smallest position number
allowed for type TIME. Finally, a type conversion will check that
the result belongs to the subtype denoted by the type mark of the
target type.

Coverage Compatibility
* dvt69525 - (results) Some toggle nodes of a VHDL record were
missing in viewcov mode

SystemVerilog Compatibility
* [nodvtid] - (source, results) There has been a change in the VPI
interface to vpiAssertion class objects. The SystemVerilog 2012 LRM
indicates that vpiAssertion objects may be iterated for from
vpiInstance class objects only, not from all vpiScopes, however
assertion objects may in fact be under other scope class parents.
We have previously added these sub-scope descendant assertions to
the instance assertion. This change makes the assertion iteration
valid on all scope objects to bring it into line with similar
vpiVariable iterations. A consequence is that sub-scope iterations
are necessary to find all the assertions in an instance.
_______________________________________________________________________

User Interface Defects Repaired in 10.4b

* dvt63651 - A drag-area zoom-in operation in the wave window would
sometimes zoom to the wrong location. This issue has been resolved.
* dvt77471 - Wave window cursor frequency display shows incorrectly
scaled values for certain time resolution values. This problem has
been corrected.
_______________________________________________________________________

SystemVerilog Defects Repaired in 10.4b

* dvt76387 - The prototypes of DPI functions inside nested interface
were not generated in dpiheader generation.
* dvt76661 - The compiler incorrectly issued a "data size overflow"
error for large unpacked arrays and structures that overflowed a
32-bit integer size even when compiled for 64-bit.
_______________________________________________________________________

VHDL Defects Repaired in 10.4b

* dvt70676 - Some uses of A'RANGE (and A'REVERSE_RANGE) where a value
(not a range) is required were not being caught as errors by the
compiler.
 * [nodvtid] - Writing a value to a file of a type whose type mark is
a scalar subtype that has a range constraint would not check that
the value belonged to the subtype. This has been fixed.
* dvt67887 - Associating a signal alias with a port, where the
subtype indication of the alias declaration is a partially
constrained record, would result in a design that would fail during
elaboration.
* dvt75934 - unexpected internal error: ../../src/vsim/vinst.c(7889)
issue resolved.
* dvt69385 - Declaring and using aliases of external signals in a
block would crash.
* dvt73631 - If a subprogram instantiates a package, and then calls a
subprogram of the package, variables of the called subprogram may
not be visible or accessible in the graphical interface or through
the examine command. In addition, if the design is optimized with
vopt using the +cover switch to enable code coverage, during
elaboration of the design, the simulator's console terminal may
report errors of the form:
../../src/vsim/rtu.c(xxxx). Please contact Questa support at http://supportnet.m
entor.com/

* dvt77077 - A crash could occur when using an output port as the

actual to a subprogram formal that is a signal Rising_edge is an
example of such a subprogram. Because of optimization, this doesn't
no occur for all cases and maybe affected by the use of switches
like -no1164 and -O1.
* dvt76995 - A variable of a protected type that contains a data
member that is of class FILE could not be displayed, examined, or
logged properly. Since FILEs themselves cannot be logged, such a
protected type variable will have the FILE data member be shown as
"Not Loggable", and the WLF file (for post-sim viewing) will not
show the variable as having this FILE at all.
* dvt77275 - A Fatal error during elaboration could occur within an
optimized vhdl process if signal valued attributes are used within
that process. The name reported for the optimized processed will
start #MERGED#.
* [nodvtid] - Bad machine code would be generated in the case of an
access type to an generic type and the generic type's actual is a
record type. This could result in crashes or incorrect simulation
* dvt77420 - Memory corruption could occur if a generic package is
instantiated within the scope of a subprogram. Instances of a
generic package outside of subprogram is unaffected by this issue.
The memory corruption has been fixed.
* dvt77769 - (results) A type conversion from a floating point type
to an integer type will now produce an Error message if the
floating point value is outside the range of a signed 32-bit
integer. Also, a type TIME expression involving a floating point
expression will produce an Error message if the result is outside
the range of a 64-bit signed integer; in this case, the lower bound
is -9223372036854775807, which is the smallest position number
allowed for type TIME. Finally, a type conversion will check that
the result belongs to the subtype denoted by the type mark of the
target type.
_______________________________________________________________________

General Enhancements in 10.4b

* dvt25231 - The following license related items are added to
'simstats' command report.
[simstats verbose]
 New 'elab' report item is added for checked-out license features
names.
Example:
# elab: license features used qhsimvl
[simstats license]
New 'License Statistics' section is added for checkout time and
checked-out
license features names. Example:
# License Statistics
# license: checkout time 0.05 s
# license: features used qhsimvl
_______________________________________________________________________

SystemVerilog Enhancements in 10.4b

* [nodvtid] - (source, results) There has been a change in the VPI
interface to vpiAssertion class objects. The SystemVerilog 2012 LRM
indicates that vpiAssertion objects may be iterated for from
vpiInstance class objects only, not from all vpiScopes, however
assertion objects may in fact be under other scope class parents.
We have previously added these sub-scope descendant assertions to
the instance assertion. This change makes the assertion iteration
valid on all scope objects to bring it into line with similar
vpiVariable iterations. A consequence is that sub-scope iterations
are necessary to find all the assertions in an instance.
_______________________________________________________________________

Coverage Enhancements in 10.4b

* [nodvtid] - vcover parallelmerge command now supports auto-rerun
feature for failed parallel processes (due to either job submission
or merge failure). Job submission failures are rerun by default.
Merge failure rerun can be enabled with -mergererun option. Number
of retries for both rerun types can be controlled with -maxrerun
option.
-maxrerun < val > : Specify maximum number of times job queue, timeou
ts
or merge failure processes are rerun automaticall
y. (Default: 10)
Specifying 0 will disable reruns for all failures
types
-mergererun : Allow merge failure processes to rerun automatica
lly

* [nodvtid] - vcover parallelmerge command allows user to override

temporary directory path.
-tempdir "< dir_path >" : Specify temporary directory for intermedia
te output
(Default: "$cwd/TEMP_MERGE_DIR")