Release Notes For ModelSim Altera 10.

3e

Feb 23 2015
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_______________________________________________________________________

Index to Release Notes

* [2]Key Information
* [3]Release Announcements in 10.3e
* [4]Base Product Specifications in 10.3e
* [5]Compatibility Issues with Release 10.3e
* [6]General Defects Repaired in 10.3e
* [7]User Interface Defects Repaired in 10.3e
* [8]SystemVerilog Defects Repaired in 10.3e
* [9]VHDL Defects Repaired in 10.3e
* [10]General Enhancements in 10.3e
* [11]User Interface Enhancements in 10.3e
_______________________________________________________________________

Key Information
* The following lists the supported platforms:
+ win32aloem - Windows XP, Windows 7, Windows 8
+ linuxaloem - RedHat Enterprise Linux 5 and 6, SUSE Linux
 Enterprise Server 10 and 11
_______________________________________________________________________

Release Announcements in 10.3e

* [nodvtid] -
In the next major release (10.4), support for Windows XP and
Windows Vista will be discontinued.
[10.3e] Licensing Information
There is no licensing change between release 10.3 and 10.3e.
However if you are migrating to 10.3e from a release like 10.2 and
older, please note the following:
+ Starting 10.3, it uses FLEXnet v11.11.1.1. The vendor daemons
and lmgrd that are shipped with this release will be FLEXnet
version 11.11.1.1.
+ For floating licenses it will be necessary to verify that the
vendor daemon (i.e., mgcld) and the license server (i.e.,
lmgrd) have FLEXnet versions equal to or greater than
11.11.1.1. If the current FLEXnet version of your vendor
daemon and lmgrd are less than 11.11.1.1 then it will be
necessary to stop your license server and restart it using the
vendor daemon and lmgrd contained in this release.
+ If you use node locked licenses you don't need to do anything.
[10.3b] OVL is upgraded to v2.8.1.
[10.3b] The VHDL OSVVM (Open Source VHDL Verification Methodology)
library, sources and documentation have been updated to version
2014.01. Dependency checks in vopt and vsim will force
recompilation of designs that use the osvvm library. If
optimization is performed using vopt, the optimizer will
automatically generate new optimized design units. Without the
optimization step, vsim will detect dependency errors.
[10.3] Support for RedHat Enterprise Linux (RHEL) 4.0 has been
discontinued.
[10.2] Support for Solaris SPARC and Solaris x86 has been
discontinued. All Solaris OS platforms are not supported.
[10.2] Support for RedHat Enterprise Linux (RHEL) 3.0 and Novell
SUSE Linux Enterprise (SLES) 9 has been discontinued.
[10.1] Support for GCC versions
gcc-4.1.2-sunos510/gcc-4.1.2-sunos510x86 has been discontinued.
[10.0] Support for Solaris 8 and Solaris 9 has been discontinued.
_______________________________________________________________________

Base Product Specifications in 10.3e

* [nodvtid] -
[Supported Platforms]
Linux RHEL 5 x86/x86-64
Linux RHEL 6 x86/x86-64
Linux SLES 10 x86/x86-64
Linux SLES 11 x86/x86-64
Windows 7 x86/x64
Windows 8 x86/x64
Windows XP
Windows Vista
[Supported GCC Compilers (for SystemC)]
gcc-4.5.0-linux/gcc-4.5.0-linux_x86_64
gcc-4.3.3-linux/gcc-4.3.3-linux_x86_64
gcc-4.2.1-mingw32vc9
[OVL (shipped with product)]
v2.8.1
[VHDL OSVVM (shipped with product)]
 v2014.01
[Licensing]
FLEXnet v11.11.1.1
MSL v2013_3
MGLS v9.10_7.2
PCLS v9.10.7.2
_______________________________________________________________________

Compatibility Issues with Release 10.3e

Key Information Compatibility

* dvt73631 - (results) VHDL 2008 users who use generic packages or
subprograms must refresh the associated design units or recompile
from source code with this release. Changes made for correctness
affect internal data structures and are incompatible with vhdl-2008
design units generated with earlier releases.

User Interface Compatibility

* dvt71982 - (results) Individual 2-state SV struct field values
could be shown incorrectly in the Objects window. This has been
corrected.
* dvt70169 - (results) Logging a System Verilog interface port would
result in the actual interface being logged, but not the port. The
fix ensures that the port AND the actual interface are logged so
that post-simulation viewing of the WLF file will contain both the
port and the actual interface. NOTE: This required a WLF file
version change. This makes WLF files written with this version of
Modelsim/Questa incompatible and unreadable by older version of
Modelsim/Questa.
* [nodvtid] - (results) A new feature called VHDL Access Path
Expressions has been introduced which provides improved visibility
and a more intuitive way of viewing VHDL access variables and
objects in the Wave Window. Some of the features of vhdl access
path expressions are:
+ More descriptive pointer values. Values are Dynamic Object
Identifiers instead of hexadecimal memory address.
+ Access references may be expanded in place in the wave window
rather than having to inspect individual access objects one by
one.
+ Ability to add access_var.all to see dereferenced object
values.
+ Ability to "cast" unconstrained arrays to constrained array
type.
+ The [accessinfo] command gives metrix and reports about access
object usage.
+ Enabled with -accessobjdebug switch or AccessObjDebug
modelsim.ini variable setting.

VHDL Compatibility
* dvt71619 - (results) On 64 bits, array shift and rotate operations
whose second operand ( shift/rotate amount) is INTEGER'LEFT would
generate a stack overflow error. This has been fixed and the result
when the shift/rotate amount is INTEGER'LEFT on both 64 and 32 bit
has been changed to generate the correct value.
_______________________________________________________________________

General Defects Repaired in 10.3e

* dvt70157 - Restored vmake's behavior for VHDL design units to
better deal with building incrementally and use of vcom's "-f"
 switch.
_______________________________________________________________________

User Interface Defects Repaired in 10.3e

* dvt63858 - Toggling the "Within Cells" mode of the Memory List
window while a search filter is in use can cause the display of an
incomplete list of memories. This issues has been resolved.
* dvt71982 - (results) Individual 2-state SV struct field values
could be shown incorrectly in the Objects window. This has been
corrected.
* dvt64155 - Two new radixes have been implemented, sfixed and ufixed
(signed fixed and unsigned fixed, respectively.) Values may be
displayed using these radixes, for example, [examine -radix ufixed
var] might produce the value 1.375. The criteria for displaying an
object as sfixed or ufixed is that the type of the object must be
an array of std_ulogic elements between 2 and 64 bits long with a
descending range. (The set of supported types may increase in the
future.) The binary point for the value is implicitly located
between the 0th and -1st elements of the array. The index range for
the type need not include 0 or -1, for example (-4 downto -8) in
which case the value will be extended for conversion, as
appropriate. If the type does not meet these criteria the value
will be displayed as decimal or unsigned, respectively. The radix
command, global radix dialog and wave window radix menus support
these radixes.
* dvt71287 - The "Fixed Point Radix" dialog box was missing the radix
"decimal" as a possible base type. This has been corrected. Decimal
is now the default base selection in the dialog.
* dvt74014 - A malformed [add wave] command can cause the UI to
crash.
* dvt74038 - A user defined keyboard short-cut bound to the
Simulate->Step->Step commands, or any other global menu operations
do not work. This has been resolved.
* dvt74187 - The wrong instance scope will sometimes be used when
displaying a signals declaration in the Source window from the Wave
window.
* dvt74126 - In Questa, the "change" command could crash or
incorrectly ignore ".super" psuedo scope. This has been corrected.
* dvt29745 - Using the Library window popup menu to invoke Simulate
(start a simulation) will sometimes produce an error message and
fail to launch the simulation. This occurs after performing a
design optimization from the Library window.
* dvt74813 - Mouse Middle Button zoom-out stroke does not work in
Wave window when the waveform view starts at 0.
* dvt70169 - (results) Logging a System Verilog interface port would
result in the actual interface being logged, but not the port. The
fix ensures that the port AND the actual interface are logged so
that post-simulation viewing of the WLF file will contain both the
port and the actual interface. NOTE: This required a WLF file
version change. This makes WLF files written with this version of
Modelsim/Questa incompatible and unreadable by older version of
Modelsim/Questa.
_______________________________________________________________________

SystemVerilog Defects Repaired in 10.3e

* dvt70882 - A bit-select of a hierarchical reference connected to a
module input port produced incorrect results in some cases if the
bit-select index also contained a hierarchical reference.
* [nodvtid] - Array manipluation functions like
 "arr.find_first_index(x) with ...condition..." would incorrectly
report the error "No field named 'x'" in some cases.
* dvt73472 - vsim gave incorrect result when using tagged union over
an expression with different size elements.
* dvt73470 - vlog/vopt gave internal error in vgenexpr.c(2897) when a
wait statement is over a method call of an element of a class
array.
* dvt74214 - Fixed a crash in a DPI import call caused by using class
member fields as the actual arguments of unsized packed open array.
* dvt74468 - The implied @* sensitivity should exclude variables
referenced within a sequential delay.
* dvt73310 - Traversing individual words of large SV memories using
vpi_iterate/vpi_scan functions caused huge memory usage.
_______________________________________________________________________

VHDL Defects Repaired in 10.3e

* dvt67672 - An array aggregate with an OTHERS choice in an O'SUBTYPE
or A'ELEMENT context was erroneously being flagged as an Error.
This has been fixed.
* dvt71619 - (results) On 64 bits, array shift and rotate operations
whose second operand ( shift/rotate amount) is INTEGER'LEFT would
generate a stack overflow error. This has been fixed and the result
when the shift/rotate amount is INTEGER'LEFT on both 64 and 32 bit
has been changed to generate the correct value.
* dvt72143 - If an uninstantiated package contains signal
declarations, and an instance of the package is associated with an
interface package in an entity, package, or subprogram
instantiation, accesses to the signals could lead to simulator
error messages of the form:
# ** INTERNAL ERROR: pkgref: export lookup failed for package #8[7]

* dvt72793 - A PROCESS(ALL) statement in which the ALL represents no

signals would result in the process having no termination (infinite
loop).
* dvt73051 - Fixed elaboration crash with subelement association. The
formal must be an element or subelement of a multidimensional port
and the actually a 2008 signal expression.
* [nodvtid] - Aggregates of signals in subprograms, either as
parameters to other subprogram, or as targets of signal assignments
could cause a crash if the aggregate contained both parameters and
non-parameter signals.
* dvt74124 - Vcom could fail with an internal error when a port map
statement is present on a block
* dvt74313 - If an attribute that returned a range is used as the
expression to a return statement, incorrect machine code could be
generated. A range is not a valid return value and is now flagged
as an error a compile time.
* [nodvtid] - Logging of composite type variables with embedded
access type subelements would sometimes not detect and record
changes to those subelements.
_______________________________________________________________________

General Enhancements in 10.3e

* dvt68871 - Added support in vlog, vcom and vopt to automatically
create missing work libraries. Vlog/vcom/vopt command-line option
'-nocreatelib', or modelsim.ini variable 'CreateLib', may be used
to stop automatic creation of missing work libraries and revert
back to the old (10.3x and earlier) behavior.
* dvt73792 -
 1. The vsim "checkpoint" command now accepts a file or a directory
as the pathname.
Syntax:
checkpoint [-dir] <pathname>
The following are the two valid scenarios for specifying a
directory as the <pathname>. In both these cases a checkpoint file
named 'vsim.cpt' is created in the specified directory.
+ - The "-dir" option is specified with the <pathname>. If the
directory doesn't exist then a new one is created.
+ - The "-dir" option is not specified with the <pathname> but
it represents a pre-exisiting directory.
It is an error if "-dir" is specified but the <pathname> represents
a regular file.
2. vsim's "restore" CLI command and the command line switch
"-restore" now accept a file or a directory as the pathname. (The
syntax has not changed, only the semantics).
Syntax:
restore <pathname>

* - If the <pathname> represents a pre-exisiting directory, then a

checkpoint file named 'vsim.cpt' must exist in the specified
directory.
* - Otherwise the <pathname> must represent a checkpoint file.

3. When the checkpoint is represented by a directory the following new

function, declared in "mti.h" file, returns that directory name.
extern char * mti_GetCheckpointDirname PROTO((void));
_______________________________________________________________________

User Interface Enhancements in 10.3e

* dvt10305 - The [add log], [add wave] and [add list] commands have
the new -filter and -nofilter switches to allow a one-time
modification of the WildcardFilter in the command invocation. The
commands can take as many [-filter <f>] and [-nofilter <f>]
arguments as the user would like to specify. The valid filters are
exactly the same set of words that can be applied to the
WildcardFilter. The filter used during a command starts with the
WildcardFilter and then applies the user specified filters, if any.
The -filter values are added to the filter, the -nofilter values
are removed from the filter. They are applied in the order
specified so conflicts are resolved with the last specified wins.
* [nodvtid] - (results) A new feature called VHDL Access Path
Expressions has been introduced which provides improved visibility
and a more intuitive way of viewing VHDL access variables and
objects in the Wave Window. Some of the features of vhdl access
path expressions are:
+ More descriptive pointer values. Values are Dynamic Object
Identifiers instead of hexadecimal memory address.
+ Access references may be expanded in place in the wave window
rather than having to inspect individual access objects one by
one.
+ Ability to add access_var.all to see dereferenced object
values.
+ Ability to "cast" unconstrained arrays to constrained array
type.
+ The [accessinfo] command gives metrix and reports about access
object usage.
+ Enabled with -accessobjdebug switch or AccessObjDebug
modelsim.ini variable setting.