Code No: R2032042 R20 SET -1
III B. Tech II Semester Regular/Supplementary Examinations, May/June -2024
VLSI DESIGN
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****
UNIT-I
1. a) Derive the CMOS inverter DC characteristics and obtain the relationship for [7M]
output voltage at different region in the transfer characteristics.
b) For a CMOS inverter calculates the shift in transfer characteristic curve when [7M]
βn/βp ratio is varied from 1/1 to 10/1.
(OR)
2. a) Derive the equations for Ids of an n-channel enhancement MOSFET operating [7M]
in Non-saturated region and saturated region?
b) Draw the circuit for nMOS inverter and explain the transfer characteristic using [7M]
necessary equations, and the different regions in the characteristics.
UNIT-II
3. a) List out the scaling factors for the different device parameters in terms of [7M]
different scaling models?
b) Calculate the ON resistance from VDD to GND for the nMOS and CMOS [7M]
inverter circuits.
(OR)
4. a) Explain the model for derivation of time delay? [7M]
b) Discuss the limits of scaling. Why scaling is necessary for VLSI circuits? [7M]
UNIT-III
5. a) Draw and explain the circuit diagram for common source amplifier and also [7M]
construct input-output characteristics for the same?
b) How do we maximize the voltage gain of a common-source stage? Explain [7M]
(OR)
6. a) Draw the small-signal equivalent circuit of diode connected MOSFET and [7M]
measure the equivalent resistance?
b) Calculate the output resistance of a simple current mirror. [7M]
UNIT-IV
7. a) Explain the different approaches used to reduce delays in large fan-in circuits? [7M]
b) Draw the basic structure of a dynamic CMOS gate and explain the same? [7M]
(OR)
8. a) Explain about pass transistor logic. [7M]
b) Draw and explain about SR Master slave register. [7M]
UNIT-V
9. a) Write down the step by step approach of FPGA design process on XILINX [7M]
environment?
b) Draw and explain the basic architecture of FPGA? [7M]
(OR)
10. a) Write about Drain Induced Barrier Lowering effect in nMOS transistor? [7M]
Explain with neat sketch.
b) List out the advantages and disadvantages of metal gate technology? [7M]
1 of 1
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Code No: R203105O
R2031011
R2031351
R203135A
R203147A
R203147C
P2031051
R2032042 R20 SET
SET
RA--22
III B. Tech II Semester Regular/Supplementary Examinations, May/June -2024
VLSI DESIGN
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****
UNIT-I
1. a) Explain in detail the p-well process for CMOS fabrication indicating the masks [7M]
used.
b) Tabulate the comparisons between n-well and p-well CMOS fabrication [7M]
processes?
(OR)
2. a) What is a stick diagram? Draw the stick diagram and layout for a CMOS [7M]
inverter?
b) Explain the different types of design rules and give some examples. [7M]
UNIT-II
3. a) What is sheet resistance? Derive the Expression for RS? [7M]
b) Two nMOS inverters are cascaded to drive a capacitive load CL = 16 Cg. [7M]
Calculate the pair delay in turns of τ for the inverter indicated in the figure
below. What are the ratios of each inverter?
Inverter 1 Inverter 2
LPU = 16 λ LPU = 2 λ
WPU = 2 λ WPU = 2 λ
LPd = 2 λ LPd = 2 λ
WPd = 2 λ WPd = 8 λ
(OR)
4. a) What is the problem of driving large capacitive loads? Explain a method to [7M]
drive such load.
b) Briefly discuss about the scaling limits on logic levels and supply voltage due [7M]
to noise?
UNIT-III
5. a) Draw the small-signal model for the MOS transistor. Briefly explain each [7M]
component in that?
b) Choose values of VGS = 1,2,3,4 and 5V, assume that the channel modulation [7M]
parameter is zero. Sketch to scale the output characteristics of an enhancement
n-channel device if VT = 0.7V and ID = 500µA when VGS = 5 Vin saturation.
(OR)
6. a) Derive the voltage gain equation for common source amplifier at high [7M]
frequencies.
b) Write short notes on current sinks and sources? [7M]
1 of 2
|'''|'|'|''||'''||||
Code No: R2032042
R2031011
R2031351
R203135A
R203147A
R203147C
R203105O
P2031051 R20 SET
SET
RA--22
UNIT-IV
7. a) Draw the basic one-transistor storage cell with cross-coupled latch sense [7M]
amplifier and explain the operation with suitable timing diagrams?
b) With EX-OR gate as an example explain about static and dynamic logics. [7M]
(OR)
8. a) Implement 4-input NAND gate using CPL and also construct the layout [7M]
diagram for the same?
b) With suitable diagrams explain how switch logic can be implemented using [7M]
Pass Transistors and transmission gates?
UNIT-V
9. a) Give the steps in FPGA design flow with flow diagram and briefly discuss [7M]
about each step.
b) List out the various FPGA Boards and software tools required for digital [7M]
system design?
(OR)
10. a) How does surface scattering affect the mobility of electrons in MOSFET? [7M]
Explain with neat diagram.
b) What is tunneling field effect transistor (TFET)? What are the advantages of [7M]
using a TFET transistor?
2 of 2
|'''|'|'|''||'''||||
Code No: R203105O
R2031351
R203135A
R203147A
R203147C
P2031051
R2032042
R2031011 R20 SET
SET
RA--32
III B. Tech II Semester Regular/Supplementary Examinations, May/June -2024
VLSI DESIGN
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****
UNIT-I
1. a) Explain the steps in twin-tub process of CMOS fabrication with suitable sketch. [7M]
b) Tabulate the encoding scheme for a simple single metal nMOS process with [7M]
respect to various MOS layers.
(OR)
2. a) Give the design rules for the following cases with neat sketches [7M]
i) Polysilicon – polysilicon ii) n-type diffusion – n-type diffusion
iii) n-type diffusion – p-type diffusion iv) metal 1 – metal 2.
b) Show that the switching speed of an enhancement MOSFET varies inversely as [7M]
the square of the channel length?
UNIT-II
3. a) What is inverter delay? How delay is calculated for multiple stages. [7M]
b) How does depletion regions around source and drain are affected due to scaling [7M]
down of device dimensions? Explain
(OR)
4. a) Explain about the constraints in choice of layers. [7M]
b) Derive the expression for propagation delay in the case of cascaded pass [7M]
transistors?
UNIT-III
5. a) With the help of neat circuit diagrams explain about CS stage with source [7M]
degeneration?
b) Derive an expression for transconductance and small-signal voltage gain for [7M]
degenerated CS stage with the help of small-signal equivalent circuit?
(OR)
6. a) What is the need of source follower? Draw and explain the input-output [7M]
characteristics of source follower?
b) List out the comparisons between CS, CG and CD amplifier stages? [7M]
UNIT-IV
7. a) In gate logic compare the geometry aspects between two input nMOS NAND gate [7M]
and CMOS NAND gate?
b) Draw the positive latch using transmission gates and explain the operation? [7M]
(OR)
8. a) Explain about Domino CMOS logic. Draw the Domino structure for AND and OR [7M]
gates?
b) Draw the schematic circuit of a SR flip flop with negative edge triggering using [7M]
NAND gates. Give its truth table and explain its operation?
1 of 2
|'''|'|'|''||'''||||
Code No: R2032042
R2031011
R2031351
R203135A
R203147A
R203147C
R203105O
P2031051 R20 SET
SET
RA--32
UNIT-V
9. a) What are FPGAs? Explain about the principle and operation of FPGAs. What are its [7M]
applications?
b) List out the important features of Altera Flex 8000FPGA? [7M]
(OR)
10. a) With the help of neat diagram explain about impact ionization? [7M]
b) What is giga-scale integration (GSI)? How does the gate delay scale down with [7M]
improvement of semiconductor technology?
2 of 2
|'''|'|'|''||'''||||
Code No: R2031011
R2031351
R203135A
R203147A
R203147C
R203105O
P2031051
R2032042 R20 SET
SET
RA--42
III B. Tech II Semester Regular/Supplementary Examinations, May/June -2024
VLSI DESIGN
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****
UNIT-I
1. a) With neat circuit diagram and transfer characteristics explain the operation of [7M]
CMOS inverter?
b) Draw the schematic, layout and stick diagram for two input nMOS NAND [7M]
gates?
(OR)
2. a) Discuss the alternative forms of pull-up for an inverter circuit. Compare the [7M]
relative merits of three different forms of pull-ups?
b) Draw the nMOS inverter circuit and determine the pull-up to pull-down ratio of [7M]
an nMOS inverter driven by another nMOS inverter?
UNIT-II
3. a) Why scaling is required? Write the scaling factors for different types of device [7M]
parameters?
b) Write notes on sheet resistance concept and its applications. [7M]
(OR)
4. a) Explain the issues involved in driving large capacitor loads in VLSI circuit [7M]
regions?
b) Derive the expressions for rise time and fall time in the case of CMOS inverter. [7M]
UNIT-III
5. a) Explain the small signal model for common source stage and sketch the drain [7M]
current and trans conductance of transistor as a function of the input voltage?
b) Explain briefly about body bias effect with neat diagrams? [7M]
(OR)
6. a) Briefly discuss about CS stage with diode connected load and also draw the [7M]
input-output characteristics?
b) List out the applications of CS, CG and CD amplifier stages? [7M]
UNIT-IV
7. a) What is level restoration? Explain the level restoring circuit with the help of [7M]
neat sketch?
b) What are the advantages and disadvantages of dynamic logic? Explain. [7M]
(OR)
8. a) Draw the Master-slave positive edge-triggered register using multiplexers and [7M]
explain the operation?
b) What is pipelining? Explain the operation of two-phase pipelined circuit using [7M]
dynamic registers?
1 of 2
|'''|'|'|''||'''||||
Code No: R2032042
R2031011
R2031351
R203135A
R203147A
R203147C
R203105O
P2031051 R20 SET
SET
RA--42
UNIT-V
9. a) Explain the following terms: [7M]
i) LUT ii) CLB iii) IOB iv) Switch matrix
b) List out the different FPGA families. Explain how they are differing. [7M]
(OR)
10. a) Briefly discuss about velocity saturation effects in a Short Channel Si- [7M]
MOSFET?
b) What is a FinFET? What are the differences between FinFET and a multi-gate [7M]
transistor?
2 of 2
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