DIGITALLOGICDESIGN

Lecture 4
LECTUREOUTLINE
• Combinational Logic Circuits
• Stepsof Combinational Logic Design
• The XOR Function
• Half Adder
• Full Adder
• Binary Adder/Subtractor
• Binary Multiplier

2
 COMBINATIONALLOGIC
•Combinational logic circuits can
have any number of inputs and
outputs
•The logic states of the inputs at
any given instant determine the
state of the output

•Sequentialcircuits, which we will discusslater in this course, will

feature circuits in which the outputs are not determined solely by
the inputs at the same time

3
 HOWTODESIGNA
COMBINATIONAL LOGICCIRCUIT?
1. Fromthe specifications of the circuit, determine the
required number of inputs and outputs and assign a
letter (symbol) to each
2. Derive the truth table that defines the required
relationship between the inputs and outputs
3. Obtain the simplified Boolean functions for each
output as a function of the input variables (using a K-
map)
4. Sketch the logic diagram

4
 DESIGNPROBLEM
Design a digital system whose output is defined as logically
low if the 4-bit input binary number isa multiple of 3;
Otherwise, the output will be logically high. The output is
defined if and only if the input binary number is greater
than 2

5
 INPUT/OUTPUTRELATIONSHIP
AND TRUTHTABLE
• Design a digital system
whose output is defined as
logically low if the 4-bit
input binary number is a
multiple of 3; otherwise, the
output will be logically high

• The output is defined if and

only if the input binary
number is greater than 2

6
BOOLEANFUNCTION
SIMPLIFICATION USINGAK-MAP

7
 BOOLEANFUNCTION
SIMPLIFICATION USINGAK-MAP

SOP POS

𝑌𝑆𝑂𝑃 = 𝐵 ′ 𝐷 ′ + 𝐴 ′ 𝐶 ′ + 𝐴′𝐵𝐷 + 𝐵𝐶 ′ 𝐷 + 𝐴𝐵 ′ 𝐶 + 𝐴𝐶𝐷′

𝑌𝑃𝑂𝑆 = (𝐴 + 𝐵)(𝐵 + 𝐶 + 𝐷′)(𝐴 + 𝐶 ′ + 𝐷)(𝐴′ + 𝐵 ′ + 𝐶 + 𝐷)(𝐴′ + 𝐵 ′ + 𝐶′ + 𝐷′)
8
SKETCHINGTHE
LOGICDIAGRAM

9
 XOR

THEXORFUNCTION
X Y Z
The XOR symbol is denoted as ⊕ 0 0 0
Its Boolean operation is 𝑥 ⊕ 𝑦 = 𝑥𝑦′ + 𝑥 ′ 𝑦 0 1 1
1 0 1
The XNOR symbol is denoted as ⊙ 1 1 0

Its Boolean operation is 𝑥 ʘ 𝑦 = 𝑥𝑦 + 𝑥 ′ 𝑦′

XNOR
The identities of the XOR operation are
given by:
𝑥⊕0 = 𝑥 𝑥 ⊕ 1 = 𝑥′
𝑥⊕𝑥 =0 𝑥 ⊕ 𝑥′ = 1 X Y Z
0 0 1
Commutative and associative: 0 1 0
1 0 0
A⊕𝐵 = 𝐵⊕𝐴
1 1 1
(A ⊕ 𝐵) ⊕ 𝐶 = 𝐴 ⊕ (𝐵 ⊕ 𝐶) = 𝐴 ⊕ 𝐵 ⊕ 𝐶
𝑥⊙𝑦 = 𝑥 ⊕ 𝑦
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 THEXORIMPLEMENTATION
• The output analysis for the first
circuit is very easy!

• The output at each of the NAND

gates for the second circuit is as
follows:

• At L1: 𝑥𝑦 = 𝑥 ′ + 𝑦′
L2

L1 L4

L3

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 THEXORIMPLEMENTATION
• The output analysis for the first
circuit is very easy!

• The output at each of the NAND

gates for the second circuit is as
follows:

• At L1: 𝑥𝑦 = 𝑥 ′ + 𝑦′ 𝒙 L2
𝒙′ + 𝒚′ 𝒙′ + 𝒚
• At L2: L4
L1
𝑥(𝑥 ′ + 𝑦 ′ ) = 𝑥𝑥 ′ + 𝑥𝑦 ′ = 𝑥𝑦 ′ = 𝑥 ′ + 𝑦
𝒙′ + 𝒚′ 𝒙 + 𝒚′
• At L3: 𝒚 L3
𝑦(𝑥 ′ + 𝑦 ′ ) = 𝑥 ′ 𝑦 + 𝑦𝑦 ′ = 𝑥 ′ 𝑦 = 𝑥 + 𝑦′

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 THEXORIMPLEMENTATION
• The output analysis for the first
circuit is very easy!

• The output at each of the NAND

gates for the second circuit is as
follows:

• At L1: 𝑥𝑦 = 𝑥 ′ + 𝑦′
L2
• At L2: L4
L1
𝑥(𝑥 ′ + 𝑦 ′ ) = 𝑥𝑥 ′ + 𝑥𝑦 ′ = 𝑥𝑦 ′ = 𝑥′ + 𝑦

• At L3: L3
𝑦(𝑥 ′ + 𝑦 ′ ) = 𝑥 ′ 𝑦 + 𝑦𝑦 ′ = 𝑥 ′ 𝑦 = 𝑥 + 𝑦′

• At L4:
(𝑥′+𝑦)(𝑥 + 𝑦′) = (𝑥 ′ + 𝑦) + (𝑥 + 𝑦′) = 𝑥𝑦 ′ + 𝑥 ′ 𝑦 = 𝑥 ⊕ 𝑦 14
 ARITHMETICCIRCUITS
• We will continue with the design of digital logic circuits
• One of the famous digital logic circuits is the calculator
• How to design it?

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 ARITHMETICCIRCUITS
• An arithmetic circuit is a 0+0= 0
combinational circuit that 0+1= 1 outputs one digit
performs arithmetic 1+0=1
operations such as: 1 + 1 = 10 outputs two digits!
• Addition
• Subtraction carry sum
• Multiplication
• Division

•A combinational circuit that So, we need two binary outputs to

performs the addition of two bits represent the addition block
is called a Half Adder (carry & sum)

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 HALFADDER
It isrequired to design a combinational circuit that adds two
binary numbers and produces the output in the form of two bits,
sum and carry
Solution:
1. We need to determine the inputs and output of the system
and give letters for all of them: Our system has two inputs
(x, y) and two outputs (S, C)

x S
Half Adder
y C

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 HALFADDER
2. Derive the truth table Inputs Outputs
according to the given
relation between inputs and x y C S
outputs 0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

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 HALFADDER
3. Obtain the simplified Boolean functions for each output as a
function of the input variables using a K-map

𝐶 = 𝑥𝑦 𝑆 = 𝑥𝑦 ′ + 𝑥 ′ 𝑦
=𝑥⊕𝑦
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 HALFADDER
4. Sketch the logic diagram

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 FULLADDER
It isrequired to design a combinational circuit that adds
three binary numbers and produces the output in the
form of two bits, sum and carry
Solution:
1. We need to determine the inputs and outputs of the
system and give letters for all of them: Our system has
three inputs (x, y, z) and two outputs (S, C)

x
S
y Full Adder
z C

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 FULLADDER
2. Derive the truth Inputs Outputs Decimal
table according to Equivalent
the given relation
between the inputs x y z C S
and outputs 0 0 0 0 0 0
0 0 1 0 1 1
0 1 0 0 1 1
0 1 1 1 0 2
1 0 0 0 1 1
1 0 1 1 0 2
1 1 0 1 0 2
1 1 1 1 1 3

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 FULLADDER
3. Obtain the simplified Boolean functions for each output as a
function of the input variables using a K-map

𝑆 = 𝑥 ′ 𝑦 ′ 𝑧 + 𝑥 ′ 𝑦𝑧 ′ + 𝑥𝑦 ′ 𝑧 ′ + 𝑥𝑦𝑧

Remember that:
𝑥⊙𝑦 = 𝑥 ⊕ 𝑦, 𝑥 ⊕ 𝑦 = 𝑥𝑦 ′ + 𝑥 ′ 𝑦, 𝑥⊙𝑦 = 𝑥𝑦 + 𝑥 ′ 𝑦 ′
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 FULLADDER
3. Obtain the simplified Boolean functions for each output as a
function of the input variables using a K-map

𝑆 = 𝑥 ′ 𝑦 ′ 𝑧 + 𝑥 ′ 𝑦𝑧 ′ + 𝑥𝑦 ′ 𝑧 ′ + 𝑥𝑦𝑧
= 𝑧 𝑥 ′ 𝑦 ′ + 𝑥𝑦 + 𝑧 ′ 𝑥 ′ 𝑦 + 𝑥𝑦 ′
= 𝑧(𝑥 ′ 𝑦 + 𝑥𝑦 ′ ) + 𝑧′(𝑥′𝑦 + 𝑥𝑦 ′ )

Remember that:
𝑥⊙𝑦 = 𝑥 ⊕ 𝑦, 𝑥 ⊕ 𝑦 = 𝑥𝑦 ′ + 𝑥 ′ 𝑦, 𝑥⊙𝑦 = 𝑥𝑦 + 𝑥 ′ 𝑦 ′
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 FULLADDER
3. Obtain the simplified Boolean functions for each output as a
function of the input variables using a K-map

𝑆 = 𝑥 ′ 𝑦 ′ 𝑧 + 𝑥 ′ 𝑦𝑧 ′ + 𝑥𝑦 ′ 𝑧 ′ + 𝑥𝑦𝑧
= 𝑧 𝑥 ′ 𝑦 ′ + 𝑥𝑦 + 𝑧 ′ 𝑥 ′ 𝑦 + 𝑥𝑦 ′
= 𝑧(𝑥 ′ 𝑦 + 𝑥𝑦 ′ ) + 𝑧′(𝑥′𝑦 + 𝑥𝑦 ′ )
= 𝑧 𝑥 ⊕ 𝑦 + 𝑧′ 𝑥 ⊕ 𝑦

Remember that:
𝑥⊙𝑦 = 𝑥 ⊕ 𝑦, 𝑥 ⊕ 𝑦 = 𝑥𝑦 ′ + 𝑥 ′ 𝑦, 𝑥⊙𝑦 = 𝑥𝑦 + 𝑥 ′ 𝑦 ′
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 FULLADDER
3. Obtain the simplified Boolean functions for each output as a
function of the input variables using a K-map

𝑆 = 𝑥 ′ 𝑦 ′ 𝑧 + 𝑥 ′ 𝑦𝑧 ′ + 𝑥𝑦 ′ 𝑧 ′ + 𝑥𝑦𝑧
= 𝑧 𝑥 ′ 𝑦 ′ + 𝑥𝑦 + 𝑧 ′ 𝑥 ′ 𝑦 + 𝑥𝑦 ′
= 𝑧(𝑥 ′ 𝑦 + 𝑥𝑦 ′ ) + 𝑧′(𝑥′𝑦 + 𝑥𝑦 ′ )
= 𝑧 𝑥 ⊕ 𝑦 + 𝑧′ 𝑥 ⊕ 𝑦
= 𝒛⊕ 𝒙⊕𝒚
= 𝒙⊕𝒚⊕𝒛

Remember that:
𝑥⊙𝑦 = 𝑥 ⊕ 𝑦, 𝑥 ⊕ 𝑦 = 𝑥𝑦 ′ + 𝑥 ′ 𝑦, 𝑥⊙𝑦 = 𝑥𝑦 + 𝑥 ′ 𝑦 ′
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 FULLADDER
3. Obtain the simplified Boolean functions for each output as a
function of the input variables using a K-map

𝐶 = 𝑥𝑦 + 𝑥𝑧 + 𝑦𝑧

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 FULLADDER
4. Sketch the logic diagram

𝑆 = 𝑥 ′ 𝑦 ′ 𝑧 + 𝑥 ′ 𝑦𝑧 ′ + 𝑥𝑦 ′ 𝑧 ′ + 𝑥𝑦𝑧 𝐶 = 𝑥𝑦 + 𝑥𝑧 + 𝑦𝑧
𝑆 = 𝑥⊕𝑦⊕𝑧 27
 FULLADDER
• The logic circuit for the full adder could also be sketched using
two half adders and a single OR gate
Half adder Half adder
𝑆 =𝑥⊕𝑦⊕𝑧

𝐶 = 𝑥 ⊕ 𝑦 𝑧 + 𝑥𝑦
= 𝑥𝑦 ′ + 𝑥 ′ 𝑦 𝑧 + 𝑥𝑦
Compare the obtained Boolean expression = 𝑥𝑦 ′ 𝑧 + 𝑥 ′ 𝑦𝑧 + 𝑥𝑦
for 𝐶 here and the one obtained in slide 28 28
 FULLADDER
• The logic circuit for the full adder could also be sketched using
two half adders and a single OR gate
Half adder Half adder
𝑆 =𝑥⊕𝑦⊕𝑧

𝐶 = 𝑥𝑦 ′ 𝑧 + 𝑥 ′ 𝑦𝑧 + 𝑥𝑦
𝐶 = 𝑥(𝑦 + 𝑦 ′ 𝑧) + 𝑥 ′ 𝑦𝑧
Compare the obtained Boolean expression 𝐶 = 𝑥(𝑦 + 𝑧) + 𝑥 ′ 𝑦𝑧
for 𝐶 here and the one obtained in slide 28 29
 FULLADDER
• The logic circuit for the full adder could also be sketched using
two half adders and a single OR gate
Half adder Half adder
𝑆 =𝑥⊕𝑦⊕𝑧

𝐶 = 𝑥𝑦 + 𝑥𝑧 + 𝑥 ′ 𝑦𝑧
𝐶 = 𝑥𝑦 + 𝑧(𝑥 + 𝑥 ′ 𝑦)
Compare the obtained Boolean expression 𝐶 = 𝑥𝑦 + 𝑧(𝑥 + 𝑦)
for 𝐶 here and the one obtained in slide 28 31
 FULLADDER
• The logic circuit for the full adder could also be sketched using
two half adders and a single OR gate
Half adder Half adder
𝑆 =𝑥⊕𝑦⊕𝑧

𝑪 = 𝒙𝒚 + 𝒙𝒛 + 𝒚𝒛

Compare the obtained Boolean expression

for 𝐶 here and the one obtained in slide 28 31
 4-BITBINARYRIPPLECARRYADDER
• Connecting n full adders in cascade allows us to add n-bit
binary numbers together
• Example:
Connecting 4 full adders in cascade allows usto add 1011 to
0011.

𝐴 = 𝐴3𝐴2𝐴1𝐴0
= 1 0 1 1
𝐵 = 𝐵3𝐵2𝐵1𝐵0
= 0 0 1 1

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 4-BITBINARYRIPPLECARRYADDER
𝑩𝟑 = 𝟎 𝑨𝟑 = 𝟏 𝑩𝟐 = 𝟎 𝑨𝟐 = 𝟎 𝑩𝟏 = 𝟏 𝑨𝟏 = 𝟏 𝑩𝟎 = 𝟏 𝑨𝟎 = 𝟏

𝟎 𝟏 𝟏
𝑪𝟎 = 𝟎

𝑪𝟒 = 𝟎 𝑺𝟑 = 𝟏 𝑺𝟐 = 𝟏 𝑺𝟏 = 𝟏 𝑺𝟎 = 𝟎

This adder is extremely

slow, as each stage must
wait for the previous one to
get the carry from it!
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 BINARYSUBTRACTOR
• The subtraction of binary numbers can be easily done using
complements
• The subtraction 𝐴 − 𝐵 is done by taking the 2’s complement of
𝐵 and adding it to 𝐴
•The 2’s complement can be obtained by taking the
1’s complement and adding 1 to the least significant bit (LSB)
• The 1’s complement can be implemented easily with an
inverter gate
•We can add 1 to the sum by making the initial input carry of
the parallel adder equal to 1

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SUBTRACTIONEXAMPLE

101 101 101

−011 + 100 + 100
+ 001 1001
1’s Complement
+ 001
2’s Complement
1𝟎𝟏𝟎

36
 This is equivalent
to 𝐴 plus the 2’s
BINARYADDER/SUBTRACTOR complement of 𝐵

• Subtractor 𝐴
𝑆
𝐵 FA
𝐶𝑜𝑢𝑡

𝐶𝑖𝑛 = 1

• Adder/Subtractor
𝐴
𝐵 𝑆
FA
𝐶𝑜𝑢𝑡
𝐶𝑖𝑛

If 𝐶𝑖𝑛 = 0, circuit acts as an Adder

If 𝐶𝑖𝑛 = 1, circuit acts as a Subtractor
Remember that 𝐵 ⊕ 0 = 𝐵
and 𝐵 ⊕ 1 = 𝐵′

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 BINARYMULTIPLIER

2 bits × 2 bits = max 4 bits

(11)2× (11)2= (1001)2

(3)10× (3)10= (9)10

𝐶 𝑆 𝐶 𝑆

𝑀3 𝑀2 𝑀1 𝑀0 𝑀3 𝑀2 𝑀1 𝑀0

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 DECODERS
•A Decoder is a combinational circuit that converts binary
information from 𝑛 input lines to a maximum of 2𝑛 unique
output lines
•If the 𝑛 −bit coded information has unused combinations,
the decoder may have fewer than 2𝑛 outputs
•Consider a vending machine that takes 3
bits as input and releases a single product,
out of the available 8 product sorts

Output
Input pad Vending select
Machine line

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 DECODERS
•It is required to design a combinational circuit with two
inputs (𝑎, 𝑏) and four outputs (𝐷0 , 𝐷1 , 𝐷2 , 𝐷3 ), such that:

• 𝐷0 = 1 when 𝑎 = 0 and 𝑏 = 0
• 𝐷1 = 1 when 𝑎 = 0 and 𝑏 = 1
• 𝐷2 = 1 when 𝑎 = 1 and 𝑏 = 0
• 𝐷3 = 1 when 𝑎 = 1 and 𝑏 = 1

39
 DECODERS
Solution
1. Fromthe specifications of the circuit, determine the
required number of inputsand outputs and assign a
letter (symbol) to each

𝐷0
𝑎 2×4 𝐷1
𝑏 Decoder 𝐷2
𝐷3

40
 DECODERS
2. Derive the truth table that defines the required
relationship between the inputsand outputs

Inputs Outputs

𝑎 𝑏 𝐷0 𝐷1 𝐷2 𝐷3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

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 DECODERS
3. Obtain the simplified Boolean functions for each output
as a function of the input variables
𝐷0 = 𝑎 ′ 𝑏 ′
𝑏
𝐷1 = 𝑎 ′ 𝑏 𝐷0

𝐷2 = 𝑎𝑏 ′
𝐷1
𝐷3 = 𝑎𝑏
4. Sketch the logic diagram
𝐷2
𝑎
𝐷3

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 𝐷0 = 𝑥′𝑦′𝑧′

3×8DECODER 𝑧 𝐷1 = 𝑥′𝑦 ′ 𝑧

𝐷2 = 𝑥 ′ 𝑦𝑧′
𝑦
•A 3 × 8 line decoder 𝐷3 = 𝑥 ′ 𝑦𝑧
decodes 3 input bits into
one of 8 possible outputs 𝑥
𝐷4 = 𝑥𝑦′𝑧′

•Each output represents 𝐷5 = 𝑥𝑦 ′ 𝑧

one of the minterms of
the 3 input variables 𝐷6 = 𝑥𝑦𝑧′

𝐷7 = 𝑥𝑦𝑧

43
 2×4DECODER
•A decoder could include an Enable input to control the
circuit operation
•A decoder could be 𝐷0
implemented with NAND
gates and thus produces the
𝐷1
minterms in their
𝐴
complemented form
𝐷2
𝐵

𝐷3
𝐸

44
 IMPLEMENTINGFUNCTIONS
USING DECODERS
•Any combinational circuit can be constructed using
decoders and OR gates (the decoder generates the
minterms and the OR gate performs the summation)
•Example: Implement a full adder circuit with a decoder
and two OR gates
• Full adder equations:
𝑆 𝑥, 𝑦, 𝑧 = Σ𝑚(1,2,4,7) and
𝐶 𝑥, 𝑦, 𝑧 = Σ𝑚(3,5,6,7)
• Since there are 3 inputs, we need a 3 × 8 decoder

45
 IMPLEMENTINGFUNCTIONS
USING DECODERS
• 𝑆 𝑥, 𝑦, 𝑧 = Σ𝑚(1,2,4,7) and Inputs Outputs

• 𝐶 𝑥, 𝑦, 𝑧 = Σ𝑚(3,5,6,7) 𝑥 𝑦 𝑧 𝐶 𝑆
0 0 0 0 0
0 0 1 0 1

𝑆 0 1 0 0 1
𝑥 0 1 1 1 0
𝑦 1 0 0 0 1
1 0 1 1 0
𝑧 𝐶
1 1 0 1 0
1 1 1 1 1
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 DECODEREXPANSIONS
•Larger decoders can be
𝑥
constructed using a 𝐷0 to 𝐷7
𝑦
number of smaller ones
𝑧
•For example, a 3 × 8
decoder can be built 𝑤
using a couple of 2 × 4
decoders and a 4 × 16 𝐷8 to 𝐷15
decoder can be built
using a couple of 3 × 8
decoders

4 × 16 Decoder
47
 EXERCISE
•Can you sketch a 4 × 16 decoder using a
number of 2 × 4 decoders?

48
 ENCODERS
•An encoder is a digital circuit that performs the inverse
operation of a decoder
• An encoder has 2𝑛 input lines and 𝑛 output lines
•The output lines generate the binary equivalent of the
input line whose value is 1

16
8×3OCTAL-TO-BINARYENCODER
What happens if more than one input is
𝑥 = 𝐷4 + 𝐷5 + 𝐷6 + 𝐷7 active (set to HIGH) at the same time?
𝑦 = 𝐷2 + 𝐷3 + 𝐷6 + 𝐷7 For example, 𝐷3 and 𝐷6?
𝑧 = 𝐷1 + 𝐷3 + 𝐷5 + 𝐷7
What happens if all inputs are equal to 0?

17
 8×3OCTAL-TO-BINARYENCODER
What happens if more than one input is active (set to HIGH) at
the same
time? For example, 𝐷3 and 𝐷6 ?
• If 𝐷3 and 𝐷6 are active simultaneously, the output would be
(111)2= (7)10, because all three outputs would be equal to 1
•But this does not reflect the actual input which should have
resulted in an output of (011)2= (3)10 for 𝐷3 or (110)2= (6)10
for 𝐷6
• To overcome this problem, we use priority encoders
•If we establish a higher priority for inputs with higher
subscript numbers, and if both 𝐷3 and 𝐷6 are active at the
same time, the output would be (110)2 because 𝐷6 has higher
priority than 𝐷3
𝑥 = 𝐷4 + 𝐷5 + 𝐷6 + 𝐷7
𝑦 = 𝐷2 + 𝐷3 + 𝐷6 + 𝐷7
𝑧 = 𝐷1+𝐷3 + 𝐷5 + 𝐷7 18
 8×3OCTAL-TO-BINARYENCODER
What happens if all inputs are 𝐷7𝐷6𝐷5𝐷4𝐷3𝐷2𝐷1𝐷 0
equal to 0?
•The encoder output would be 𝑧
(000)2 , but in fact this is the
output when 𝐷0 is equal to 1
𝑦
•This problem can be solved by
providing an extra output to 𝑥
indicate whether at least one input
is equal to 1
• 𝑣 is the valid output 𝑣

53
 MULTIPLEXERS
• A multiplexer is used to connect 2𝑛 points 𝑰𝟏 𝑰𝟎 𝑨 𝒁
to a single point
• The control signal pattern formsthe binary 0 0 0 0
index of the input to be connected to the 0 0 1 0
output 0 1 0 1
0 1 1 0
1 0 0 0
𝑍 = 𝐴′𝐼0 + 𝐴𝐼1 1 0 1 1
𝑨 𝒁
1 1 0 1
0 𝐼𝟎 𝐼𝟎 2×1 𝑍 1 1 1 1
1 𝐼𝟏 𝐼𝟏 MUX

Functional Logical
𝐴
form form
54
 MULTIPLEXERS

𝐼𝟎
𝐼𝟎 𝐼𝟏
𝐼𝟎 2×1 𝐼𝟏 4×1 𝐼𝟐
𝑍 𝑍 8×1 𝑍
𝐼𝟏 MUX 𝐼𝟐 MUX
𝐼𝟑 MUX
𝐼𝟑 𝐼𝟒
𝐴 𝐼𝟓
𝐴 𝐵 𝐼𝟔
𝐼𝟕

𝐴𝐵𝐶

55
2× 1LINEMULTIPLEXER

𝐼𝟎
𝐼𝟎
𝑍 𝑍
𝐼𝟏
𝐼𝟏

𝑆
𝑆

56
4× 1LINEMULTIPLEXER
𝐼𝟎

𝑺𝟎 𝑺𝟏 𝒁
𝐼𝟏
0 0 𝐼𝟎
𝑍
0 1 𝐼𝟏 𝐼𝟐

1 0 𝐼𝟐
𝐼𝟑
1 1 𝐼𝟑

Functional Can you sketch the logic

form diagram of an 8×1
multiplexer?
𝑆0
𝑆1 25
 8× 1LINEMULTIPLEXER
•I am now giving you 5 minutes to attempt sketching the
logic diagram of an 8×1 line multiplexer
• After these 5 minutes, the lecture will continue

58
8× 1LINEMULTIPLEXER

59
 MULTIPLEXERSASGENERAL-
PURPOSE LOGIC
• A 2𝑛 −1 : 1 multiplexer can implement any function of
𝑛 variables
• Steps:
1. The Boolean function is listed in a truth table
2. The first 𝑛 − 1 variables in the table are applied
to the selection inputs of the MUX
3. For each combination of the selection variables,
evaluate the output as a function of the last
variable
4. The values are then applied to the data inputs in
the proper order 60
MULTIPLEXERSASGENERAL-
PURPOSE LOGIC:EXAMPLEI
𝐹 𝑥, 𝑦, 𝑧 = Σ(1,2,6,7)

𝑦
𝑥

𝑧 𝐹
𝑧′
0
1

61
MULTIPLEXERSASGENERAL-
PURPOSE LOGIC:EXAMPLEII
𝐹 𝐴, 𝐵, 𝐶, 𝐷 = Σ(1,3,4,11,12,13,14,15)

𝐶
𝐵
𝐴

𝐷
𝐹

62