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Decoder Encoder

The document outlines various problems and solutions related to digital logic design, including the design of a 2x4 decoder using NOR gates, combinational circuits with NAND gates, and the implementation of Boolean expressions with multiplexers. It also covers the design of a full adder using multiplexers and the functionality of an 8x1 multiplexer. Additionally, it includes the design of a 4x2 priority encoder with specified priorities for inputs.

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7 views

Decoder Encoder

The document outlines various problems and solutions related to digital logic design, including the design of a 2x4 decoder using NOR gates, combinational circuits with NAND gates, and the implementation of Boolean expressions with multiplexers. It also covers the design of a full adder using multiplexers and the functionality of an 8x1 multiplexer. Additionally, it includes the design of a 4x2 priority encoder with specified priorities for inputs.

Uploaded by

attiafroty
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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IET Faculty

Dr.Tallal Elshabrawy& Dr.Wassim Alexan

ELCT201 Digital Logic Design


Sheet 6

Problem I: Design a 2×4 decoder using NOR gates only. Include an enable input.

Solution:

2x4 decoder Implementation:

NOR is
equivalent to
AND gate with
inverted
inputs.
Implementation using NOR Gates:

Problem II: Design a combinational circuit defined by the following three


Boolean functions:
𝐹1 (𝐴, 𝐵, 𝐶) = 𝛴⁡(2,4,7)

𝐹2 (𝐴, 𝐵, 𝐶) = 𝛴⁡(0,3)

F3(A, B, C) = Σ(0,2,3,4,7)

Implement the circuit using a decoder constructed with NAND gates and NAND or
AND gates connected to the decoder outputs.

Solution:

F1, F2 ,F3 are OR functions we need to get their equivalence using NAND gates.
OR is equivalent to NAND with inverted inputs.
Problem III: Implement the following Boolean expressions with a multiplexer
only:

𝐹1 (A, B, C, D) = Σ(0,1,3,4,8,9,15)
𝐹2 (𝑥, 𝑦, 𝑧) = 𝛴⁡(1,2,3,6,7)
𝐹3 (𝐴, 𝐵, 𝐶, 𝐷) = 𝛴⁡(1,3,4,5,10,11,12,13,14,15)

Solution:

𝑎)⁡ 𝐹1 (A, B, C, D) = Σ(0,1,3,4,8,9,15)


b) 𝐹2 (𝑥, 𝑦, 𝑧) = 𝛴⁡(1,2,3,6,7)
𝑐)𝐹3 (𝐴, 𝐵, 𝐶, 𝐷) = 𝛴⁡(1,3,4,5,10,11,12,13,14,15)

Problem IV: Implement a full adder using two 4×1 multiplexers.


Solution:

-Full adder
truth table.
-Implementation of sum and carry outputs of FA using 2x1 multiplexers:

0 0

1
Problem V: An 8×1 multiplexer has inputs A,B and C connected to the selection
inputs S2, S1and S0, respectively. The data inputs I0 through I7 are as follows:
I1=I2=I7=0; I3=I5=1; I0=I4=D and I6=D.
Determine the Boolean function that the multiplexer implements.
Solution:

I0=D D

0
I1=0
0
I2=0
1
D
I3=1 1

I4=D D

’ 0
I5=1
I6=D A B C
’’
I7 =0

=0
Problem VI: Design a 4*2 priority encoder, such that D3 would have the highest
priority, while D0 would have the lowest priority.
Solution:

10

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