Azg 1
Azg 1
2
How to Adjust the Rotating Phase of the
Gear, Main Cam
1) Push down the hooking catch of the CHAS. MECH, and
remove the TRAY.
2) Align the arrow mark of the Gear, Main Cam with the black
round mark of the CHAS, MECHA as shown below.
3) Confirm that the Slide, Mech Cam is located in the right
position, then insert the TRAY gently.
3
ELECTRICAL MAIN PARTS LIST
REF. NO PART NO. KANRI DESCRIPTION REF. NO PART NO. KANRI DESCRIPTION
NO. NO.
IC C203 87-010-188-080 CAP,CHIP 6800P
C204 87-012-156-080 C-CAP,S 220P-50 CH
87-A20-547-010 C-IC,CXA1992AR C205 87-010-183-080 C-CAP,S 2700P-50 B<SB3MD,SB3RNMD>
87-017-917-080 IC,BU4066BCF C205 87-010-186-080 CAP,CHIP 4700P<SB3RMDM,SB3RNMDM>
87-A20-546-010 C-IC,CXD2589Q C206 87-016-526-080 C-CAP,S 0.47-16 BK
87-A20-592-040 C-IC,M51943 AML
87-A20-445-010 IC,BA5936 C207 87-010-197-080 CAP, CHIP 0.01 DM
C209 87-012-154-080 C-CAP,S 150P-50 CH
87-001-792-080 IC,NJM2100M C210 87-012-154-080 C-CAP,S 150P-50 CH
C211 87-010-176-080 C-CAP,S 680P-50 SL
C212 87-010-176-080 C-CAP,S 680P-50 SL
TRANSISTOR
C213 87-010-402-080 CAP, ELECT 2.2-50V
89-406-555-080 TR,2SD655 (0.5W) C214 87-010-402-080 CAP, ELECT 2.2-50V
87-A30-071-080 C-TR,RT1N 144C C215 87-010-154-080 CAP CHIP 10P
87-026-609-080 TR,KTA1266GR C216 87-010-154-080 CAP CHIP 10P
87-026-239-080 TR,DTC114TK (0.2W) C217 87-010-263-080 CAP, ELECT 100-10V
87-A30-060-080 C-TR,KTC3875GR<SB3MD,SB3RMDM>
C218 87-010-197-080 CAP, CHIP 0.01 DM
87-A30-061-080 C-TR,KTA1504GR C219 87-010-196-080 CHIP CAPACITOR,0.1-25
C220 87-010-197-080 CAP, CHIP 0.01 DM
C221 87-010-197-080 CAP, CHIP 0.01 DM
DIODE C222 87-010-197-080 CAP, CHIP 0.01 DM
4
REF. NO PART NO. KANRI DESCRIPTION
NO.
CON901 87-009-345-010 CONN,2P PH H
L101 87-003-102-080 COIL, 10UH
L299 87-A50-189-080 C-COIL,S BLM21B272S
LED901 87-A40-558-010 LED,SLZ-8128A-01-A
M301 87-045-305-010 MOTOR, RF-500TB DC-5V (2MA)
LED C.B<SB3MD,SB3RMDM>
T-T C.B
SPINDLE C.B
DRIVE C.B
M2 87-045-356-010 MOT,RF-310TA 30
PIN3 87-A60-086-010 CONN,6P H6216-11
SW1 87-A90-042-010 SW,LEAF MSW-17310MVP0
• Regarding connectors, they are not stocked as they are not the initial order items.
The connectors are available after they are supplied from connector manufacturers upon the order is received.
5
TRANSISTOR ILLUSTRATION
B
ECB E
KTA1266 DTC114TK
2SD655 RT1N144C
KTA1504GR
KTC3875GR
6
BLOCK DIAGRAM
7 8
WIRING-1 (3CD/LED)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
K
9 10
SCHEMATIC DIAGRAM
LED DRIVER
LED
DRIVER
KSS-213F
11 12
WIRING-2 (T-T/MOTOR) WAVE FORM
1 2 3 4 5 6 7
1 IC201 Pin 70 , 71 (XTAI, XTAO) VOLT/DIV: 1V 4 IC101 Pin # (TA O) TIME/DIV: 1mS
SYSTEM CLOCK TIME/DIV: 0.1µS TRACKING
f=33.8688MHz
A
VC
3.4V
B 0
5 IC101 Pin 1 (FE O)
FOCUS SEARCH
2 TP1 (TP-RF) VOLT/DIV: 500mV
RF TIME/DIV: 0.5µS
C
CD: 1.0±0.2V VC
CD-RW: 1.0±0.2V
VC
K
13 14
IC BLOCK DIAGRAM
IC, BA5936S
IC, NJM2100M
15
IC DESCRIPTION
IC, CXA1992AR
Pin No. Pin Name I/O Description
Output terminal for focus error amplifier. Internally connected to window comparator
1 FEO O
input for bias condition.
2 FEI I Input terminal for focus error.
3 FDFCT I Capacitor connection terminal for time constant used when there is defect.
This pin is connected to GND via capacitor when high frequency gain of the focus
4 FGD I
servo is attenuated.
This is a pin where the time constant is externally connected to raise the low frequency
5 FLB I
gain of the focus servo.
6 FE_O O Focus drive output.
7 FEM I Focus amplifier inverted input pin.
This is a pin where the time constant is externally connected to generate the focus
8 SRCH I
search waveform.
This is a pin where the selection time constant is externally connected to set the
9 TGU I
tracking servo the high frequency gain.
This is a pin where the selection time constant is externally connected to set the
10 TG2 I
tracking high frequency gain.
11 FSET I Pin for setting peak of the phase compensator of the focus tracking.
12 TA_M I Tracking amplifier inverted input pin.
13 TA_O O Tracking drive output.
14 SL_P I Sled amplifier non-inverted input pin.
15 SL_M I Sled amplifier inverted input pin.
16 SL_O O Sled drive output.
The current which determines height of the focus search, track jump and sled kick is
17 ISET I
input with external resistance connected.
18 Vcc I Power supply.
19 LOCK I “L” setting starts sled disorder-prevention circuit. (Not pull-up resistance)
20 CLK I Clock input for serial data transfer from CPU. (No pull-up resistance)
21 XLT I Latch input from CPU. (No pull-up resistance)
22 DATA I Serial data input from CPU. (No pull-up resistance)
23 XRST I Reset system at “L” setting. (No pull-up resistance)
24 C_OUT O Signal output for track number counting.
FZC, DFCT1, TZC, BALH, TGH, FOH, or ATSC is output depending on the
25 SENS1 O
command from CPU.
26 SENS2 O DFCT2, MIRR, BALL, TGL or FOL is output depending on the command from CPU.
27 FOK O Output terminal for focus OK comparator.
28 CC2 I Input pin where the DEFECT bottom hold output is capacitance coupled.
DEFECT bottom-hold output terminal. Internally connected to interruption comparator
29 CC1 O
input.
30 CB I Connection terminal for DEFECT bottom-hold capacitor.
Connection terminal for MIRR hold-capacitor.
31 CP I
Anti-reverse input terminal for MIRR comparator.
16
Pin No. Pin Name I/O Description
32 RF_I I Input terminal by capacity combination of RF summing amplifier.
33 RF_O O Output terminal of RF summing amplifier. Checkpoint of Eye pattern.
Anti-reverse input terminal for RF summing amplifier.
34 RF_M I The gain of RF amplifier is decided by the connection resistance between RF_M and
RFO terminals.
This is a pin where the selection time constant is externally connected to control the
35 RFTC I
RF level.
36 LD O APC amplifier output terminal.
37 PD I APC amplifier input terminal.
RFI-V amplifier inverted input pin.
38, 39 PD1, PD2 I These pins are connected to the A+C and B+C pins of the optical pickup, receiving by
currents input.
40 FEBIAS I/O Bias adjustment pin of the focus error amplifier. (Not connected)
F and EIV amplifier inverted input pins.
41, 42 F, E I These pins are connected to the F and E of the optical pickup, receiving by current
input.
Gain adjustment pin of the I-V amplifier E. (When not in use of BAL automatic
43 EI —
adjustment)
44 VEE — GND connection pin.
45 TEO O Output terminal for tacking-error amplifier. Output E-F signal.
46 LPFI I BAL adjustment comparator input pin. (Input through LPF from TEO)
47 TEI I Input terminal for tracking error.
48 ATSC I Window-comparator input terminal for detecting ATSC.
49 TZC I Input terminal for tracking-zero cross comparator.
50 TDFCT I Capacitor connection pin for the time constant used when there is defect.
51 VC O Output terminal for DC voltage reduced to half of VCC+VEE.
52 FZC I Input terminal for focus-zero cross comparator.
17
IC, CXD2589Q
Pin No. Pin Name I/O Description
1, 20, 45, 60 VSS — GND.
2 LMUT O Lch-“0” detect flag. (Not connected)
3 RMUT O Rch-“0” detect flag. (Not connected)
4 SQCK I Clock input for SQSO read out.
5 SQSO O SubQ 80 bit serial output.
6 SENS O SENS signal output to CPU.
7 DATA I Serial data input from CPU.
8 XLAT I Latch input from CPU, Latch serial data at fall down.
9 CLOK I Clock input to serial data transfer from CPU.
10 SEIN I SENS input from SSP.
11 CNIN I Numbers of track jump are counted and input.
12 DATO O Serial data output to SSP.
13 XLTO O Serial-data latch output to SSP. Latch at fall down.
14 CLKO O Clock output for serial data transfer to SSP.
15 SPOA I Microcomputer expansion interface. (Input A)
16 SPOB I Microcomputer expansion interface. (Input B)
17 XLON O Microcomputer expansion interface. (Output)
18 FOK I Focus OK input terminal. Used for SENS output and servo-auto sequencer.
19, 46, 61, 80 VDD — Power supply. (+5V)
21 MDP O Servo control for spindle motor.
22 PWMI I External control input for spindle motor. (Not connected)
23 TEST I
TEST terminal. (Connected to GND)
24 TESI I
25 VPCO O Charge pump output for extensive EFM PLL.
26 VCKI I VCO2 oscillator input for extensive EFM PLL.
27 V16M O VCO2 oscillator output for extensive EFM PLL.
28 VCTL I VCO2 control voltage input for extensive EFM PLL.
29 PCO O Charge pump output for master PLL.
30 FILO O Filter (slave = digital PLL) output for master PLL.
31 FILI I Filter input for master PLL.
32 AVSS — Analog GND.
33 CLTV I VCO control voltage input for master.
34 AVDD — Analog power. (+5V)
35 RF I EFM signal input.
36 BIAS I Constant current input to asymmetry circuit.
37 ASYI I Comparison voltage input to asymmetry circuit.
38 ASYO O EFM full-swing output. (L=VSS, H=VDD)
39 LRCK O D/A interface, LR clock output f=FS.
40 LRCKI I LR clock input.
41 PCMD O D/A interface, serial data output. (2’s COMP, MSB first)
42 PCMDI I D/A interface, serial data input. (2’s COMP, MSB first)
18
Pin No. Pin Name I/O Description
43 BCK O D/A interface bit clock output.
44 BCKI I D/A interface bit clock input.
47 XUGF O XUGF output, MNT1 or RPCK output by switching command. (Not connected)
48 XPCK O XPLCK output, MNT0 output by switching command. (Not connected)
49 GFS O GFS output, MNT3 or XRAOF output by switching command.
50 C2PO O C2PO output, GTOP output by switching command. (Not connected)
51 XTSL I X’tal select input terminal, X’tal: 16.9344MHz = “L” 33.8688MHz = “H”.
4.2336MHz output, Output 1/4 divided frequency of VCKI at CAV-W mode.
52 C4M O
(Not connected)
53 DOUT O Digital Out connector output signal.
54 EMPH O “H” when the playback disc has emphasis. “L” when it does not.
55 EMPHI I De-emphasis ON/OFF, “H” when ON, “L” when OFF.
56 WFCK O WFCK output. (Not connected)
57 SCOR O H output when the subcode sync S0 or S1 is detected. (Not connected)
58 SESO O Serial output for SubP-W. (Not connected)
59 EXCK I SBSO read out clock input.
62 SYSM I Mute input terminal, Active the “H” setting.
63 AVSS — Analogue GND.
64 AVDD — Analogue power supply. (+5V)
65 AOUT1 O Lch/analogue output terminal.
66 AIN1 I Lch/OP AMP input terminal.
67 LOUT1 O Lch/LINE output terminal.
68 AVSS — Analogue GND.
69 XVDD — Power supply for master clock.
Input terminal for crystal oscillator circuit.
70 XTAI I
Input external master clock from this terminal.
71 XTAO O Output terminal for crystal oscillator circuit.
72 XVSS — GND terminal for master clock.
73 AVSS — Analogue GND.
74 LOUT2 O Rch/LINE output terminal.
75 AIN2 I Rch/OP AMP input terminal.
76 AOUT2 O Rch/analogue output terminal.
77 AVDD — Analogue power supply. (+5V)
78 AVSS — Analogue GND.
79 XRST I Reset system at “L” setting.
Note)
• PCMD is the two’s complement output with MSB first.
• GTOP monitors the protection status of the Frame Sync. (H: Sync protection window opened).
• XUGF is the Frame Sync negative pulse which is obtained from the EFM signal. This is the signal before the sync protection.
• XPLCK is the inverted signal of the EFM PLL clock. The PLL works so that the fall-down edge and the changed point of the
EFM signal agree.
• GFS is the signal that goes “H” when the Frame Sync and the internally inserted timing agree.
• RFCK is the signal having 136 micro-seconds (during normal speed) that is generated to have the same accuracy as X’tal.
• C2PO is the signal indicating the error status of the data.
• XRAOF is the signal that is generated when the 16k RAM goes outside the jitter margin ±4F.
19
MECHANICAL EXPLODED VIEW 1/1
28 29
30 A
14 27
26
13
31
25
19
24 20
P.C.B
23
21
12 22
11
B a
a
10
9 32
SH, 2.5-40-0.5 PC
34
LED 901
4 35
8
18
7
6
AZA-9
17
3 5
4
P.C.B
CUSHION,CD A
1 16
CUSHION,
CD A
15
CUSHION,CD A 15
3ZG-2
33
20
MECHANICAL PARTS LIST 1/1
REF. NO PART NO. KANRI DESCRIPTION REF. NO PART NO. KANRI DESCRIPTION
NO. NO.
1 84-ZG1-225-010 BELT,SQ1.0-63.3 22 83-ZG3-213-010 LVR,SW
2 84-ZG1-672-010 F-CABLE,5P 1.25 210MM WHITE N 23 84-ZG1-266-010 LEVER,CAN 8
3 87-045-364-010 MOTOR(BCH3B14) 24 84-ZG1-205-210 GEAR,TRAY (*)
4 84-ZG1-267-010 PULLEY,LOAD MO 8 25 81-ZG1-291-110 GEAR,TRAY RELAY NO3
<EXCEPT SB3RMD,SB3RNMD> 26 84-ZG1-274-010 GEAR,RELAY 8
4 81-ZG1-212-010 PULLY,LOAD MO<SB3RMD,SB3RNMD>
27 84-ZG1-207-010 PULLEY,RELAY
5 84-ZG1-238-010 GEAR,WORM N 28 84-ZG1-209-010 BELT,SQ1.8-117.7
6 84-ZG1-248-010 SPR-C,WORM 29 84-ZG1-203-410 GEAR,MAIN CAM
7 84-ZG1-239-210 PULLY,WORM N <YSB3RNMDM,SB3RNMDM,SB3RNMD>
8 8A-ZG1-001-010 TRAY,NO3 BLU 29 84-ZG1-215-410 GEAR,MAIN CAM BLU
9 84-ZG1-291-110 HLDR,MAGNET 4 NAT <SB3RMD,SB3RMDM,YSB3RNMDM>
<YSB3RNMDM,SB3RNMDM,SB3RNMD> 30 84-ZG1-011-010 REFLECTOR,CD
<SB3RMD,SB3RMDM,YSB3RNMDM>
9 84-ZG1-272-110 HLDR,MAGNET N 4
<SB3RMD,SB3RMDM,YSB3RNMDM> 31 84-ZG1-216-310 SLIDE,MECHA CAM YEL
10 84-ZG1-259-010 SPR-P,WORM <SB3RMD,SB3RMDM,YSB3RNMDM>
11 84-ZG1-269-010 GEAR,MAIN TT 4 31 84-ZG1-204-310 SLIDER,MECHA CAM
12 84-ZG1-224-010 LEVER,TT <YSB3RNMDM,SB3RNMDM,SB3RNMD>
<SB3RMD,SB3RMDM,YSB3RNMDM> 32 84-ZG1-201-410 CHAS,MECHA
12 84-ZG1-288-010 LEVER,TT NAT <SB3RMD,SB3RMDM,YSB3RNMDM>
<YSB3RNMDM,SB3RNMDM,SB3RNMD> 32 84-ZG1-286-010 CHAS,MECHA NAT
<YSB3RNMDM,SB3RNMDM,SB3RNMD>
13 8A-ZG1-002-010 TURN TABLE,NO1 BLU 33 84-ZG1-630-010 CABLE FFC 6P-1.25
14 81-ZG1-239-010 S-SCREW,TT
15 81-ZG1-271-010 S-SCREW MECH REAR 34 84-ZG1-244-310 CABI,OPTICAL
16 85-NFT-611-110 FF-CABLE 16P-1.0 35 84-ZG1-261-010 LID,OPTICAL
17 84-ZG1-287-010 HLDR,MECHA NAT A 87-067-703-010 TAPPING SCREW, BVT2+3-10
<YSB3RNMDM,SB3RNMDM,SB3RNMD> <SB3RMD,SB3RMDM,YSB3RNMDM>
B 87-067-981-010 BVT2+3-6 BLK
17 84-ZG1-212-210 HLDR,MECHA NO2
<SB3RMD,SB3RMDM,YSB3RNMDM>
18 87-045-305-010 MOTOR, RF-500TB DC-5V (2MA)
19 84-ZG1-211-010 SPR-E CAM S
20 81-ZG1-255-110 PLATE,MAGNET MK2
21 83-ZG3-604-010 RING,MAG 2
21
CD MECHANISM EXPLODED VIEW 1/1
3
1
A
6 M2
SW1
5
P.C.B
6 83-ZG2-253-010 SHAFT,SLIDE 5
A 87-261-032-210 V+2-3
22
REFERENCE NAME LIST
ELECTRICAL SECTION MECHANICAL SECTION
DESCRIPTION REFERENCE NAME DESCRIPTION REFERENCE NAME
WHL WHEEL
WORM-WHL WORM-WHEEL
23
2–11, IKENOHATA 1–CHOME, TAITO-KU, TOKYO 110-8710, JAPAN TEL:03 (3827) 3111
0251431 Printed in Singapore