Gate-Level Minimization

Prof. Wangrok Oh

Dept. of Information Communications Eng.

Chungnam National University

Prof. Wangrok Oh(CNU) 1 / 67

Overview

1 Introduction

2 The Map Method

3 Product-of-Sums Simplification

4 Don’t-Care Conditions

5 NAND and NOR Implementation

6 Other Two-Level Implementations

7 Exclusive-OR Function

8 Hardware Description Language

Prof. Wangrok Oh(CNU) 2 / 67

Introduction

Gate-level minimization is the design task of finding an optimal

gate-level implementation of the Boolean functions
This task is difficult when the logic has more than a few inputs
Computer-based logic synthesis tools can minimize a large set of
Boolean equations efficiently and quickly
It is important that a designer understand the underlying
mathematical description and solution of the problem

Prof. Wangrok Oh(CNU) Introduction 3 / 67

The Map Method

Although the truth table of a function is unique, the function can be

expressed in many different but equivalent forms
The map method provides a simple and straightforward procedure
for minimizing Boolean functions
This method may be regarded as a pictorial form of a truth table
The map method is also known as the Karnaugh map or K-map
K-map is a diagram made up of squares and each square represents
one minterm of the function to be minimized

Prof. Wangrok Oh(CNU) The Map Method 4 / 67

The Map Method

Any Boolean function can be expressed as a sum of minterms →

Boolean function is recognized graphically in the map from the area
enclosed by those squares whose minterms are included in the
function
The map presents a visual diagram of all possible ways a function
may be expressed in standard form
By recognizing various patterns, the user can derive alternative
algebraic expressions from which the simplest can be selected
The simplified expressions produced by the map are always in one of
the two standard forms: sum of products or product of sums
The simplest algebraic expression has a minimum number of terms
and with the smallest possible number of literals in each term
This expression produces a circuit diagram with a minimum number
of gates and the minimum number of inputs to each gate

Prof. Wangrok Oh(CNU) The Map Method 5 / 67

 m3, a 1 is placed inside the square that belongs to m3. Similarly, the function x + y is
Therepresented
Map Method
in the map of Fig. 3.2(b) by three squares marked with 1’s. These squares
are found from the minterms of the function:

m1 + m2 + m3 = x!y + xy! + xy = x + y
Two-Variable K-Map
y
y
x 0 1
m0 m1
m0 m1 0 x!y! x!y
m2 m3
m2 m3 x 1 xy! xy

(a) (b)

FIGURE 3.1
Two-variable K-map for two variables → The map consists of 4 squares
4 minterms
The map is redrawn in (b) to show the relationship between the
squares and the two variables x and y
Two-variable map becomes another useful way to represent any one
of the 16 Boolean functions of two variables

Prof. Wangrok Oh(CNU) The Map Method 6 / 67

 The Map Method

Section 3.2 The Map Method 75

y y
y y
x 0 1 x 0 1
m0 m1 m0 m1 y
0 0 1
m2 m3 m2 m3
x 1 1 x 1 1 1

x
(a) xy (b) x ! y

FIGURE 3.2
For (b), m1 + m2 + m3 = x0 y + xy 0 + xy = x + y
Representation of functions in the map

The three squares could also have been determined from the intersection of variable
x in the second row and variable y in the second column, which encloses the area
belonging to x or y. In each example, the minterms at which the function is asserted are
marked with a 1.

Three-Variable K-Map
Prof. Wangrok Oh(CNU) The Map Method 7 / 67
 numbers are concatenated, they give the binary number 101, whose decimal equivalent
is 5. Each cell of the map corresponds to a unique minterm, so another way of looking at
The Map Method
square m5 = xy!z is to consider it to be in the row marked x and the column belonging
to y!z (column 01). Note that there are four squares in which each variable is equal to 1
and four in which each is equal to 0. The variable appears unprimed in the former four
Three-Variable K-Map
y
yz
x 00 01 11 10
m0 m1 m3 m2
m0 m1 m3 m2 0 x"y"z" x"y"z x"yz x"yz"
m4 m5 m7 m6
m4 m5 m7 m6 x 1 xy"z" xy"z xyz xyz"

z
(a) (b)

FIGURE 3.3
Three-variable
8 minterms K-map
forthree binary variables → The map consists of 8
squares
Note that the minterms are arranged not in a binary sequence but in
a sequence similar to the Gray code
Only one bit changes in value from one adjacent column to the next
There are 4 squares in which each variable is equal to 1 and 4 in
which each is equal to 0
Any two adjacent squares in the map differ by only one variable

Prof. Wangrok Oh(CNU) The Map Method 8 / 67

EXAMPLE
The Map 3.1 Method
Simplify the Boolean function
The sum of two minterms
F (x, y, z) in
= adjacent
"(2, 3, 4,squares
5) can be simplified to a
single product term consisting of only two literals
First, a 1 is marked in each minterm square that represents the function. This is shown
in Fig. 3.4, in which the squares
m5 +form7minterms
= xy 0 z +010,
xyz011,
=100, and
xz(y 0 101 are marked with 1’s.
+ y) = xz
The next step is to find possible adjacent squares. These are indicated in the map by two
shaded rectangles,
Any twoeach enclosing
minterms intwo 1’s. Thesquares
adjacent upper right rectangle
(vertically orrepresents the but
horizontally area
enclosed by x!y. This area is determined by observing that the two-square area is in row
not diagonally) that are ORed together will cause a removal of the
0, corresponding to x!, and the last two columns, corresponding to y. Similarly, the lower
dissimilar variable
left rectangle represents the product term xy!. (The second row represents x and the
two left columns represent y!.) The sum of four P minterms can be replaced by a sum of
Example (Simplify F (x, y, z) = (2, 3, 4, 5))
y
yz x!y
x
00 01 11 10
m0 m1 m3 m2
0 1 1
m4 m5 m7 m6
x 1 1 1

z
xy!

FIGURE 3.4
F = xy 0 + x0 y
Map for Example 3.1, F (x, y, z) = "(2, 3, 4, 5) = x!y + xy!

Prof. Wangrok Oh(CNU) The Map Method 9 / 67

EXAMPLE 3.2
TheSimplify
MaptheMethod
Boolean function
F (x, y, z) = "(3, 4, 6, 7)
Two squares are considered to be adjacent even though they do not
The map for this function
touch each otheris shown in Fig. 3.5. There are four squares marked with 1’s,
one for each
m0minterm of thetofunction.
is adjacent m2 andTwom4adjacent squares
is adjacent to m are combined in the third
6 because their
column to give a two-literal term yz. The remaining two squares with 1’s are also adja-
minterms differ by one variable
cent by the new definition. These two squares, when combined, give the two-literal term
m0 + mthen
xz!. The simplified function 2 = x0 y 0 z 0 + x0 yz 0 = x0 z 0 (y 0 + y) = x0 z 0
becomes
0 0
m4 + m6 = F xy z + xyz 0 = xz 0 (y 0 + y) = xz 0
= yz + xz!
P
Example (Simplify F (x, y, z) = (3, 4, 6, 7))
y
yz
x 00 01 11 10
m0 m1 m3 m2 yz
0 1

m4 m5 m7 m6
x 1 1 1 1

z
xy!z! xyz!
Note: xy!z! " xyz! # xz!

FIGURE 3.5
F = yz + xz 0
Map for Example 3.2, F (x, y, z) = "(3, 4, 6, 7) = yz + xz! ■

Prof. Wangrok Oh(CNU) The Map Method 10 / 67

The Map Method

Consider any combination of 4 adjacent squares in the three-variable

map
Any such combination represents the logical sum of 4 minterms →
An expression with only one literal
m0 + m2 + m4 + m6 = x0 y 0 z 0 + x0 yz 0 + xy 0 z 0 + xyz 0
= x0 z 0 (y 0 + y) + xz 0 (y 0 + y)
= x0 z 0 + xz 0 = z 0 (x + x0 ) = z 0

The number of adjacent squares that may be combined must always

represent a number that is a power of two
As more adjacent squares are combined, we obtain a product term
with fewer literals
1 1 square: One minterm giving a term with three literals
2 2 adjacent squares: A term with two literals
3 4 adjacent squares: A term with one literal
4 8 adjacent squares: Encompass the entire map and produce a
function that is always equal to 1

Prof. Wangrok Oh(CNU) The Map Method 11 / 67

 first and last columns to give the single literal term z!. The remaining single square,
representing minterm 5, is combined with an adjacent square that has already been used
The Map Method
once. This is not only permissible, but rather desirable, because the two adjacent squares
give the two-literal term xy! and the single square represents the three-literal minterm
xy!z. The simplified function is P
Example (Simplify F (x, y, z) =
F = z! + xy!
(0, 2, 4, 5, 6))
y
yz
x 00 01 11 10
y!z!
m0 m1 m3 m2 yz!
0 1 1

m4 m5 m7 m6
x 1 1 1 1

z
xy!
Note: y!z! " yz! # z!

FIGURE 3.6 F = z 0 + xy 0
Map for Example 3.3, F (x, y, z) = "(0, 2, 4, 5, 6) = z! + xy!

If a function is not expressed in sum-of-minterms form, it is possible ■

to use the map to obtain the minterms of the function
Each product term can be plotted in the map in 1, 2 or more squares
The minterms of the function are then read directly from the map

Prof. Wangrok Oh(CNU) The Map Method 12 / 67

 F (A, B, C ) = "(1, 2, 3, 5, 7)
The Map Method
he sum-of-products expression, as originally given, has too many terms. It can
mplified, as shown in the map, to an expression with only two terms:
F = C + 0 A!B
Example (F = A0 C + A0 B + AB C + BC)
B
BC A!B
A 00 01 11 10
m0 m1 m3 m2
0 1 1 1
m4 m5 m7 m6
A 1 1 1

C
C

FIGURE 3.7 X
F !=AB!C !
Map of Example 3.4, A!C ! A!B (1, BC
2, 3,"5, C
7) ! A!B
0
= C +A B

Prof. Wangrok Oh(CNU) The Map Method 13 / 67

 Four adjacent squares represent a term with two literals.
Eight adjacent squares represent a term with one literal.
The Map Method Sixteen adjacent squares produce a function that is always equal to 1.
No other combination of squares can simplify the function. The next two examples
show the procedure used to simplify four-variable Boolean functions.
Four-Variable K-Map
y
yz
wx 00 01 11 10
m0 m1 m3 m2

m0 m1 m3 m2 00 w!x!y!z! w!x!y!z w!x!yz w!x!yz!

m4 m5 m7 m6

m4 m5 m7 m6 01 w!xy!z! w!xy!z w!xyz w!xyz!

m12 m13 m15 m14

x

m12 m13 m15 m14 11 wxy!z! wxy!z wxyz wxyz!

w m8 m9 m11 m10

m8 m9 m11 m10 10 wx!y!z! wx!y!z wx!yz wx!yz!

z
(a) (b)

FIGURE 3.8
Four-variable
There aremap
16 minterms and each square assigned to one of midterms
The rows and columns are numbered in a Gray code sequence
Only one digit changing value between two adjacent rows or columns

Prof. Wangrok Oh(CNU) The Map Method 14 / 67

 Since the function has four variables, a four-variable map must be used. The minterms
listed in the sum are marked by 1’s in the map of Fig. 3.9. Eight adjacent squares marked
The Map Method
with 1’s can be combined to form the one literal term y". The remaining three 1’s on the
right cannot be combined to give a simplified term; they must be combined as two or
four adjacent squares. The larger the number of squares combined, the smaller is the
numberCombination
of literals in theof adjacent
term. squaresthe top two 1’s on the right are combined
In this example,
with the top1 two 1’s on the
1 square left to give
represents: Onetheminterm
term w"z"with
. Note4 that it is permissible to use
literals
the same square more thansquares:
2 2 adjacent once. WeA areterm
now with
left with a square marked by 1 in the third
3 literals
row and fourth column (square
3 4 adjacent squares:1110). Instead
A term withof taking this square alone (which will
2 literals
give a term4with four literals),
8 adjacent we combine
squares: A termit with
with squares
1 literalalready used to form an area
of four adjacent
5 16 squares.
adjacent These squares
squares make a
produce upfunction
the two middle
that isrows andequal
always the two
toend
1
columns, giving the term xz". The simplified function is
P + w"z" + xz"
Example (F (w, x, y, z) =F = y"(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14))
y
yz
wx
00 01 11 10
w!y!z! m0 m1 m3 m2
00 1 1 1
w!yz!
m4 m5 m7 m6
01 1 1 1
m12 m13 m15 m14
x
11 1 1 1 xyz!
xy!z!
w m8 m9 m11 m10
10 1 1

z
y!
FNote: y 0 + "ww!yz!
= w!y!z! 0
z +#xz 0
w!z!
xy!z! " xyz! # xz!

FIGURE
Prof. Wangrok 3.9
Oh(CNU) The Map Method 15 / 67
 The Map Method
hapterExample
3 Gate-Level
(F =Minimization
A0 B 0 C 0 + B 0 CD0 + A0 BCD0 + AB 0 C 0 )
A!B!C!
C
CD
AB 00 01 11 10
A!B!C!D!
m0 m1 m3 m2
A!B!CD!
00 1 1 1
m4 m5 m7 m6
01 1 A!CD!

m12 m13 m15 m14 B

11
A m8 m9 m11 m10
10 1 1 1
AB!CD!
AB!C!D! D AB!C!
Note: A!B!C!D! " A!B!CD! 0# A!B!D!
B 0 C 0 +"BAB!CD!
F =AB!C!D! 0 0
D +A # CD
0
AB!D!
A!B!D! " AB!D! # B!D!
A!B!C! " AB!C! # B!C!
Prof. Wangrok Oh(CNU) The Map Method 16 / 67
The Map Method

Prime Implicants
In choosing adjacent squares in a map, we must ensure that
1 All the minterms are covered when we combine the squares
2 The number of terms in the expression is minimized
3 There are no redundant terms (minterms covered by other terms)
Sometimes there may be two or more expressions that satisfy the
criteria
The procedure for combining squares may be made more systematic
if we understand the meaning of two special types of terms
1 Prime implicant: Product term obtained by combining the maximum
possible number of adjacent squares
2 If a minterm is covered by only one prime implicant, that prime
implicant is said to be essential
The prime implicants can be obtained by combining all possible
maximum numbers of squares

Prof. Wangrok Oh(CNU) The Map Method 17 / 67

 adjacent squares, and this gives the second term BD. The two essential prime implicants
cover eight minterms. The three minterms that were omitted from the partial map
The Map Method (m3, m9, and m11) must be considered next.
Figure 3.11(b) shows all possible ways that the three minterms can be covered with
prime implicants. Minterm m3 can be covered with either prime implicant CD or prime
implicant B"C. Minterm m9 can be covered with either AD or AB". Minterm m11 is
covered with any one of theX four prime implicants. The simplified expression is obtained
F (A,
from B, C,
the logical D)
sum = two essential
of the (0, 2, 3, 5, 7,
prime 8, 9, 10,
implicants and11,
any13, 15) implicants
two prime

C C
CD CD
AB 00 01 11 10 AB 00 01 11 10
m0 m1 m3 m2 A!B!CD! m0 m1 m3 m2
00 1 1 00 1 1 1

A!B!C!D! m4 m5 m7 m6
CD m4 m5 m7 m6
01 1 1 AD 01 1 1
BD
m12 m13 m15 m14 B m12 m13 m15 m14 B B!C
11 1 1 11 1 1
A m8 m9 m11 m10
A m8 m9 m11 m10
10 1 1 10 1 1 1 1
AB!CD!
AB!C!D! D D
Note: A!B!C!D! " A!B!CD! # A!B!D! AB!
AB!C!D! " AB!CD! # AB!D!
A!B!D! " AB!D! # B!D!
(a) Essential prime implicants (b) Prime implicants CD, B!C,
BD and B!D! AD, and AB!

FIGURE 3.11
Simplification
In (a), using prime
two essential primeimplicants
implicants having only two literals
Omitted minterms m3 , m9 , m11 must be considered next
m3 can be covered with CD or BC 0
m9 can be covered with AD or AB 0
m11 can be covered with AD or AB 0 or CD or B 0 C

Prof. Wangrok Oh(CNU) The Map Method 18 / 67

The Map Method

Simplified expression is obtained from the sum of two essential prime

implicants and any two prime implicants cover m3 , m9 , m11
4 possible expressions for F

F = BD + B 0 D0 + CD + AD
= BD + B 0 D0 + CD + AB 0
= BD + B 0 D0 + B 0 C + AD
= BD + B 0 D0 + B 0 C + AB 0

The procedure for finding the simplified expression

1 Determine all the essential prime implicants
2 Find a logical sum of all essential prime implicants + other prime
implicants that may be needed to cover any remaining minterms
There may be more than one way of combining squares and each
combination may produce an equally simplified expression

Prof. Wangrok Oh(CNU) The Map Method 19 / 67

The Map Method

Five-Variable Map
Maps for more than four variables are not as simple to use as maps
for four or fewer variables
A five-variable map needs 32 squares and a six-variable map needs 64
squares
When the number of variables becomes large, it is not easy to find a
simplified expression

Prof. Wangrok Oh(CNU) The Map Method 20 / 67

Product-of-Sums Simplification

The minimized Boolean functions derived from the map in all

previous examples were expressed in sum-of-products form
With a minor modification, the product-of-sums form can be
obtained
The minterms not included in the standard sum-of-products form
denote the complement of the function
The complement of a function is represented in the map by the
squares not marked by 1’s
If we mark the empty squares by 0’s and combine them into valid
adjacent squares, we obtain a simplified sum-of-products expression
of F 0
The complement of F 0 gives us back F in product-of-sums form
(DeMorgan’s theorem)
The function obtained is in product-of-sums form

Prof. Wangrok Oh(CNU) Product-of-Sums Simplification 21 / 67

 Applying DeMorgan’s theorem (by taking the dual and complementing each
literal as described in Section 2.4), we obtain the simplified function in product-
Product-of-Sums Simplification
of-sums form:
(b) F = (A" + B") (C" + D") (B" + D) P
Example (Simplify F (A, B, C, D) = (0, 1, 2, 5, 8, 9, 10)) ■
The gate-level
1 Sumimplementation of theFsimplified
of Products form: =BD + expressions
B C + Aobtained
0
C D in Example 3.7 is
0 0 0 0 0

shown in Fig. 3.13. The of

2 Product sum-of-products
Sums form: expression is implemented in (a) with a group of
AND gates, one forCombining
each ANDsquares
term. The outputs
marked withof theFAND
0’s: 0 = ABgates
+ CDare+ connected
BD0 to the
inputs of a single OR gate. The
Applying same function
DeMorgan’s is implemented
theorem → F = (A in
0 + (b)
0
in its+product-of-sums
B )(C 0 D0 )(B 0 + D)

C
CD
AB 00 01 11 10
m0 m1 m3 m2 CD
00 1 1 0 1 BCD!
BC!D! m4 m5 m7 m6
01 0 1 0 0
m12 m13 m15 m14 B
11 0 0 0 0
A m8 m9 m11 m10
10 1 1 0 1 AB

D
Note: BC!D! " BCD! # BD!

FIGURE 3.12
Prof. Wangrok Oh(CNU) Product-of-Sums Simplification 22 / 67
Product-of-Sums Simplification
Gate-level implementation of sum-of-products
1 Implemented with a group of AND gates
2 Each AND gate is for each product term
3 The outputs of the AND gates are connected to the inputs of a
single OR gate
Gate-level implementation of product-of-sums
1 Implemented with a group of OR gates
2 Each OR gate is for each sum term
3 The outputs of the OR gates are connected to the inputs of a single
86 Chapter
AND 3 Gate-Level Minimization
gate
B! A!

D! B!

C!
F F
C! D!

A!
D D
(a) F " B!D! # B!C! # A!C!D (b) F " (A! # B!) (C! # D!) (B! # D)

FIGURE 3.13
Gate implementations
Prof. Wangrok Oh(CNU) of the function
Product-of-Sums of Example 3.7
Simplification 23 / 67
Product-of-Sums Simplification
The procedure is also valid when the function is originally expressed
in the product-of-maxterms canonical form

Example (F (x, y, z) = Section

(1, 3.4
3, 4,Product-of-Sums Simplification 87
P
6))
y
yz
x 00 01 11 10
m0 m1 m3 m2
x!z
0 0 1 1 0
m4 m5 m7 m6
x 1 1 0 0 1

xz!

FIGURE 3.14 Q
F (x, y, z)
Map for the function of Table 3.1
= (0, 2, 5, 7)
For the sum-of-products, we combine the 1’s: F = x0 z + xz 0
For the product-of-sum, we combine the 0’s:: F 0 = xz + x0 z 0
In product-of-maxterms form, it is expressed
Take the complement of F 0 : F as
= (x0 + z 0 )(x + z)
F (x, y, z) = !(0, 2, 5, 7)
In other
Prof. words,
Wangrok Oh(CNU)the 1’s of the function represent
Product-of-Sums the minterms and the 0’s represent
Simplification 24 / 67
Don’t-Care Conditions

The sum of the minterms associated with a Boolean function

specifies the conditions under which the function is equal to 1
The function is equal to 0 for the rest of the minterms
In some applications, the function is not specified for certain
combinations of the variables
Functions that have unspecified outputs for some input
combinations are called incompletely specified functions
It is customary to call the unspecified minterms of a function
don’t-care conditions
These don’t-care conditions can be used on a map to provide further
simplification of the Boolean expression
A don’t-care minterm is a combination of variables whose logical
value is not specified
To distinguish the don’t-care condition from 1’s and 0’s, an X is used

Prof. Wangrok Oh(CNU) Don’t-Care Conditions 25 / 67

Don’t-Care Conditions
In choosing adjacent squares, the don’t-care minterms may be
assumed to be either 0 or 1
P
Example (Simplify F (w, x,P
y, z) = (1, 3, 7, 11, 15) which has
don’t-care conditions d = (0,Section 3.5 Don’t-Care Conditions
2, 5)) 89

y y
yz yz
wx 00 01 11 10 wx 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 X 1 1 X 00 X 1 1 X
w!x!
m4 m5 m7 m6
w!z m4 m5 m7 m6
01 0 X 1 0 01 0 X 1 0
m12 m13 m15 m14
x m12 m13 m15 m14
x
11 0 0 1 0 11 0 0 1 0
w m8 m9 m11 m10
w m8 m9 m11 m10
10 0 0 1 0 10 0 0 1 0

z z
yz yz
(a) F " yz # w!x! (b) F " yz # w!z

FIGURE 3.15
Example with don’t-care conditions
Prof. Wangrok Oh(CNU) Don’t-Care Conditions 26 / 67
Don’t-Care Conditions

Consider two simplified expressions

F = yz + w0 x0 =
P
(0, 1, 2, 3, 7, 11, 15)
F = yz + w0 z =
P
(1, 3, 5, 7, 11, 15)

Both expressions include minterms 1, 3, 7, 11 and 15 that make F

equal to 1
The don’t-care minterms 0, 2, and 5 are treated differently in each
expression
The two expressions represent two functions that are not
algebraically equal
Both cover the specified minterms of the function, but each covers
different don’t-care minterms
As far as the incompletely specified function is concerned, either
expression is acceptable because the only difference is in the value of
F for the don’t-care minterms

Prof. Wangrok Oh(CNU) Don’t-Care Conditions 27 / 67

Don’t-Care Conditions

It is also possible to obtain a simplified product-of-sums expression

Only way to combine the 0’s is to include don’t-care minterms 0 and
2
F 0 = z 0 + wy 0
Taking the complement of F 0

F = z(w0 + y) =
P
(1, 3, 5, 7, 11, 15)

Prof. Wangrok Oh(CNU) Don’t-Care Conditions 28 / 67

NAND and NOR Implementation
Digital circuits are frequently constructed with NAND or NOR gates
rather than with AND and OR gates
NAND and NOR gates are easier to fabricate with electronic
components and are the basic gates used in all IC families
AND, OR and NOT −→ NAND and NOR
NAND Circuits
NAND gate is said to be a universal gate because any logic circuit
can be implemented with it
Logical operations of AND, OR, and complement can be obtained
with NAND gates aloneSection 3.6 NAND and NOR Implementation 91

Inverter x x!

x
AND y xy

OR (x!y!)! " x # y

Prof. FIGURE 3.16

Wangrok Oh(CNU) NAND and NOR Implementation 29 / 67
 Inverter x x!

NAND and NOR Implementation

x
xy
AND y

OR (x!y!)! " x # y

The conversion
FIGURE 3.16 from AND, OR and complement to NAND can be
done
Logicby simple with
operations circuit manipulation
NAND gates techniques that change AND-OR
diagrams to NAND diagrams
x x
y (xyz)! y x! # y! # z! " (xyz)!
z z
(a) AND-invert (b) Invert-OR

FIGURE 3.17
When both symbols
Two graphic symbolsforare mixed inNAND
a three-input the same
gate diagram, the circuit is
said to be in mixed notation

of an AND graphic symbol followed by a small circle negation indicator referred to as

a bubble. Alternatively, it is possible to represent a NAND gate by an OR graphic
symbol that is preceded by a bubble in each input. The invert-OR symbol for the
NAND gate follows DeMorgan’s theorem and the convention that the negation indica-
tor (bubble) denotes complementation. The two graphic symbols’ representations are
useful in the analysis and design of NAND circuits. When both symbols are mixed in
the same diagram, the circuit is said to be in mixed notation.

Prof. Wangrok Oh(CNU) NAND and NOR Implementation 30 / 67

NAND and NOR Implementation
Two-Level Implementation
The implementation of Boolean functions with NAND gates requires
that the functions be in sum-of-products form

92 Chapter 3 Gate-Level Minimization

F = AB + CD

A
B
F
C
D

(a)

A A
B B
F F
C C
D D

(b) (c)

FIGURE 3.18
h i0
0
F = F(AB)
Three ways to implement (CD)0
= AB + CD = AB + CD

In Fig. 3.18(c), the output

Prof. Wangrok Oh(CNU) NANDNAND gate
and NOR is redrawn with the AND-invert graphic symbol.
Implementation 31 / 67
NAND and NOR Implementation
Section 3.6 NAND and NORP
Implementation 93
Example (Implement with NAND: F = (1, 2, 3, 4, 5, 7))
y
yz Section 3.6 NAND and NOR Implementation 93
x 00 01 11 10
m0 m1 m3 m2 y
yz x!y
0 0 x 1 00 1 01 111 10
m0 m1 m3 m2
m4 m5 m7 m6 x!y
0 0 1 1 1
x 1 1 1 1 F " xy! # x!y # z
m4 m5 m7 m6
x 1 1 1 1 F " xy! # x!y # z

xy! z z
xy! z z
(a)
F = xy 0 + 0
(a) x y + z

x x x
y! y! y!
x! x!
F x! F
y F y F
y
z z!

(b)
z! (c)

(b)FIGURE 3.19 (c)

Solution
Prof. Wangrok to Example 3.9
Oh(CNU) NAND and NOR Implementation 32 / 67
NAND and NOR Implementation
Multilevel NAND Circuits
94 Chapter 3 Gate-Level Minimization

C
F = A(CD + B) + BC 0
94 Chapter 3 Gate-Level Minimization
D
B
C
A
D
F
B
B
A
C!
F
B (a) AND–OR gates
C!
(a) AND–OR gates
C
D
B!
C
A
D
F
B
B!
C!
A
F
B (b) NAND gates
1 C!FIGURE
Convert all
3.20 AND gates to NAND gates with AND-invert symbols
2 Implementing
Convert all FOR
= A(CD + B)
gates BC!
to+ NAND gates
(b) NAND with invert-OR symbols
gates

FIGURE 3.20
Although
Oh(CNU)it is possible to remove the parentheses and reduce the expression into a standard
Prof. Wangrok Implementing F = A(CD +NAND
B) +and
BC!
NOR Implementation 33 / 67
NAND and NOR Implementation
3 Check all the bubbles in the diagram: For every bubble that is not
compensated by another bubble → Insert an inverter

(AB 0 3.6
F = Section 0
+ ANAND
B)(C + D0 )
and NOR Implementation 95

A
B!

A!
B F

C
D!
(a) AND–OR gates

A
B!

A!
B F

C!

D
(b) NAND gates

FIGURE 3.21
Implementing F = (AB! NAND
Prof. Wangrok Oh(CNU) + A!B)and
(CNOR
+ D!)
Implementation 34 / 67
NAND and NOR Implementation

NOR Implementation
NOR operation is the dual of the NAND operation
All procedures and rules for NOR logic are the duals of the
corresponding procedures and rules developed for NAND logic
The NOR gate is another universal gate that can be used to
96 Chapter 3 Gate-Level Minimization
implement any Boolean function

Inverter x x"

x
OR x!y
y

AND (x" ! y")" # xy

FIGURE 3.22
Logic operations with NOR gates

x
Prof. Wangrok Oh(CNU) x
NAND and NOR Implementation 35 / 67
 y

NAND and NOR Implementation

x

AND (x" ! y")" # xy

OR-invert symboly defines the NOR operation as an OR followed by a
complement
FIGURE 3.22
Invert-AND symbol complements each input and then performs an
Logic operations with NOR gates
AND operation
x x
y (x ! y ! z)" y x"y"z" # (x ! y ! z)"
z z
(a) OR-invert (b) Invert-AND

FIGURE 3.23 implementation with

A two-level NOR gates requires that the
Two graphic symbols for the NOR gate
function be simplified into product-of-sums form
Simplified product-of-sums expression is obtained from the map by
A two-level
combining implementation with NOR gates requires that the function be simplified
the 0’s and complementing
into product-of-sums form. Remember that the simplified product-of-sums expression
A product-of-sums expression: First level of OR gates followed by a
is obtained from the map by combining the 0’s and complementing. A product-of-sums
second-level
expression AND gate
is implemented with a first level of OR gates that produce the sum terms
The transformation from the OR-AND diagram to a NOR diagram is
followed by a second-level AND gate to produce the product. The transformation from
achieved by changing
the OR–AND diagram to a NOR diagram is achieved by changing the OR gates to
1 OR
NOR gates withgates to NOR
OR-invert gates with
graphic OR-invert
symbols and thegraphic symbols
AND gate to a NOR gate with an
2 AND
invert-AND gatesymbol.
graphic to a NOR gate with
A single literalanterm
invert-AND graphic
going into symbol
the second-level gate must
be complemented. Figure 3.24 shows the NOR implementation of a function expressed
as a product of sums:
Prof. Wangrok Oh(CNU) NAND and NOR Implementation 36 / 67
NAND and NOR Implementation

Example (F = (A +Section
B)(C3.7 Other Two-Level Implementations
+ D)E) 97

A
B

C
F
D

E!

FIGURE 3.24 The OR-AND pattern can easily be detected by the removal of the
Implementing Fbubbles
= (A + along
B)(C +
theD)E
same line
Variable E is complemented to compensate for the third bubble at
A! the input of the second-level gate
B

F
A
B!

C
Prof. Wangrok Oh(CNU) NAND and NOR Implementation 37 / 67
 Section 3.7 Other Two-Level Implementations 97
NAND and NOR Implementation
A
B
Multilevel AND-OR diagram to an all-NOR diagram
1 Convert Ceach OR gate to an OR-invert and each AND gate to an
F
invert-AND
D
2 Any bubble that is not compensated by another bubble along the
same lineE! needs an inverter
FIGURE 3.24
Example (F = (AB + A B)(C + D0 ))
0 0
Implementing F = (A + B)(C + D)E

A!
B

F
A
B!

C
D!

FIGURE 3.25
The Fequivalent
Implementing AND-OR
= (AB! + A!B)(C diagram
+ D!) with can be
NOR gates recognized from the NOR
diagram by removing all the bubbles
ToAND–OR
The equivalent compensate for can
diagram thebebubbles in four
recognized from inputs,
the NORitdiagram
is necessary to
by remov-
complement
ing all the bubbles. the corresponding
To compensate input
for the bubbles in literals
four inputs, it is necessary to
complement the corresponding input literals.

Prof. Wangrok Oh(CNU) NAND and NOR Implementation 38 / 67

Other Two-Level Implementations
The gates most often found in integrated circuits: NAND and NOR
→ NAND and NOR logic implementations are the most important
Some NAND or NOR gates allow the possibility of a wire connection
between the outputs of two gates to provide a specific logic function
→ Wired logic
Open-collector TTL NAND gates, when tied together, perform
wired-AND logic 98 Chapter 3 Gate-Level Minimization

A A
B B
F ! (AB " CD)#
C C
D D
(a) Wired-AND in open-collector (b) Wired-OR in ECL gates
AND gate is drawn withTTL NAND
the gates.
lines going through the center of the
gate (AND–OR–INVERT) (OR–AND–INVERT)

The wired-AND gate is notFIGURE 3.26 gate: Only a symbol to

a physical
Wired logic
designate the function obtained from the indicated wired connection
(a) Wired-AND logic with two NAND gates
(b) Wired-OR in emitter-coupled logic (ECL) gates
F = (AB)0 · (CD)0 = (AB + CD)0 = (A0 + B 0 )(C 0 + D0 )

AND-OR-INVERT functionSimilarly, the NOR outputs of ECL gates can be tied together to
Prof. Wangrok Oh(CNU) function.
Other Two-Level The logic
Implementations function implemented by the circuit of 39
Fig. 3.2
/ 67
 Other Two-Level Implementations

NOR outputs of ECL gates can be tied together to perform a

3 Gate-Level Minimization
wired-OR function
A
B
F ! (AB " CD)# F ! [(A " B) (C " D)]#
C
D
open-collector (b) Wired-OR in ECL gates
D gates.
0
F = (A + B)0 + (C + D)0 = (A + B)(C + D)

NVERT) (OR–AND–INVERT)

RE 3.26
d logic OR-AND-INVERTER function
Wired-AND logic with two NAND gates
Wired-OR in emitter-coupled logic (ECL) gates

arly, the NOR outputs of ECL gates can be tied together to perform a wired-OR
n. The logic function implemented by the circuit of Fig. 3.26(b) is
Prof. Wangrok Oh(CNU) Other Two-Level Implementations 40 / 67
Other Two-Level Implementations

Nondegenerate Forms
How many two-level combinations of gates are possible?
4 types of gates: AND, OR, NAND and NOR → 16 possible
combinations
The same type of gate can be in the first and second levels
1 8 of these combinations are said to be degenerate forms
2 They degenerate to a single operation
3 AND-AND configuration = AND of all input variables
The remaining eight nondegenerate forms produce an
implementation in sum-of-products form or product-of-sums form
1 AND-OR/OR-AND
2 NAND-NAND/NOR-NOR
3 NOR-OR/NAND-AND
4 OR-NAND/AND-NOR

Prof. Wangrok Oh(CNU) Other Two-Level Implementations 41 / 67

 By using the alternative graphic symbol for the NOR gate, we obtain the diagram of
Fig. 3.27(b). Note that the single variable E is not complemented, because the only
Other Two-Level Implementations
change made is in the graphic symbol of the NOR gate. Now we move the bubble from
the input terminal of the second-level gate to the output terminals of the first-level gates.
An inverter is needed for the single variable in order to compensate for the bubble.
Alternatively, the inverter can be removed, provided that input E is complemented. The
circuit of Fig.
AND-OR-INVERT 3.27(c) is a NAND–AND form and was shown in Fig. 3.26 to implement
Implementation
the AND–OR–INVERT function.
NAND-AND and AND-NOR
An AND–OR implementationarerequires
equivalent
an expression in sum-of-products form. The
AND-NORAND–OR–INVERT
resembles the implementation
AND-ORis similar,
but withexcept
anforinversion
the inversion.done
Therefore,
by ifthe
the
complement of the function is simplified into sum-of-products form (by combining the 0’s
bubble in
inthe
the output of the NOR
map), it will be possible to implement F! with the AND–OR part of the function.
When F! passes through the always present output inversion (the INVERT part), it will
F = (AB + CD + E)0

A A A
B B B

C C C
F F F
D D D

E E E

(a) AND–NOR (b) AND–NOR (c) NAND–AND

FIGURE 3.27
AND-OR AND–OR–INVERT
implementation requires
circuits, F = (AB +an
CD expression
in sum-of-products
+ E )!
form
AND-OR-INVERT implementation is similar except for the inversion

Prof. Wangrok Oh(CNU) Other Two-Level Implementations 42 / 67

 INVERT function.
The OR–AND–INVERT implementation requires an expression in product-of-sums
Other Two-Level Implementations
form. If the complement of the function is simplified into that form, we can implement
F! with the OR–AND part of the function. When F! passes through the INVERT part,
we obtain the complement of F!, or F, in the output.
If the complement of the function is simplified into sum-of-products
(by combining
Tabular Summary theand in the map) → Implement F 0 with the
0’sExample
AND-OR part of the function
Table 3.2 summarizes the procedures for implementing a Boolean function in any one
0
When F passes
of the through
four 2-level the always
forms. Because presentpart
of the INVERT output
in each inversion (the to
case, it is convenient
INVERT use part),
the simplification of F! (the complement)
it will generate the output of the
F function. When F! is implemented
in one of these forms, we obtain the complement of the function in the AND–OR or
OR–AND form.
OR-AND-INVERT The four 2-level forms invert this function, giving an output that is the
Implementation
complement of F!. This is the normal output F.
OR-NAND and NOR-OR perform the OR-AND-INVERT function
A A A
B B B

C C C
F F F
D D D

E E E

(a) OR–NAND (b) OR–NAND (c) NOR–OR

FIGURE 3.28  0
OR–AND–INVERT F = (A
circuits, F = +
3 ( AB)(C +DD)E
+ B )(C + )E 4!

OR-AND-INVERT requires an expression in product-of-sums form

If the complement of the function is simplified into that form, we can
implement F 0 with the OR-AND part of the function
Prof. Wangrok Oh(CNU) Other Two-Level Implementations 43 / 67
Other Two-Level Implementations

When F 0 passes through the INVERT part, we obtain the

complement of F 0 , or F in the output
Section 3.7 Other Two-Level Implementations 101
Summary
Table 3.2
Implementation with Other Two-Level Forms
Equivalent
Nondegenerate Form Implements Simplify To Get
the F’ an Output
(a) (b)* Function into of

AND–NOR NAND–AND AND–OR–INVERT Sum-of-products

form by combining
0’s in the map. F
OR–NAND NOR–OR OR–AND–INVERT Product-of-sums
form by combining
1’s in the map and
then complementing. F

*Form (b) requires an inverter for a single literal term.

EXAMPLE
Prof. Wangrok Oh(CNU) 3.10 Other Two-Level Implementations 44 / 67
 Other Two-Level Implementations
hapterExample
3 Gate-Level Minimization
(Implement a function with the four 2-level forms)
y
yz
x 00 01 11 10
m0 m1 m3 m2
F = x!y!z! + xyz!
0 1 0 0 0
F! = x!y + xy! + z
x!y!z!
m4 m5 m7 m6
xyz!
x 1 0 0 0 1

z
(a) Map simplification in sum of products
The complement of the function is simplified into sum-of-products
x!
by combining the 0’s x!
y F 0 = x0 y +y xy 0 + z

x
Normal output: F = (x0 y + xy 0 + z)
x
0
← AND-OR-INVERT
F F
y! y!
Prof. Wangrok Oh(CNU) Other Two-Level Implementations 45 / 67
 00 01 11 10
m0 m1 m3 m2
F = x!y!z! + xyz!
Other Two-Level
x!y!z!
Implementations
0 1 0 0 0
F! = x!y + xy! + z
m4 m5 m7 m6
xyz!
x 1 0 0 0 1

Example (Continued) z
(a) Map simplification in sum of products
AND-NOR and NAND-AND implementations
x! x!
y y

x x
F F
y! y!

z z
AND–NOR NAND–AND
(b) F " (x!y # xy! # z)!
OR-AND-INVERT require a simplified expression of the complement
of the function in product-of-sums form
x x
y y
z z
F F
Prof. Wangrokx!Oh(CNU) x!
Other Two-Level Implementations 46 / 67
 x! x!
Other Two-Level
y
Implementations
y

Example
x (Continued) x
F F
y! y!
1 Combine the 1’s in the map: F = x y z + xyz 0 0 0 0

2 Take the complement of the function: F 0 = (x + y + z)(x0 + y 0 + z)

z z
3 The normal output F can be expressed in the OR-AND-INVERT
AND–NOR NAND–AND
(b)
 F " (x!y # xy! #0z)!
0 0
F = (x + y + z)(x + y + z)

x x
y y
z z
F F
x! x!
y! y!
z z
OR–NAND NOR–OR
(c) F " [(x # y # z) (x! # y! # z)]!

FIGURE 3.29
Other two-level implementations
Prof. Wangrok Oh(CNU) Other Two-Level Implementations 47 / 67
Exclusive-OR Function

Exclusive-OR (XOR)
1 Denoted by the symbol ‘⊕’
2 Performs the Boolean operation: x ⊕ y = xy 0 + x0 y
Exclusive-OR is equal to 1 if x and y differ in value
Exclusive-NOR: Equivalence

(x ⊕ y)0 = xy + x0 y 0

Exclusive-NOR is the complement of the exclusive-OR

(x ⊕ y)0 = (xy 0 + x0 y)0 = (x0 + y)(x + y 0 ) = xy + x0 y 0

Identities for the exclusive-OR

1 x⊕0=x
2 x ⊕ 1 = x0
3 x⊕x=0
4 x ⊕ x0 = 1
5 x ⊕ y 0 = x0 ⊕ y = (x ⊕ y)0

Prof. Wangrok Oh(CNU) Exclusive-OR Function 48 / 67

Exclusive-OR Function

Exclusive-OR operation is both commutative and associative

A⊕B = B⊕A
(A ⊕ B) ⊕ C = A ⊕ (B ⊕ C) = A ⊕ B ⊕ C
104 Chapter 3 Gate-Level
Implementation Minimization
of two-input exclusive-OR with AND-OR-NOT gates
x

x!y

(a) Exclusive-OR with AND–OR–NOT gates

Prof. Wangrok Oh(CNU) Exclusive-OR Function 49 / 67

 x!y

Exclusive-OR Function
y

(a) Exclusive-OR with AND–OR–NOT gates

Implementation of two-input exclusive-OR with NAND gates
x

x!y

(b) Exclusive-OR with NAND gates

0 0 0
The 3.30
1FIGURE first NAND performs (xy) = (x + y )
2Exclusive-OR
The other implementations
two-level NAND produces the sum of products of its inputs

(x0 + y 0 )x + (x0 + y 0 )y = xy 0 + x0 y = x ⊕ y
Only a limited number of Boolean functions can be expressed in terms of exclusive-OR
operations.
XOR Nevertheless,
emerges this function
quite often duringemerges quite often
the design of during
digitalthesystems
design of digital
systems. It is particularly useful in arithmetic operations and error detection and correc-
tion Useful in arithmetic operations
1 circuits.
2 Error detection and correction circuits
Odd Function
The exclusive-OR operation with three or more variables can be converted into an
ordinary Boolean function by replacing the { symbol with its equivalent Boolean
Prof. expression.
Wangrok Oh(CNU)In particular, the three-variable case can be converted to a Boolean expres-
Exclusive-OR Function 50 / 67
Exclusive-OR Function

Odd Function
Exclusive-OR with three or more variables can be converted into an
ordinary Boolean function by replacing ⊕ with its equivalent Boolean
expression

A⊕B⊕C = (AB 0 + A0 B)C 0 + (AB + A0 B 0 )C

= AB 0 C 0 + A0 BC 0 + ABC + A0 B 0 C
P
= (1, 2, 4, 7)

Three-variable exclusive-OR function is equal to 1 if

1 Only one variable is equal to 1
2 All three variables are equal to 1
For three or more variables, the output is 1 when there are odd
number of inputs whose value is 1
Multiple-variable exclusive-OR operation is defined as an odd
function

Prof. Wangrok Oh(CNU) Exclusive-OR Function 51 / 67

 we can obtain the sum of minterms for this function:
A { B { C { D = (AB! + A!B) { (CD! + C!D)
A { B { C { D = =(AB!
Exclusive-OR Function (AB!++ A!B)
A!B)(CD{ (CD! + C!D)
+ C!D!) + (AB + A!B!)(CD! + C!D)
= =(AB! + 4,A!B)(CD
"(1, 2, 7, 8, 11, 13,+ 14)
C!D!) + (AB + A!B!)(CD! + C!D)
= "(1, 2, 4, 7, 8, 11, 13, 14)
B B
BC BC
A 00 01 11 B 10 A
00 01 11 B10
BC m0 m1 m3 m2 BCm0 m1 m3 m2
A A
0 00 01 1 11 101 0 100 01 1 11 10
m0 m1 m3 m2 m0 m1 m3 m2
m4 m5 m7 m6 m4 m5 m7 m6
0 1 1 0 1 1
A 1 1 1 A 1 1 1
m4 m5 m7 m6 m4 m5 m7 m6
A 1 1 C1 A 1 1C 1
(a) Odd function F ! A ! B ! C (b) Even function F ! (A ! B ! C)"

FIGURE 3.31 C C
(a)aOdd
Map for A ! B ! C function (b) Even function F ! (A ! B ! C)"
function F !exclusive-OR
three-variable
FIGURE 3.31
A A
Map for a three-variable exclusive-OR function
B B
A A
C C
B (a) 3-input odd function B (b) 3-input even function

FIGURE 3.32
C C
Logic diagram of odd and even functions
(a) 3-input odd function (b) 3-input even function

FIGURE 3.32
Logic diagram of odd and even functions
Prof. Wangrok Oh(CNU) Exclusive-OR Function 52 / 67
Exclusive-OR Function
4-variable exclusive-OR

A⊕B⊕C ⊕D = (AB 0 + A0 B) ⊕ (CD0 + C 0 D)

= (AB 0 + A0 B)(CD + C 0 D0 )
+(AB + A0 B 0 )(CD0 + C 0 D)
P
106
=
Chapter 3 Gate-Level Minimization
(1, 2, 4, 7, 8, 11, 13, 14)

C C
CD CD
AB 00 01 11 10 AB 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 00 1 1

m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 01 1 1
B m12 m13 m15 m14 B
m12 m13 m15 m14
11 1 1 11 1 1
A A m8 m9 m11 m10
m8 m9 m11 m10
10 1 1 10 1 1

D D
(a) Odd function F ! A ! B ! C ! D (b) Even function F ! (A ! B ! C ! D)"

FIGURE 3.33
Map for a four-variable exclusive-OR function
Prof. Wangrok Oh(CNU) Exclusive-OR Function 53 / 67
Exclusive-OR Function

Parity Generation and Checking

Exclusive-OR is very useful in systems requiring error detection and
correction codes
Parity bit is used for the purpose of detecting errors during the
transmission of binary information
A parity bit is an extra bit included with a binary message to make
the number of 1’s either odd or even
The circuit generates the parity bit in the transmitter is called a
parity generator
The circuit checks the parity in the receiver is called a parity checker

Prof. Wangrok Oh(CNU) Exclusive-OR Function 54 / 67

 Three-Bit Message P
Exclusive-OR Function x y z

0 0 0
Section 3.8 Exclusive-OR Function 107 0 0 1
Example (3-bit Message with an Even-Parity Bit) 0 1 0
Table 3.3 0 1 1
Even-Parity-Generator Truth Table 1 0 0
1 0 1
Three-Bit Message Parity Bit
1 1 0
x y z P 1 1 1

0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0 x
1 0 0 1 x y
1 0 1 0 y P
1 1 0 0 z
1 1 1 1
z P
(a) 3-bit even parity generator (b) 4
For even parity, bit P must be generated to make the total number
FIGURE 3.34
of 1’s even x Logic diagram of a parity generator and checker
P should constitute
y an odd function: P = x ⊕ y ⊕ z
The output
P of the parity checker, denoted by C C will be equal to 1 if
z
an error occurs (odd parity)
P
odd function because it is equal to 1 for those minter
an odd number of 1’s. Therefore, P can be expressed a
(a) 3-bit even parity generator (b) 4-bit even parity checker
function:
Prof. Wangrok Oh(CNU) Exclusive-OR Function 55 / 67
 Section 3.8 Exclusive-OR Function 107
Exclusive-OR Function
Table 3.3
Even-Parity-Generator Truth Table

Example (Continued)
Chapter 3 Gate-Level Minimization Three-Bit Message Parity Bit

Table 3.4 x y z P
Even-Parity-Checker Truth Table
0 0 0 0
Four Bits Parity Error
Received 0 Check 0 1 1
0 1 0 1
x y z P C
0 1 1 0
0 0 0 0 1 0 0 0 1
0 0 0 1 1 1 0 1 0
0 0 1 0 1
1 1 0 0
0 0 1 1 0
0 1 0 0 1 1 1 1 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
x
1 x0 1 1 1 y
1 1 0 0 0
1 y1 0 1 1 P C
1 1 1 0 1 z
1 1 1 1 0
z P
(a) 3-bit even parity generator (b) 4-bit even parity checker
represents an odd function. The parity checker can be implemented with exclusive-
OR gates: FIGURE 3.34
C =x⊕y⊕z⊕P
= x{y{
Logic Cdiagram ofza{parity
P generator and checker
The logic diagram of the parity checker is shown in Fig. 3.34(b).
Generator can be implemented with the checker ← z ⊕ 0 = z
It is worth noting that the parity generator can be implemented with the circuit of
Same circuit can be used for both parity generation and checking
Fig. 3.34(b) if the input P is connected to logic 0 and the output is marked with P. This is
because z { 0 = z, causing the value of z to pass through the gate unchanged. The advan-
oddthe
tage of this strategy is that function because
same circuit can beitused
is equal toparity
for both 1 forgeneration
those minterms
and whose numerical values have
checking. an odd number of 1’s. Therefore, P can be expressed as a three-variable exclusive-OR
It is obvious from theOh(CNU)
foregoing example that parity generation and checking circuits
function:
Prof. Wangrok Exclusive-OR Function 56 / 67
Hardware Description Language

Manual design of logic circuits is feasible when the circuit is small

Usually, designers use computer-based design tools
Hardware Description Language (HDL)
1 Computer-based language that describes the hardware of digital
systems in a textual form
2 It resembles an ordinary computer programming language, such as C
3 It is specially oriented to describing hardware structures and the
behavior of logic circuits
HDLs are used in several major steps in the design flow of an
integrated circuit
1 Design entry
2 Functional simulation or verification
3 Logic synthesis
4 Timing verification and fault simulation
Two standard HDLs supported by the IEEE
1 VHDL
2 Verilog

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Hardware Description Language

Module Declaration
The term module refers to the text enclosed by the keyword pair
module and endmodule
Module is the fundamental descriptive unit in the Verilog language
Combinational logic can be described by
A schematic connection of gates
A set of Boolean equations
A truth table
Each type of description can be developed in Verilog

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 signal), and other elements of the language so that they can be referenced in the design.
In general, we choose meaningful names for modules. Identifiers are composed of alpha-
Hardware Description Language
numeric characters and the underscore (_), and are case sensitive. Identifiers must start
with an alphabetic character or an underscore, but they cannot start with a number.
Example (Module Declaration)

A w1
G1 G3 D
B

C G2 E

112 Chapter 3 Gate-Level Minimization

FIGURE 3.35
HDL Example
Circuit to demonstrate an 3.1
HDL (Combinational Logic Modeled with Primitives)

// Verilog model of circuit of Figure 3.35. IEEE 1364–1995 Syntax

module Simple_Circuit (A, B, C, D, E);
output D, E;
input A, B, C;
wire w1;
and G1 (w1, A, B); // Optional gate instance name
not G2 (E, C);
or G3 (D, w1, E);
endmodule

TheOh(CNU)
Prof. Wangrok port list of a module is the interface
Hardware between
Description Language the module and its environment. 59 / 67
Hardware Description Language

Gate Delays
All physical circuits exhibit a propagation delay between the
transition of an input and a resulting transition of an output
When an HDL model of a circuit is simulated, it is some- times
necessary to specify the amount of delay from the input to the
output of its gates
In Verilog, the propagation delay of a gate is specified in terms of
time units and by the symbol #
The numbers associated with time delays in Verilog are dimensionless
The association of a time unit with physical time is made with the
timescale compiler directive
Compiler directives start with the ‘
Directive is specified before the declaration of a module and applies
to all numerical values of time in the code that follows
Example: ‘timescale 1ns/100ps
The first number specifies the unit of measurement for time delays
The second number specifies the precision for which the delays are
rounded off

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Hardware Description Language

1 // Verilog Model of Simple Circuit with Propagation

Delay
2
3 module S i m p l e _ C i r c u t i _ p r o p _ d e l a y (A ,B ,C ,D , E ) ;
4 output D , E ;
5 input A , B , C ;
6 wire w1 ;
7
8 and #(30) G1 ( w1 ,A , B ) ;
9 not #(10) G2 (E , C ) ;
10 or #(20) G3 (D , w1 , E ) ;
11 endmodule

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Hardware Description Language

Section 3.9 Hardware Description Language 115

0.0 ns 58.0 ns 116.0 ns 174.0 ns

Name

A
B
C

D
E

FIGURE 3.36
Simulation
In order output of HDL
to simulate Examplewith
a circuit 3.3 an HDL, it is necessary to apply
inputs to the circuit
An probes
HDL(wires)
description thatofprovides
to the outputs the circuit. the
(The stimulus to a design
interaction between is genera-
the signal called a
testtors of the stimulus module and the instantiated circuit module is illustrated in Fig. 4.36.)
bench
Hardware signal generators are not used to verify an HDL model: The entire simula-
tion exercise is done with software models executing on a digital computer under the
direction of an HDL simulator. The waveforms of the input signals are abstractly modeled
(generated) by Verilog statements specifying waveform values and transitions. The initial
keyword is used with a set of statements that begin executing when the simulation is ini-
tialized; the signal activity associated with initial terminates execution when the last state-
ment has finished executing. The initial statements are commonly used to describe
Prof. waveforms in a test bench.
Wangrok Oh(CNU) The set
Hardware of statements
Description to be executed is called a block statement
Language 62 / 67
Hardware Description Language

1 // Test bench for S i m p l e _ C i r c u i t _ p r o p _ d e l a y

2 module t _ S i m p l e _ C i r c u i t _ p r o p _ d e l a y ;
3 wire D , E ;
4 reg A , B , C ;
5 S i m p l e _ C i r c u i t _ p r o p _ d e l a y M1 (A , B , C , D , E ) ;
6 // Instance Name Required
7 initial begin
8 A = 1 ’ b0 ;
9 B = 1 ’ b0 ;
10 C = 1 ’ b0 ;
11 #100 A = 1 ’ b1 ; B = 1 ’ b1 ; C = 1 ’ b1 ;
12 end
13 initial #200 $finish ;
14 endmodule

Using a test bench is similar to testing actual hardware by attaching

signal generators to the inputs of a circuit and attaching probes to
the outputs
The initial keyword is used with a set of statements that begin
executing when the simulation is initialized

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Hardware Description Language
Boolean Expressions
Boolean equations describing combinational logic are specified in
Verilog with a continuous assignment statement consisting of the
keyword assign followed by a Boolean expression
Logical operators in Verilog
&: AND
/ : OR
∼: NOT
Example:
1 assign D = ( A && B ) || (! C ) ;

1 // Verilog model : Circuit with Boolean expressions

2 module C i r c u i t _ B o o l e a n _ C A (E , F , A , B , C , D ) ;
3 output E , F ;
4 input A ,B ,C , D ;
5 assign E = A ||( B && C ) ||((! B ) && D ) ;
6 assign F =((! B ) && C ) || ( B && (! C ) && (! D ) ) ;
7 endmodule

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Hardware Description Language

User-Defined Primitives
System primitives: Verilog descriptions defined by the system
User can create additional primitives by defining them in tabular
form → User-defined primitives (UDPs)
UDP descriptions do not use the keyword pair module and
endmodule
Keyword pair primitive and endprimitive are used for UDPs
Define an UDP with a truth table
1 Declared with the keyword primitive followed by a name and port list
2 There can be only one output and it must be listed first in the port
list and declared with keyword output
3 There can be any number of inputs
4 The order in which they are listed in the input declaration must
conform to the order in which they are given values in the table that
follows
5 The truth table is enclosed within the keywords table and endtable
6 The values of the inputs are listed in order ending with a colon (:)
7 Output is always the last entry in a row and is followed by a
semicolon (;)
8 The declaration of a UDP ends with the keyword endprimitive

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Hardware Description Language

1 // Verilog model : User - defined Primitive

2 primitive UDP_02467 (D ,A ,B , C ) ;
3 output D ;
4 input A ,B , C ;
5 // Truth table for D = f (A ,B , C ) = Sum (0 ,2 ,4 ,6 ,7) ;
6 table
7 // A B C : D
8 0 0 0 : 1;
9 0 0 1 : 0;
10 0 1 0 : 1;
11 0 1 1 : 0;
12 1 0 0 : 1;
13 1 0 1 : 0;
14 1 1 0 : 1;
15 1 1 1 : 1;
16 endtable
17 endprimitive

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 Hardware Description Language
118 Chapter 3 Gate-Level Minimization

A
B UDP_02467 E
C

F
D

FIGURE 3.37
Schematic for Circuit model
1 // Verilog with_UDP_02467
: Circuit instantiation of
Circuit_UDP_02467
2 module C i r c u i t _ w i t h _ U D P _ 0 2 4 6 7 (e ,f ,a ,b ,c , d ) ;
Note that the variables listed on top of the table are part of a comment and are show
3 output e , f ;
only for
4
clarity.
input The system
a ,b ,crecognizes
,d; the variables by the order in which they are listed
in the input
5
declaration. A user-defined primitive can be instantiated in the construction
of other
6 modules (digitalM0circuits),
UDP_02467 (e ,a ,bjust
, c )as
; the system primitives are used. For example
the declaration
7 and (f ,e , d ) ; // Option gate instance name omitted
8 endmodule
Circuit _with _UDP_ 02467 (E, F, A, B, C, D);
will produce a circuit that implements the hardware shown in Figure 3.37.
Although Verilog HDL uses this kind of description for UDPs only, other HDLs and
computer-aided design (CAD) systems use other procedures to specify digital circuit
in Wangrok
Prof. tabular form. The tables can
Oh(CNU) be processed
Hardware by CAD software to derive an efficient
Description Language 67 / gat
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