ANALOG & DIGITAL ELECTRONICS

18CS33
QUESTION BANK
MODULE 1
1 What are Opto-electronic devices? Explain the construction, working principle and V-I-
characteristics of Photodiode with neat diagram.
2 Explain the construction, working principle of LED with neat diagram
3 What are the applications of LED‟s
4 What is Opto-coupler? Explain the construction, working principle and application of
optocoupler with neat diagram
5 Explain base bias or fixed biasing circuit with neat diagram
6 Explain collectror bias circuit with neat diagram
7 Explain voltage divider bias circuit with neat diagram. OR With neat circuit diagram
and mathematical analysis explain voltage divider bias circuit
8

9 Differentiate between Ideal Opamp and practical opamp

10 Explain the internal structure of 555 Timer IC with neat diagram
11 Explain the working of Mono-stable Multi-vibrator using 555 Timer IC
12 Show how 555 Timer can be used as an astable multi-vibrator
13 Explain the working of Peak detector circuit
14 Explain with circuit diagram the working of Inverting Schmitt trigger
15 Explain the working of First order Low pass filter
16 Explain the working of relaxation oscillator with neat circuit diagram and waveform
17 Explain the Performance Parameters of a Power Supply.
18 Find the binary equivalent weight of each bit in 4-bit system
19 Explain Binary weighted resistive divider D to A converter
20 List the drawback of Resistive Divider D to A converter
21 For a 5-bit resistive divider network determine the following:
a) The weight assigned to the LSB
b) The weight assigned to the second and third LSB
c) The change in output voltage due to change in LSB, second LSB and the third
LSB
d) The output voltage for the digital input 10101. Assume 0 = 0V and 1 = +10V
22 Draw the schematic of 4 bit binary ladder (R-2R binary ladder) and explain how digital
to analog conversion is achieved using that circuit
23 Explain the Binary Ladder with digital input 0100
24 Explain the Binary Ladder with digital input 1100
25

26

27 Define the terms Accuracy and Resolution with respect to D to A converter

28 Explain the working of successive approximation type of A to D converter
MODULE 2
1 Define Minimum Sum of Product logic expression.
2 Find a minimum sum-of-products expression for F (a, b, c) = ∑ m (0, 1, 2, 5, 6, 7)
3 Convert the Sum of Product expression Y = F (A, B, C) = ∑ m (1, 4, 5, 7) into Product
of Sum expression
4 What is Karnaugh-Map? Plot the following functions on the given Karnaugh maps:
F (R, S, T) = ∑ m (0, 1, 5, 6) or F(R, S, T) = m0 + m1 + m5 + m6
5 Find the minimum SOP form for the function shown below:
Y = F(a, b, c) = ∑ m(1, 3, 5)
6 Find the minimum SOP form for the function shown below:
Y = F(a, b, c) = ∑ m(0, 2, 4,6,7)
7 Y = F(a, b, c) = ∑ m(0, 1, 2, 5, 6, 7). Find minimum SOP form.
8 Find the minimum SOP form for the function Y = F(a, b, c, d) = ∑ m(1, 3, 4, 5,
10,12,13)
9 A digital system is to be designed in which months of the year is given as input in four
bit form. The month January is represented as „0000‟, February as „0001‟ and so on. The
output of the system should be „1‟ corresponding to the input of the month containing31
days or otherwise it is „0‟. Consider excess numbers in the input beyond „1011‟ as don‟t
care conditions. For this system of four variables (A, B, C, D) find the following:
i. Write the truth table
ii. Boolean expression in ∑m and ΠM form
iii. Using K-Map simplify in SOP form(simplify Boolean expression of
canonical min-term form)

10 Find the minimum SOP and minimum POS expressions for the following function using
K-map. F(A, B, C, D) = ∑m(1, 3, 4, 11) + ∑d(2, 7, 8,12, 14, 15)
11 Find the minimum sum of products expression for F = ∑m(2, 4, 8) + ∑d(0, 3, 7)
12 What is implicant of a function? What is prime implicant?
13 What is essential prime implicant?
14 With the help of flow chart explain how to determine minimum sum of products using
Karnaugh Map
15 What are the advantages and disadvantages of K-Map method of simplification of logic
expression.
16 What are the disadvatages of K-Map method? How they are overcome in Quine-
McCluskey method
17 Simplify the Boolean function f(a, b, c, d) = Σm (0, 1, 2, 5, 6, 7, 8, 9, 10, 14) using
Quine-McClusky method.
18 Simplify the Boolean function given below:
Y = F(a, b, c, d) = ∑ m(0, 2, 3, 5, 6,7,8,10,11,14,15) using QUINE-McCLUSKY
Method
19 With example explain Petrick‟s method
20 Simplify the Boolean expression for the function: F(a, b, c, d)=∑ m(2, 3, 7, 9, 11, 13) +
d(1, 10, 15) using Quine-McClusky method
21 Simplify the Boolean function F(A,B, C, D) = ∑m(0, 1, 2, 3, 10, 11. 12, 13. 14. 15)
using Quine-McClusky Method
22 Simplify Y (A, B, C) = Σm (1, 2, 3, 4, 8, 9, 10, 13, 14) by using entered variable map
method by taking a) “D” as map entered variable b) “C and D” as map entered variables
23 What is Map Entered Variable method? Using MEV method simplify the following
function:
MODULE 3
1 What is Combinational Circuit?
2 Realize f (a, b, c, d) = ∑ m(0, 3, 4, 5, 8, 9, 10, 14, 15) using three-input NOR gates.
3 What are propagation or gate delays?
4 What are Hazards in Digital circuits? Explain different types of hazards
5 How to design a hazard free circuit? Explain with an example
6 Explain simulation and testing of logic circuits
7 What is multiplexer? Realize the function F (A, B, C, D) = ∑ m(0, 2, 3, 4, 5, 8, 9, 10, 11,
12, 13, 15) using 8 to 1 MUX
8 Realize the function F (A, B, C, D) = ∑m(1, 2, 5, 6, 9, 12) using 8:1 MUX
9 Design a 32 to 1 Multiplexer using two 16 to 1 multiplexers and one 2 to 1 Multiplexer.
10 What is decoder? Explain 3 to 8 line decoder.
11 Realize the following function using 3:8 decoder
F1 (a, b, c) = ∑m(1, 3, 4)
F2 (a, b, c) = ∑m(3, 5, 7)
12 Realize the following function using 3:8 decoder and NAND gate
F1 (a, b, c, d) = ∑m(1, 2, 4)
F2 (a, b, c, d) = ∑m(4, 7, 9)
13

14 Implement full subtractor using 3 to 8 decoder and NAND gates

15 Implement the Full adder outputs using 3- to-8 decoder and NAND gates
16 What is an encoder? Explain 8 to 3 line encoder.
17 Design a priority encoder for a system with three inputs whose truth table is as shown
below; the order of priority for three inputs is X1 > X2 > X3. However if the encoder is
not enabled by S or all the inputs are inactive the output AB = 00.
18 Design hexadecimal (Binary) to ASCII code converter using suitable ROM. Give the
Connection diagram of ROM.
19 What are programmable logic devices (PLDs)
20 Differentiate between ROM and PLA
21 Realize the following functions using suitable PLA
22 Design 7 segment decoder using PLA
23 Implement a Full adder using PAL
24 Differentiate between PLA and PAL
MODULE 4
1 With example explain the signal assignment statement in VHDL.
2 With example explain the conditional signal assignment statement in VHDL
3 Explain the structure of VHDL program. Write VHDL code for 4-bit parallel adder
using full adder as component
4 Differentiate Combinational and Sequential circuits
5 Explain the working of SR Latch using NOR gates.
6 Explain the operation of SR latch when both the inputs S = R = 1
7 Derive the Characteristic or Next state equation for SR Latch circuit
8 Show how S-R latch is used for De-bouncing switches OR What is switch contact
bounce? How to remove any contact bounce due to switch using SR Latch
9 Explain the working S-R Flip-Flop with logic diagram, truth table and timing diagram.
10 Draw the logic diagram of master slave J-K Flip-Flop using NAND gates and explain
the working with suitable timing diagram.
11 Show how S-R Flip-Flop can be converted to D Flip-Flop
12 Show how D Flip-Flop can be converted to S-R Flip-Flop
13 Show how J-K Flip-Flop can be converted to T Flip-Flop
14 Show how D Flip-Flop can be converted to T Flip-Flop
15 Differentiate between Latch and Flip-Flop
16 Derive the characteristic equations for SR, JK, D and T flip-Flops
MODULE 5
1 What is register? Explain how 4-bit register with data, load, clear and clock input is
constructed using D flip-flops
2 With a block diagram explain the working of n-bit parallel adder with accumulator
3 What is shift register? Explain the working of 4-bit shift register using D-Flip Flop
4 Explain the working of 8-bit SISO shift register using SR-Flip Flop
5 Explain the working of 4-bit parallel-in, parallel-out shift register
6 Explain the working of 4-bit PISO shift register
7 Explain the working of shift register with inverted feedback or Johnson counter or
twisted ring counter
8 What is counter? What is synchronous counter?
9 Write the excitation table for D, T, SR and JK Flip-flop
10 Design a mod-8 synchronous up counter using T flip-flops
11 Design a mod-8 synchronous up counter using D flip-flops
12 Design a mod-8 synchronous up counter using SR flip-flops
13 Design a mod-8 synchronous up counter using JK flip-flops
14 Design a random counter using T, D, SR and JK flip-flops whose transition graph is
shown below:

15 With the help of state graph, state and transition tables and timing diagram explain
sequential parity checker
16 Analyse the following Moore Sequential circuit for an input sequence of X = 01101 and
draw the timing diagram

17 Explain Mealy sequential circuit

18 What is the difference between Moore machine and Mealy machine