CHAPTER 3

• Memory unit design with special emphasis on

implementation of CPU memory interfacing

- The memory unit is an essential component in any digital

computer since it is needed for storing programs and
data. The memory unit that communicate directly with the
CPU is called the main memory.

Devices that provide backup storage are called auxiliary

memory. The most common auxiliary memory devices used
in computer systems are magnetic disks and tapes. They
are used for storing system programs, large data les, and
other backup information. Only programmes and data
currently needed by the processor reside in main memory.
All other information is stored in auxiliary memory and
transferred to main memory when needed.

The total memory capacity of a computer can be

visualised as being a hierarchy of components. The
memory
hierarchy
system
consist of
all storage
devices
employed
in a
computer
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 system from the slow but high capacity auxiliary memory to
a relatively faster memory, and even smaller and faster
cache memory accessible to the high speed processing
logic.

The cache memory is employed to computer systems to

compensate for the speed di erential between main
memory access time and processor logic. The cache is
used for storing segments of programs currently being
executed in the CPU and temporary data frequently needed
in the present calculations.

While the IO processor manages Data transfers between

auxiliary memory and main memory, the cache organisation
is concerned with the transfer of information between main
memory and CPU.

Auxiliary and cache memories are used for di erent

purposes. The cache holds those parts of the program and
data that are most heavily used, while the auxiliary memory
hold those parts that are not presently used by the CPU.
Moreover, the CPU has direct access to both cache and
main memory but not to auxiliary memory. The transfer from
auxiliary memory to main memory is usually done by means
of direct memory access of large blocks of data.

Main memory
- The main memory is the central storage unit in a
computer system. It is a relatively large and fast memory
used to store programs and data during the computer
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 operation. The principal technology used for the main
memory is based on semiconductor integrated circuit.
Integrated circuit RAM chips are available in two
possible operating modes, static and dynamic.

The static RAM (SRAM) consists essentially of internal ip-

op ops that stores the binary information. The dynamic
RAM stores the binary information in the form of electric
charges that are applied to capacitor. The capacitors are
provided inside the chip by MOS transistors.

The dynamic RAM (DRAM) o ers reduced power

consumption and larger storage capacity in a single
memory chip. The static RAM is easier to use and has
shorter read and write cycles.

ROM(read only memory) is the type of computer memory

that is used to permanently store data that does not need
to be modi ed. ROM is non-volatile memory, which means
that the data stored in it is retained even when the power is
turned o . ROM is typical used to store the computers
BIOS, which contains the instruction for booting the
computer, as well as rmware for other hardware devices.

ROM consumes less power compared to other types of

memory, which makes it an ideal memory for portable
devices. The capacity of ROM is typically Limited, can be
relatively expensive compare to the other types of memory,
such as hard drives or SSD.

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 4

 Memory Interfacing

Memory interfacing is a crucial aspect of computer system

design that involves connecting various types of memory
devices to the central processing unit (CPU) and other
peripheral devices. Memory is essential for storing data and
instructions that the CPU needs to process during program
execution. Di erent types of memory, such as RAM
(Random Access Memory), ROM (Read-Only Memory), and
various external storage devices, play speci c roles in the
functioning of a computer system.

Key Concepts in Memory Interfacing

• Address Bus: The address bus is a set of wires that

carry memory addresses from the CPU to the memory
module. The number of address lines determines the
maximum memory capacity that can be addressed. For
example, a 16-bit address bus can address up to 64KB
(2^16) of memory locations.

• Data Bus: The data bus is a set of wires that enable

the bidirectional transfer of data between the CPU and
memory module. The width of the data bus determines
the amount of data that can be transferred in a single
operation. For instance, a 32-bit data bus can transfer
32 bits (4 bytes) of data at a time.

• Control Signals: These signals manage the ow of

data between the CPU and memory, indicating whether

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 it is a read operation, write operation or other control
actions like enabling memory access.

• Memory Decoding: Memory decoding is the

process of interpreting the address lines to select a
speci c memory location. It ensures that the CPU can
access the intended memory device accurately.

Memory Interfacing

• Memory Types: Di erent memory technologies,

such as SRAM (Static RAM) and DRAM (Dynamic
RAM), have distinct characteristics, including speed,
cost, and volatility. The memory interfacing design
should consider these aspects based on the system’s
requirements.

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 • Memory Hierarchy: Modern computer systems
often use a memory hierarchy to optimise performance.
This hierarchy includes multiple levels of memory, such
as cache, main memory, and secondary storage, with
varying access speeds and capacities.

• Interfacing with I/O Devices: Memory

interfacing also extends to communication between the
CPU and input/output (I/O) devices, such as hard
drives, solid-state drives, and peripherals.

Memory Organisation, Static and Dynamic

Memory allocation is an important aspect of computer
programming, especially when it comes to creating and
managing data structures. When writing code, memory is used to
store variables and data, which can either be allocated statically
or dynamically.

Static Memory Allocation:

Static memory allocation is a memory management

technique that involves reserving a xed amount of memory
for a variable at the time of program compilation. The
memory is allocated at compile time, and the memory
remains xed throughout the life of the program. Static
memory allocation is commonly used for global variables,
static variables, and arrays.

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 Static variables are declared outside the main function and
are available throughout the program. These variables are
allocated memory at the time of program compilation.
Global variables are like static variables but are accessible
from all the functions in the program. Arrays are also
allocated memory at the time of program compilation, and
their size is xed.

Advantages of Static Memory Allocation:

Faster Access: Since the memory is allocated at compile

time, accessing static memory is faster compared to
dynamic memory. This is because the memory address is
known at the time of compilation.

No Overhead: Static memory allocation does not require any

runtime overhead for memory allocation and deallocation.
This makes it more e cient than dynamic memory
allocation.

Persistent Data: Static variables and arrays retain their data

throughout the life of the program. This is useful when data
needs to be shared between di erent functions.

Disadvantages of Static Memory Allocation

Limited Flexibility: Static memory allocation is in exible

because the size of the memory is xed at compile time.
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 This means that if the size of the data structure needs to be
changed, the entire program needs to be recompiled.

Wastage of Memory: If the size of the data structure is not

known in advance, static memory allocation can result in
the wastage of memory.

Limited Scope: Static variables are only accessible within

the function where they are de ned, or globally if they are
de ned outside of any function.

Dynamic Memory Allocation:

Dynamic memory allocation is a memory management

technique that involves reserving memory for variables at
runtime. This means that memory is allocated and
deallocated as required during the program execution.
Dynamic memory allocation is commonly used for creating
data structures such as linked lists, trees, and dynamic
arrays.

The dynamic memory allocation process involves using

functions such as malloc(), calloc(), realloc(), and free().
Malloc() function allocates memory in bytes and returns a
pointer to the allocated memory. Calloc() function allocates
memory and initialises it to zero. Realloc() function is used
to change the size of an already allocated memory block.
Free() function deallocates the memory previously allocated
by malloc() or calloc().

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 Advantages of Dynamic Memory Allocation:
Flexible Memory Usage: Dynamic memory allocation allows
the size of the data structure to be changed dynamically
during program execution. This makes it more exible than
static memory allocation.

Ef cient Memory Usage: Dynamic memory allocation allows

memory to be allocated only when it is needed, which
makes it more e cient than static memory allocation. This
results in less wastage of memory.

Global Access: Dynamic memory can be accessed globally,

which means that it can be shared between di erent
functions.

Disadvantages of Dynamic Memory Allocation:

Slower Access: Accessing dynamic memory is slower

compared to static memory because the memory address
is not known at compile time. The memory address must be
looked up during program execution.

Memory Leaks: Dynamic memory allocation can result in

memory leaks if memory is not deallocated properly. This
can cause the program to crash or slow down.
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 Fragmentation: Dynamic memory allocation can result in
memory fragmentation if the memory is not allocated and
deallocated properly. Memory fragmentation occurs when
there are small unused gaps between allocated memory
blocks. These gaps can prevent larger memory blocks from
being allocated, even if there is enough total memory
available.

Difference

Static Memory Dynamic Memory

Allocation Allocation
It allows allocation of Itallows the allocation of
memory at compile time memory at execution time
(Compile-time). (Run-time).
It uses the stack memory for It uses heap memory for
management and storage. management and storage.
Static memory is xed and Dynamic memory is not
hence cannot be reused for xed and can be reused and
di erent applications. changed for di erent
applications.
Allocation of memory is Memory can be allocated or
permanent and cannot be changed at any point in
changed. time.

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 Static Memory Dynamic Memory
Allocation Allocation
This is used in an array. This is used in linked lists.

Execution is faster and Execution is slower.

saves running time
This process is simple for This process is complicated
static allocation. or complex for dynamic
allocation.

Memory Hierarchy

In the computer system design, Memory Hierarchy is an

enhancement to organise the memory such that it can
minimise the access time.The memory hierarchy was
developed based on a program behaviour known as locality
of references.The gure below clearly demonstrates the
di erent levels of the memory hierarchy.

The Computer memory hierarchy looks like a pyramid

structure which is used to describe the differences among
memory types. It separates the computer storage based
on hierarchy.

Level 0: CPU registers

Level 1: Cache memory

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 Level 2: Main memory or primary memory

Level 3: Magnetic disks or secondary memory

Level 4: Optical disks or magnetic types or tertiary Memory

Memory Hierarchy

In Memory Hierarchy the cost of memory, capacity is inversely

proportional to speed. Here the devices are arranged in a
manner Fast to slow, that is form register to Tertiary memory.

Let us discuss each level in detail:

Level-0 − Registers

The registers are present inside the CPU. As they are present
inside the CPU, they have least access time. Registers are most
expensive and smallest in size generally in kilobytes. They are
implemented by using Flip-Flops.

Level-1 − Cache

Cache memory is used to store the segments of a program

that are frequently accessed by the processor. It is expensive

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 and smaller in size generally in Megabytes and is implemented
by using static RAM.

Level-2 − Primary or Main Memory

It directly communicates with the CPU and with auxiliary

memory devices through an I/O processor. Main memory is
less expensive than cache memory and larger in size generally
in Gigabytes. This memory is implemented by using dynamic
RAM.

Level-3 − Secondary storage

Secondary storage devices like Magnetic Disk are present

at level 3. They are used as backup storage. They are cheaper
than main memory and larger in size generally in a few TB.

Level-4 − Tertiary storage

Tertiary storage devices like magnetic tape are present at level

4. They are used to store removable files and are the cheapest
and largest in size (1-20 TB).

Let us see the memory levels in terms of size, access time,

bandwidth.

Level Register Cache Primary Seconda

memory ry
memory
Bandwidt 4k to 32k 800 to 5k 400 to 2k 4 to 32
h MB/sec MB/sec MB/sec MB/sec
Size Less than Less than Less than Greater
1KB 4MB 2 GB than 2 GB
Access 2 to 3 to 10 80 to 400 5ms
time 5nsec nsec nsec
Managed Compiler Hardware Operating OS or
by system user
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 Why memory Hierarchy is used in systems?

Memory hierarchy is arranging different kinds of storage

present on a computing device based on speed of access. At
the very top, the highest performing storage is CPU registers
which are the fastest to read and write to. Next is cache
memory followed by conventional DRAM memory, followed by
disk storage with different levels of performance including SSD,
optical and magnetic disk drives.

To bridge the processor memory performance gap, hardware

designers are increasingly relying on memory at the top of the
memory hierarchy to close / reduce the performance gap. This
is done through increasingly larger cache hierarchies (which
can be accessed by processors much faster), reducing the
dependency on main memory which is slower.

Associative Memory
Associative memory is also known as content addressable
memory (CAM) or associative storage or associative array.
It is a special type of memory that is optimised for
performing searches through data, as opposed to providing
a simple direct access to the data based on the address.

It can store the set of patterns as memories when the

associative memory is being presented with a key pattern,
it responds by producing one of the stored pattern which
closely resembles or relates to the key pattern.

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 It can be viewed as data correlation here. Input data is
correlated with that of stored data on the CAM.

The block diagram of associative memory is shown

in the figure. It includes a memory array and logic
for m words with n bits per word. The argument
register A and key register K each have n bits, one
for each bit of a word.

The match register M has m bits, one for each

memory word. Each word in memory is related in
parallel with the content of the argument register.

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 The words that connect the bits of the argument
register set an equivalent bit in the match register.
After the matching process, those bits in the match
register that have been set denote the fact that their
equivalent words have been connected.

Reading is proficient through sequential access to

memory for those words whose equivalent bits in
the match register have been set.

The key register supports a mask for selecting a

specific field or key in the argument word. The
whole argument is distinguished with each memory
word if the key register includes all 1's.

Hence, there are only those bits in the argument

that have 1's in their equivalent position of the key
register are compared. Therefore, the key gives a
mask or recognising a piece of data that determines
how the reference to memory is created.

The following figure can define the relation between

the memory array and the external registers in
associative memory.

The cells in the array are considered by the letter C

with two subscripts. The first subscript provides the
word number and the second determines the bit
position in the word. Therefore cell Cij is the cell for
bit j in word i.
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 A bit in the argument register is compared with all
the bits in column j of the array supported that Kj =
1. This is completed for all columns j = 1, 2 . . . , n.

If a match appears between all the unmasked bits of

the argument and the bits in word i, the equivalent
bit Mi in the match register is set to 1. If one or
more unmasked bits of the argument and the word
do not match, Mi is cleared to 0.

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 Applications
It can be used in memory allocation format.

It is widely used in the database management systems.

It is used in image processing applications to search for

speci c features or patterns within an image.

It is used in arti cial intelligence applications such as expert

systems and pattern recognition.

It can be used in database management systems.

Advantages
It is used where search time needs to be less or short.

It is suitable for parallel searches.

It is often used to speedup databases.

Disadvantages
It is more expensive than RAM.

Each cell must have storage capability and logical circuits

for matching its content with external argument.

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 Cache Memory
Cache memory is a small, high-speed storage area in a
computer. The cache is a smaller and faster memory that
stores copies of the data from frequently used main
memory locations.

There are various independent caches in a CPU, which

store instructions and data. The most important use of
cache memory is that it is used to reduce the average time
to access data from the main memory.

By storing this information closer to the CPU, cache

memory helps speed up the overall processing time. Cache
memory is much faster than the main memory (RAM). When
the CPU needs data, it rst checks the cache. If the data is
there, the CPU can access it quickly. If not, it must fetch the
data from the slower main memory.

Characteristics of Cache Memory

Cache memory is an extremely fast memory type that acts

as a bu er between RAM and the CPU.

Cache Memory holds frequently requested data and

instructions so that they are immediately available to the
CPU when needed.
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 Cache memory is costlier than main memory or disk
memory but more economical than CPU registers.

Cache Memory is used to speed up and synchronise with a

high-speed CPU.

Cache Memory

Levels of Memory
Level 1 or Register: It is a type of memory in which data is
stored and accepted that are immediately stored in the
CPU. The most commonly used register is Accumulator,
Program counter , Address Register, etc.

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 Level 2 or Cache memory: It is the fastest memory that has
faster access time where data is temporarily stored for
faster access.

Level 3 or Main Memory: It is the memory on which the

computer works currently. It is small in size and once power
is o data no longer stays in this memory.

Level 4 or Secondary Memory: It is external memory that is

not as fast as the main memory but data stays permanently
in this memory.

Cache Performance
When the processor needs to read or write a location in the
main memory, it rst checks for a corresponding entry in
the cache.

If the processor nds that the memory location is in the

cache, a Cache Hit has occurred and data is read from the
cache.

If the processor does not nd the memory location in the

cache, a cache miss has occurred. For a cache miss, the
cache allocates a new entry and copies in data from the
main memory, then the request is ful lled from the contents
of the cache.
The performance of cache memory is frequently measured
in terms of a quantity called Hit ratio.

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 Hit Ratio(H) = hit / (hit + miss) = no. of hits/total accesses
Miss Ratio = miss / (hit + miss) = no. of miss/total accesses
= 1 - hit ratio(H)

We can improve Cache performance using higher cache

block size, and higher associativity, reduce miss rate,
reduce miss penalty, and reduce the time to hit in the
cache.

Cache Mapping
There are three di erent types of mapping used for the
purpose of cache memory which is as follows:

• Direct Mapping
• Associative Mapping
• Set-Associative Mapping

Direct Mapping

The simplest technique, known as direct mapping, maps

each block of main memory into only one possible cache
line. or In Direct mapping, assign each memory block to a

speci c line in the cache. If a line is previously taken up by

a memory block when a new block needs to be loaded, the
old block is trashed. An address space is split into two
parts index eld and a tag eld.

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 The cache is used to store the tag eld whereas the rest is
stored in the main memory. Direct mapping`s performance
is directly proportional to the Hit ratio.

i = j modulo m
where
i = cache line number
j = main memory block number
m = number of lines in the cache

Direct Mapping

For purposes of cache access, each main memory address

can be viewed as consisting of three elds. The least
signi cant w bits identify a unique word or byte within a
block of main memory. In most contemporary machines,
the address is at the byte level. The remaining s bits specify
one of the 2 s blocks of main memory. The cache logic
interprets these s bits as a tag of s-r bits (the most

signi cant portion) and a line eld of r bits. This latter eld
identi es one of the m=2 r lines of the cache. Line o set is
index bits in the direct mapping.

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 Direct Mapping - Structure

Associative Mapping
In this type of mapping, associative memory is used to
store the content and addresses of the memory word. Any
block can go into any line of the cache. This means that the
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 word id bits are used to identify which word in the block is
needed, but the tag becomes all of the remaining bits. This
enables the placement of any word at any place in the
cache memory. It is considered to be the fastest and most
exible mapping form. In associative mapping, the index
bits are zero.

Associative Mapping Structure

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 Set-Associative Mapping
This form of mapping is an enhanced form of direct
mapping where the drawbacks of direct mapping are
removed. Set associative addresses the problem of
possible thrashing in the direct mapping method. It does
this by saying that instead of having exactly one line that a
block can map to in the cache, we will group a few lines
together creating a set . Then a block in memory can map
to any one of the lines of a speci c set. Set-associative
mapping allows each word that is present in the cache can
have two or more words in the main memory for the same
index address. Set associative cache mapping combines
the best of direct and associative cache mapping
techniques. In set associative mapping the index bits are
given by the set o set bits. In this case, the cache consists
of a number of sets, each of which consists of a number of
lines.

Set-Associative Mapping

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 Relationships in the Set-Associative Mapping can be de ned
as:

m=v*k
i= j mod v

where
i = cache set number
j = main memory block number
v = number of sets
m = number of lines in the cache number of sets
k = number of lines in each set

Set-Associative Mapping Structure 28


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 Application of Cache Memory
• Primary Cache: A primary cache is always located on
the processor chip. This cache is small and its access
time is comparable to that of processor registers.

• Secondary Cache: Secondary cache is placed

between the primary cache and the rest of the
memory. It is referred to as the level 2 (L2) cache.
Often, the Level 2 cache is also housed on the
processor chip.

• Spatial Locality of Reference: Spatial Locality of

Reference says that there is a chance that the element
will be present in close proximity to the reference point
and next time if again searched then more close
proximity to the point of reference.

• Temporal Locality of Reference: Temporal Locality of

Reference uses the Least recently used algorithm will
be used. Whenever there is page fault occurs within a
word will not only load the word in the main memory
but the complete page fault will be loaded because the
spatial locality of reference rule says that if you are
referring to any word next word will be referred to in its
register that’s why we load complete page table so the
complete block will be loaded.

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 Advantages
• Cache Memory is faster in comparison to main
memory and secondary memory.

• Programs stored by Cache Memory can be executed

in less time.

• The data access time of Cache Memory is less than

that of the main memory.

• Cache Memory stored data and instructions that are

regularly used by the CPU, therefore it increases the
performance of the CPU.

Disadvantages
• Cache Memory is costlier than primary memory and
secondary memory .

• Data is stored on a temporary basis in Cache Memory.

• Whenever the system is turned o , data and

instructions stored in cache memory get destroyed.

• The high cost of cache memory increases the price of

the Computer System.

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 Cache memory is important because it helps speed up the
processing time of the CPU by providing quick access to
frequently used data, improving the overall performance of
the computer.

Is cache memory volatile?

Yes, cache memory is volatile, meaning it loses all stored
data when the computer is turned o , just like RAM.

Virtual Memory
Virtual memory is a memory management technique used
by operating systems to give the appearance of a large,
continuous block of memory to applications, even if the
physical memory (RAM) is limited. It allows the system to
compensate for physical memory shortages, enabling larger
applications to run on systems with less RAM.

The size of virtual storage is limited by the addressing

scheme of the computer system and the amount of
secondary memory available not by the actual number of
main storage locations.

Working of Virtual Memory

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 It is a technique that is implemented using both hardware
and software. It maps memory addresses used by a
program, called virtual addresses, into physical addresses
in computer memory.

• All memory references within a process are logical

addresses that are dynamically translated into physical
addresses at run time. This means that a process can
be swapped in and out of the main memory such that
it occupies di erent places in the main memory at
di erent times during the course of execution.

• A process may be broken into a number of pieces and

these pieces need not be continuously located in the
main memory during execution. The combination of
dynamic run-time address translation and the use of a
page or segment table permits this.

If these characteristics are present then, it is not necessary

that all the pages or segments are present in the main
memory during execution. This means that the required
pages need to be loaded into memory whenever required.
Virtual memory is implemented using Demand Paging or
Demand Segmentation.

Types of Virtual Memory

In a computer, virtual memory is managed by the Memory
Management Unit (MMU), which is often built into the CPU.
The CPU generates virtual addresses that the MMU
translates into physical addresses.

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 There are two main types of virtual memory:

• Paging
• Segmentation

Paging
Paging divides memory into small xed-size blocks called
pages. When the computer runs out of RAM, pages that
aren’t currently in use are moved to the hard drive, into an
area called a swap le. The swap le acts as an extension
of RAM. When a page is needed again, it is swapped back
into RAM, a process known as page swapping. This

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Demand Paging

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 ensures that the operating system (OS) and applications
have enough memory to run.

Demand Paging: The process of loading the page into

memory on demand (whenever a page fault occurs) is
known as demand paging. The process includes the
following steps are as follows:

• If the CPU tries to refer to a page that is currently not

available in the main memory, it generates an interrupt
indicating a memory access fault.

• The OS puts the interrupted process in a blocking

state. For the execution to proceed the OS must bring
the required page into the memory.

• The OS will search for the required page in the logical

address space.

• The required page will be brought from logical address

space to physical address space. The page
replacement algorithms are used for the decision-
making of replacing the page in physical address
space.

• The page table will be updated accordingly.

• The signal will be sent to the CPU to continue the

program execution and it will place the process back
into the ready state.

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 Hence whenever a page fault occurs these steps are
followed by the operating system and the required page is
brought into memory.

What is Page Fault Service Time?

The time taken to service the page fault is called page fault
service time. The page fault service time includes the time
taken to perform all the above six steps.

Let Main memory access time is: m

Page fault service time is: s
Page fault rate is : p
Then, E ective memory access time = (p*s) + (1-p)*m

Segmentation
Segmentation divides virtual memory into segments of
di erent sizes. Segments that aren’t currently needed can
be moved to the hard drive. The system uses a segment
table to keep track of each segment’s status, including
whether it’s in memory, if it’s been modi ed, and its
physical address. Segments are mapped into a process’s
address space only when needed.

Combining Paging and Segmentation

Sometimes, both paging and segmentation are used
together. In this case, memory is divided into pages, and
segments are made up of multiple pages. The virtual
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 address includes both a segment number and a page
number.

Virtual Memory vs Physical Memory

When talking about the di erences between virtual memory
and physical memory, the biggest distinction is speed. RAM
is much faster than virtual memory, but it is also more
expensive.

When a computer needs storage for running programs, it

uses RAM rst. Virtual memory, which is slower, is used
only when the RAM is full.

Feature Virtual Memory Physical Memory (RAM)

De nition An abstraction that The actual hardware
extends the available (RAM) that stores data
memory by using disk and instructions currently
storage being used by the CPU
Location On the hard drive or SSD On the computer’s
motherboard
Speed Slower (due to disk I/O Faster (accessed directly
operations) by the CPU)
Capacity Larger, limited by disk Smaller, limited by the
space amount of RAM installed
Cost Lower (cost of additional Higher (cost of RAM
disk storage) modules)
Data Access Indirect (via paging and Direct (CPU can access
swapping) data directly)
Volatility Non-volatile (data Volatile (data is lost when
persists on disk) power is o )

What is Swapping?
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 Swapping is a process out means removing all of its pages
from memory, or marking them so that they will be removed
by the normal page replacement process. Suspending a
process ensures that it is not runnable while it is swapped
out. At some later time, the system swaps back the process
from the secondary storage to the main memory. When a
process is busy swapping pages in and out then this
situation is called thrashing.

Swappinghierar

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 What is Thrashing?
At any given time, only a few pages of any process are in
the main memory, and therefore more processes can be
maintained in memory. Furthermore, time is saved because
unused pages are not swapped in and out of memory.
However, the OS must be clever about how it manages this
scheme. In the steady state practically, all of the main
memory will be occupied with process pages, so that the
processor and OS have direct access to as many
processes as possible. Thus when the OS brings one page
in, it must throw another out. If it throws out a page just
before it is used, then it will just have to get that page again
almost immediately. Too much of this leads to a condition
called Thrashing. The system spends most of its time
swapping pages rather than executing instructions. So a
good page replacement algorithm is required.

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 Causes of Thrashing

1. High Degree of Multiprogramming: If the number of

processes keeps on increasing in the memory then the
number of frames allocated to each process will be
decreased. So, fewer frames will be available for each
process. Due to this, a page fault will occur more frequently
and more CPU time will be wasted in just swapping in and
out of pages and the utilization will keep on decreasing.

For example:
Let free frames = 400

Case 1: Number of processes = 100

Then, each process will get 4 frames.
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 Case 2: Number of processes = 400
Each process will get 1 frame.
Case 2 is a condition of thrashing, as the number of
processes is increased, frames per process are decreased.
Hence CPU time will be consumed just by swapping
pages.

2. Lacks of Frames: If a process has fewer frames then

fewer pages of that process will be able to reside in
memory and hence more frequent swapping in and out will
be required. This may lead to thrashing. Hence a su cient
amount of frames must be allocated to each process in
order to prevent thrashing.

Recovery of Thrashing
• Do not allow the system to go into thrashing by
instructing the long-term scheduler not to bring the
processes into memory after the threshold.

• If the system is already thrashing then instruct the

mid-term scheduler to suspend some of the processes
so that we can recover the system from thrashing.

Performance in Virtual Memory

• Let p be the page fault rate( 0 <= p <= 1).

• if p = 0 no page faults

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 • if p =1, every reference is a fault.

E ective access time (EAT) = (1-p)* Memory Access Time

+ p * Page fault time.
Page fault time = page fault overhead + swap out + swap in
+restart overhead
The performance of a virtual memory management system
depends on the total number of page faults, which depend
on “paging policies” and “frame allocation“

Frame Allocation
A number of frames allocated to each process in either
static or dynamic.

• Static Allocation: The number of frame allocations to a

process is xed.

• Dynamic Allocation: The number of frames allocated

to a process changes.

Paging Policies
• Fetch Policy: It decides when a page should be loaded
into memory.

• Replacement Policy: It decides which page in memory

should be replaced.

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 • Placement Policy: It decides where in memory should
a page be loaded.

Applications of Virtual memory

Virtual memory has the following important characteristics
that increase the capabilities of the computer system. The
following are ve signi cant characteristics of Lean.

• Increased E ective Memory: One major practical

application of virtual memory is, virtual memory
enables a computer to have more memory than the
physical memory using the disk space. This allows for
the running of larger applications and numerous
programs at one time while not necessarily needing an
equivalent amount of DRAM.

• Memory Isolation: Virtual memory allocates a unique

address space to each process and that also plays a
role in process segmentation. Such separation
increases safety and reliability based on the fact that
one process cannot interact with and or modify
another’s memory space through a mistake, or even a
deliberate act of vandalism.

• E cient Memory Management: Virtual memory also

helps in better utilization of the physical memories
through methods that include paging and
segmentation. It can transfer some of the memory
pages that are not frequently used to disk allowing
RAM to be used by active processes when required in

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 a way that assists in e cient use of memory as well as
system performance.

• Simpli ed Program Development: For case of

programmers, they don’t have to consider physical
memory available in a system in case of having virtual
memory. They can program ‘as if’ there is one big
block of memory and this makes the programming
easier and more e cient in delivering more complex
applications.

How to Manage Virtual Memory?

Here are 5 key points on how to manage virtual memory:

1. Adjust the Page File Size

• Automatic Management: All contemporary operating

systems including Windows contain the auto-
con guration option for the size of the empirical page
le. But depending on the size of the RAM, they are
set automatically, although the user can manually
adjust the page le size if required.

• Manual Con guration: For tuned up users, the setting

of the custom size can sometimes boost up the
performance of the system. The initial size is usually
advised to be set to the minimum value of 1. To set the
size of the swap space equal to 5 times the amount of
physical RAM and the maximum size 3 times the
physical RAM.

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 2. Place the Page File on a Fast Drive

• SSD Placement: If this is feasible, the page le should

be stored in the SSD instead of the HDD as a storage
device. It has better read and write times, and the
virtual memory may prove benifecial in an SSD.

• Separate Drive: Regarding systems having multiple

drives involved, the page le needs to be placed on a
di erent drive than the os and that shall in turn
improve its performance.

3. Monitor and Optimise Usage

• Performance Monitoring: Employ the software tools

used in monitoring the performance of the system in
tracking the amounts of virtual memory. High page le
usage may signify that there is a lack of physical RAM
or that virtual memory needs a change of settings or
addition in physical RAM.

• Regular Maintenance: Make sure there is no toolbar or

other application running in the background, take time
and uninstall all the tool bars to free virtual memory.

4. Disable Virtual Memory for SSDs (with Su cient RAM)

• Su cient RAM: If for instance your system has a big

physical memory, for example 16GB and above then it
would be advised to freeze the page le in order to
minimize SSD usage. But it should be done, in my
opinion, carefully and only if the additional signals that
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 one decides to feed into his applications should not
likely use all the available RAM.

5. Optimise System Settings

• System Con guration: Change some general

properties of the system concerning virtual memory
e ciency. This also involves enabling additional
control options in Windows such as adjusting
additional system setting option on the operating
system, or using other options in di erent operating
systems such as Linux that provides di erent tools
and commands to help in adjusting how virtual
memory is utilised.

• Regular Updates: Ensure that your drivers are run in

their newest version because new releases contain
some enhancements and issues regarding memory
management.

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 Advantages of Virtual Memory
• More processes may be maintained in the main
memory: Because we are going to load only some of
the pages of any particular process, there is room for
more processes. This leads to more e cient utilisation
of the processor because it is more likely that at least
one of the more numerous processes will be in the
ready state at any particular time.

• A process may be larger than all of the main memory:

One of the most fundamental restrictions in
programming is lifted. A process larger than the main
memory can be executed because of demand paging.
The OS itself loads pages of a process in the main
memory as required.

• It allows greater multiprogramming levels by using less

of the available (primary) memory for each process.

• It has twice the capacity for addresses as main

memory.

• It makes it possible to run more applications at once.

• Users are spared from having to add memory modules

when RAM space runs out, and applications are
liberated from shared memory management.

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 • When only a portion of a program is required for
execution, speed has increased.

• Memory isolation has increased security.

• It makes it possible for several larger applications to

run at once.

• Memory allocation is comparatively cheap.

• It doesn’t require outside fragmentation.

• It is e cient to manage logical partition workloads

using the CPU.

• Automatic data movement is possible.

Disadvantages of Virtual Memory

• It can slow down the system performance, as data
needs to be constantly transferred between the
physical memory and the hard disk.

• It can increase the risk of data loss or corruption, as

data can be lost if the hard disk fails or if there is a
power outage while data is being transferred to or
from the hard disk.

• It can increase the complexity of the memory

management system, as the operating system needs
to manage both physical and virtual memory.

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 Data Path Design for read/write access

A data path is a collection of functional units such as

arithmetic logic units or multipliers that perform data
processing operations, registers, and buses. Along with the
control unit, it composes the central processing unit (CPU).
A larger data path can be made by joining more than one
data path using multiplexers.

BUS
In early computers BUS were parallel electrical wires with
multiple hardware connections. Therefore a bus is a
communication system that transfers data between
components inside a computer, or between computers. It
includes hardware components like wires, optical bers, etc
and software, including communication protocols. The
Registers, ALU, and the interconnecting BUS are
collectively referred to as data paths.

Types of the bus

There are mainly three type of bus:-

Address bus: Transfers memory addresses from the

processor to components like storage and input/output
devices. It’s one-way communication.

Data bus: carries the data between the processor and other
components. The data bus is bidirectional.
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 Control bus: carries control signals from the processor to
other components.The control bus also carries the clock’s
pulses. The control bus is unidirectional.

The bus can be dedicated, i.e., it can be used for a single

purpose or it can be multiplexed, i.e., it can be used for
multiple purposes. when we would have di erent kinds of
buses, di erent types of bus organisations will take place.

What is Data Path?

Suppose that the CPU needs to carry out any data
processing action, such as copying data from memory to a
register and vice versa, moving register content from one
register to another, or adding two numbers in the ALU.
Therefore, whenever a data processing action takes place
in the CPU, the data involved for that operation follows a
particular path, or data path.

Data paths are made up of various functional components,

such as multipliers or arithmetic logic units. Data path is
required to do data processing operations.

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 One Bus Organisation

In one bus organisation, a single bus is used for multiple

purposes. A set of general-purpose registers, program
counters, instruction registers, memory address registers
(MAR), memory data registers (MDR) are connected with
the single bus. Memory read/write can be done with MAR
and MDR. The program counterpoints to the memory
location from where the next instruction is to be fetched.
Instruction register is that very register will hold the copy of
the current instruction. In the case of one bus organization,
at a time only one operand can be read from the bus.

As a result, if the requirement is to read two operands for

the operation then the read operation needs to be carried
twice. So that’s why it is making the process a little longer.
One of the advantages of one bus organisation is that it is
one of the simplest and also this is very cheap to
implement.

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 Two Bus Organisation
To overcome the disadvantage of one bus organisation
another architecture was developed known as two bus
organisation. In two bus organisations, there are two buses.
The general-purpose register can read/write from both the
buses. In this case, two operands can be fetched at the
same time because of the two buses. One bus fetch
operand for ALU and another bus fetch for register. The
situation arises when both buses are busy fetching
operands, the output can be stored in a temporary register
and when the buses are free, the particular output can be
dumped on the buses.

There are two versions of two bus organisations, i.e., in-bus

and out-bus. From in-bus, the general-purpose register can
read data and to the out bus, the general-purpose registers
can write data. Here buses get dedicated.

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 Three Bus Organisation
In three bus organisations we have three buses, OUT bus1,
OUT bus2, and an IN bus. From the out buses, we can get
the operand which can come from the general-purpose
register and evaluated in ALU and the output is dropped on
In Bus so it can be sent to respective registers. This
implementation is a bit complex but faster in nature
because in parallel two operands can ow into ALU and out
of ALU. It was developed to overcome the busy waiting
problem of two bus organisations. In this structure after
execution, the output can be dropped on the bus without
waiting because of the presence of an extra bus. The
structure is given below in the gure.

The main advantages of multiple bus organisations over the

single bus are as given below.
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 1. Increase in size of the registers.
2. Reduction in the number of cycles for execution.
3. Increases the speed of execution or we can say faster
execution.

Data Path Design

Data path design denotes the physical implementation of

any computer’s internal circuitry that boosts data
procession and movement. This represents a section of the
CPU (Central Processing Unit) that deals with the data
section. It requires arithmetic logic units (ALU), registers,
and multiplexers’ arrangements. It is a great way to assess
the performance and e ciency of a computer’s operations,
including fetching, decoding, and executing data. It ensures
smooth data ow by encompassing an organisation and
interconnections of several components. A well-designed
data path can extensively reduce bottlenecks, improve
system performance, and optimises resource utilisation. It
e ectively contributes to the e ciency of computer
architecture.

To leverage the bene ts of learning data path design, be a

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 Types of Data Path Design in Computer
Architecture
The interconnection of BUS with ALU and registers is a
data path that will be elaborated on later. These data paths
can be broadly divided into three types, as described
below.

Single Cycle
This has one CPI (Clock Cycle Per Instruction) and does not
divide instructions per CPI. In such data paths, only one
instruction is executed at one time. Besides, it does not
require any registers. In a single data path, the clock time is
longer than the other types. Overlapping the clock cycle
cannot be done with such data paths.

Multiple Cycle
Such data paths have variable CPIs. Here, instructions can
be segregated into arbitrary steps. Like a single cycle,
multiple cycles can also execute only one instruction at one
time. However, they need registers to carry further.
Moreover, the clock time is shorter than a single cycle.
Clock cycle overlapping isn’t possible in the case of
multiple cycles.

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 Pipeline
Such data paths do not have xed CPIs. Here, per stage,
instruction has one step. Unlike single and multiple cycles,
pipelines can execute multiple instructions at one time.
With that, it requires registers. Like multiple-cycle data
paths, the pipeline also requires a short time per clock
cycle. Plus, a clock cycle occurs in the case of pipeline
data paths.

Components Associated with Data Path

To execute the proper operation of a computing system, the
function units of the data path play a crucial role. Below are
the primary function units that are an inevitable part of data
path design.

Arithmetic Logic Unit (ALU)

It is one of the fundamental components of the data path.
ALU performs logical arithmetic operations on data like
addition, subtraction, division, multiplication, comparisons,
and bitwise operations. ALU primarily takes input data from
the register and performs an operation on the data to
produce the necessary output. It operates on binary data,
manipulating bits based on the control signals received
from the control unit.

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 Registers
These are small storage elements in a processor known for
their high speed. While processing data, it stores the data
temporarily. These data can be either intermediate results,
operands, or program counters. Registers are important for
fast data access, decreasing the requirement of retrieving
data from memory, which slows down the operation. Two
types of registers are available to serve di erent purposes.
General-purpose registers are required to hold data during
computation. On the other hand, special-purpose registers
store program status ags or addresses.

Program Counter

The program counter (PC) is a CPU register in the computer

processor which has the address of the next instruction to
be executed from memory. As each instruction gets
fetched, the program counter increases its stored value by
1. It is a digital counter needed for faster execution of tasks
and tracking the current execution point.

Instruction Register

In computing, an instruction register (IR) is the part of a

CPU's control unit that holds the instruction currently being
executed or decoded. An instruction register is the part of a
CPU's control unit that holds the instruction currently being
executed or decoded. The instruction register speci cally

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 holds the instruction and provides it to the instruction
decoder circuit.

Memory Address Register

The Memory Address Register (MAR) is the CPU register

that either store the memory address from which data will
fetch from the CPU or the address to which data will be
sent and stored. It is a temporary storage component in the
CPU (central processing unit) that temporarily stores the
address (location) of the data sent by the memory unit until
the instruction for the particular data is executed.

Memory Data Register

The memory data register (MDR) is the register in a

computer's processor, or central processing unit, CPU, that
stores the data being transferred to and from the immediate
access storage. Memory data register (MDR) is also known
as memory bu er register (MBR).

General Purpose Register

General-purpose registers are used to store temporary data

within the microprocessor, and it is a multipurpose register.
They can be used either by a programmer or by a user.

BUS
It is a communication system that transfers data between
various components of a computer or between two
computers. BUS is a collection of hardware components,
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 including optical bers and wire. It also has software
components, like communication protocols. It allows data
and instructions movement between memory, registers, and
other peripherals. ALU, registers, and various BUS together
are termed as data paths.

Multiplexers
A data path also has multiplexers. These are required to
select data from multiple sources and route these to an
appropriate destination. Multiplexers are essential for the
movement of data within a processor—these help in
selecting from di erent inputs along with directing them to
the component on the focal point. For instance, a
multiplexer may choose between two registers to evaluate
and source the ALU operation.

Control Unit
Any data path interacts with the control unit. This unit
generates control signals that coordinate the data path
component’s activities. It interprets instructions fetched
from memory and generates the necessary signals to
control data movement, ALU operations, and register
manipulations. These units ensure the proper execution of
instructions in the right sequence. Besides, it ensures a
synchronised data path function.

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 Final Words
Data path design plays a critical role in computer
architecture. This ensures e cient processing, movement,
and manipulation of data within a system. The components
of data path design, such as registers, buses, multiplexers,
the Arithmetic Logic Unit (ALU), and the control unit, work
in harmony to enable seamless data ow and execution of
instructions. With the advancement of technology, data
path design will keep evolving and continue shaping the
future of computer architecture.

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