VHDL: DATA-TYPES

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design (PVL204) 1
DATA TYPES

 Every data object in VHDL can hold a value that belongs to a set of
values. This set of values is specified by type declaration.

 A type is a name that is associated with a set of values and a set of

operations.

 The operations that can be performed on objects of these types, are

predefined in the language.

 All declaration of VHDL ports, signals and variables must specify

their corresponding type or subtype
• Example: signal A,B: std_logic;

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 2
DATA TYPES: CLASSIFICATION

 The VHDL provides the facility to define new types by using type
declarations and also to define a set of operations on these types by
writing functions that return values of this new type.
 The possible types in VHDL: Type
1. Scalar types: Values belonging to
these types appear in a sequential Scalar type
Composite
Access type File
type
order.
2. Composite types: These are
composed of elements of a single Integer type Array
type (an array type) or elements
of different types (a record type). Floating
record
point
3. Access types: These provide
access to objects of a given type Enumeration
(via pointers). type
4. File types: These provides access
to objects that contain a sequence Physical type
of values of a given type.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 3
SUBTYPES

 A subtype is a type with a constraint.

• The constraint specifies the subset of values for the type.
• The type is called the base type of the subtype.
• An object belong to a subtype if it is of the base type and if it satisfies the
constraint.
• Subtype declarations are used to declare subtypes.
• An object can be declared to either belong to a type or to a subtype.

 Subtypes are useful for range checking and for imposing additional
constraints on types.

 Examples of subtypes are

subtype MY_INTEGER is INTEGER range 48 to 156 ;
type DIGIT is ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9') ;
subtype MIDDLE is DIGIT range '3' to '7' ;

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 4
SCALAR TYPES

 The scalar type is ordered, therefore, relational operators can be used

on objects belong to this data-type.
• For example, BIT is a scalar type and the expression '0' < 1' is valid and
has H i.e. value TRUE.
 There are four different kinds of scalar types.
• Enumeration,
• Integer,
• Floating point,
• Physical.
 Integer types, floating point types, and physical types are classified as
numeric types.
 Further, enumeration and integer types are called discrete types since
these types have discrete values associated with them.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 5
ENUMERATION TYPES

 An enumeration type declaration defines a type that has a set of user-

defined values consisting of identifiers and character literals.
type MVL is ('U','0','1','Z);
type MICRO_OP is (LOAD, STORE, ADD, SUB, MUL, DIV);
subtype ARITH_OP is MICRO_OP range ADD to DIV;

 The order of values appearing in an enumeration type declaration

defines the lexical order for the values.

 Examples of objects defined for these types are

signal CONTROL_A: MVL;
signal CLOCK: MVL range '0' to '1'; -- Implicit subtype declaration.
variable IC: MICRO_OP := STORE; -- STORE is the initial value for IC.
variable ALU: ARITH_OP

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 6
ENUMERATION TYPES (CONT.)

 The predefined enumeration types of the language are CHARACTER,

BIT, BOOLEAN, and SEVERITY_LEVEL.

• Values belonging to the type CHARACTER constitute the 128 characters

of the ASCII character set. These values are called character literals and
are always written between two single quotes (' ').

• The predefined type BIT has the literals '0' and ‘1'.

• type BOOLEAN has literals FALSE and TRUE.

• type SEVERITY_LEVEL has the values NOTE, WARNING, ERROR,

and FAILURE;

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 7
INTEGER TYPES

 An integer type defines a type whose set of values fall within a specified
integer range.
type INDEX is range 0 to 15;
type WORD_LENGTH is range 31 downto 0;
subtype DATA_WORD is WORD_LENGTH range 15 downto 0;
type MY_WORD is range 4 to 6;

 Some object declarations using these types are

constant MUX_ADDRESS: INDEX := 5;
signal DATA_BUS: DATA_WORD;

• The position of each value of an integer type is the value itself.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 8
INTEGER SUBTYPES

 Predefined subtype of integer are

• Natural
• Positive

subtype natural is integer range 0 to integer'high;

subtype positive is integer range 1 to integer'high;

 When type natural is used in calculations, the calculations are carried out
using the base type, integer, and then checked to ensure that they fit the
subtype range of natural.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 9
INTEGER TYPES

 Example 1: Definition of a 4-bit subtype of integer:

subtype nat4 is natural range 0 to 15;
signal w, x, y , z : nat4 ;
Consider the signals values: x = 3, y = 4, z = 5
w <= x – y + z; --- w?

 Example 2: Definition of a 4-bit subtype of integer:

subtype nat4 is positive range 1 to 15;
signal w, x, y , z : nat4 ;
Consider the signals values: x = 3, y = 4, z = 5
w <= x – y + z; --- w?

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 10
FLOATING POINT TYPES

 A floating point type has a set of values in a given range of real numbers.

type TTL_VOLTAGE is range -5.5 to -1.4;

type REAL_DATA is range 0.0 to 31.9;

variable LENGTH: REAL_DATA range 0.0 to 15.9;

variable L1, L2, L3: REAL_DATA range 0.0 to 15.9;

subtype RD16 is REAL_DATA range 0.0 to 15.9;

variable LENGTH: RD16;
variable L1, L2, L3: RD16;

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 11
FLOATING POINT TYPES (CONT.)

 Floating point literals can also be expressed in an exponential form.

 The exponent represents a power of ten and the exponent value must be an
integer.

 The predefined floating point type is REAL.

 The range of REAL is again implementation dependent but it must at least

cover the range -1.0E38 to +1.0E38 and it must allow for at least six
decimal digits of precision.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 12
PHYSICAL TYPES

 The physical data type is used for values which have associated units.
Therefore, a physical type contains values that represent measurement of
some physical quantity, like time, length, voltage, and current.
 Values of this type are expressed as integer multiples of a base unit.
type CURRENT is range 0 to 1 E9
units
nA; -- (base unit) nano-ampere
uA = 1000 nA; -- micro-ampere
mA = 1000 μA; --milli-ampere
amp = 1000 mA; -- ampere
end units;
subtype FILTER_CURRENT is CURRENT range 10 μA to 5 mA;

• CURRENT is defined to be a physical type that contains values from 0 nA to

109 nA. The base unit is a nano-ampere while all others are derived units.
• The position number of a value is the number of base units represented by
that value. For example, 2 μA has a position of 2000.
Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 13
PHYSICAL TYPES (CONT.)

 Values of a physical type are called physical literals.

 Physical literals are written as an integer literal followed by the unit

name.

 The only predefined physical type is TIME and its range of base values,
which again is implementation dependent, must at least be -(231 - 1) to
+(231 - 1).

 The declaration of type TIME appears in package STANDARD

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 14
COMPOSITE DATE TYPES: (1) ARRAY

 A composite type represents a collection of values.

• An array type represents a collection of values all belonging to a single type.

 Declaration:
type data_bus is array (0 to 31) of BIT;

Variable x: data_bus;
Variable y: BIT;

Y := x(12);

type data_bus is array (31 downto 0) of BIT;

Variable x: data_bus;
Variable y: BIT;

Y := x(12);

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 15
COMPOSITE DATE TYPES: (2) RECORD

 Used to group elements of possibly different types into a single

VHDL object
• Elements are indexed via field names

 Record declaration and usage:

type binary is (ON, OFF);

Type switch_info is
record
status : binary;
IDnumber : integer;
end record;

variable switch : switch_info;

switch.status := ON; --status of the switch
switch. IDnumber := 20; -- e.g. number of switch

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 16
ACCESS TYPE

 The access type is similar to a pointer in other programming

languages.

 It dynamically allocates and deallocates storage space to the object.

 This capability is useful for implementing abstract data structures

(such as queues and first-in-first-out buffers) where the size of the
structure may not be known at compile time.

 The VHDL access type will not be discussed in detail in this module.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 17
QUESTIONS?

 What is data type? Explain its classification.

 How subtypes can add constraints to a type?
 Explain, how physical types are declared to represent physical quantities
such as distance, current, and time.
 What is the need of record data type? Explain with the help of an
example.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 18