Institute Of Space Technology

Islamabad

VLSI LAB
Lab # 06
“Switch Level Modelling”

Submitted To:
Sir Asad-Ur-Rehman

Submitted By
Asad Iqbal (200401033)
Hasnat Mubashir (200401049)
Waiz Yousaf (200401057)
Table of Contents
Objectives: .................................................................................................................................................... 3
Software: ....................................................................................................................................................... 3
Introduction:.................................................................................................................................................. 3
Task No 1 ...................................................................................................................................................... 4
Design of NOR Gate ................................................................................................................................. 4
Procedure: ............................................................................................................................................. 4
Design of NAND Gate .............................................................................................................................. 8
Procedure: ............................................................................................................................................. 8
Task Results: ......................................................................................................................................... 8
Design of NOT Gate ............................................................................................................................... 11
Procedure: ........................................................................................................................................... 11
Task Results: ....................................................................................................................................... 11
............................................................................................................................................................ 12
Task No 2 .................................................................................................................................................... 14
Implementation of OAI and AOI Logic Gates............................................................................................ 14
AOI Logic Diagram .................................................................................................................................... 14
Task No 3 .................................................................................................................................................... 15
2:1 MUX using TRANSMISSION GATE ............................................................................................. 15
Procedure: ........................................................................................................................................... 15
Task Results: ....................................................................................................................................... 15
Conclusion: ................................................................................................................................................. 17
Objectives:
 Implementation of NAND, NOR & NOT Gate Design in Vivado.
 Implementation of OAI & AOI Logic Gate Design of functions.
 Implementation of 2:1 Multiplexer using Transmission Gates.

Software:
 Vivado Software

Introduction:
This lab report focuses on the design and analysis of basic logic gates, advanced logic gates, and
implementation of a multiplexer using transfer gates.
CMOS Logic Gates:
The foundation of digital circuits lies in logic gates, the basic building blocks that process binary
information. In this lab s, attention is focused on CMOS (Complementary Metal-Oxide-
Semiconductor) logic gates - NOT, NAND, and NOR gates.
CMOS NOT Gate:
NOT Gate reverse the input logic state. NOT gate consist of two series connected MOSFETS,
one NMOS and one is PMOS.
CMOS NAND Gate:
NAND Gate is complementary of AND Gate .Here if any input is 0 then output is also 0.
CMOS NOR Gate:
NOR Gate is complementary of OR Gate .Here if any input is 1 then output is 0.

CMOS NOT CMOS NAND CMOS NOR

Once we get past the basic gates, then focuses into advanced logic gates, namely the AND-OR-
INVERT (AOI) and OR-AND-INVERT (OAI) gates. These gates offer a more compact
representation of complex Boolean functions and increase the efficiency of digital circuits. The
lab explores the implementation of complex Boolean expressions F= [ab+ac+bd] for AOI and
F=[(a+b)(a+c)(b+d)] for OAI.
Multiplexers play a key role in digital systems, enabling dynamic data routing based on control
signals. The last part of this report focuses on the design and analysis of a 2:1 multiplexer using
transmission gates.

Task No 1
Design of NOR Gate
Procedure:
 Defines a NOR gate with inputs a and b, output y, and complementary PMOS and
parallel NMOS transistors.
 Instantiates the NOR gate module and defines a testbench with registers a and b, and wire
y.
 Simulates the NOR gate behavior by sequentially toggling inputs a and b through
different combinations with a 5-unit delay.
 Observes the NOR gate's response to input changes during simulation.
 Stops the simulation after the last input combination with #5; $stop.

Task Results:
Design Code:
`timescale 1ns / 1ps

module LAB6T4_NOR_42(a,b,y );

input a,b;

output y;

supply1 vdd;

supply0 vss;
wire temp;

pmos p1(temp,vdd,b);

pmos p2(y,temp,a);

nmos n1(y,vss,a);

nmos n2 (y,vss,b);

endmodule

Test Bench:
`timescale 1ns / 1ps

module NOR_tb_42();

reg a,b;

wire y;

LAB6T4_NOR_42 uut(a,b,y);

initial

begin

a=1'b0; b=1'b0;

#5;

a=1'b0; b=1'b1;

#5;

a=1'b1; b=1'b0;
#5;

a=1'b1; b=1'b1;

#5; $stop;

end

endmodule

Output Waveform:
 Design of NAND Gate
Procedure:
 Defines a NAND gate with inputs a and b, output y, and complementary parallel PMOS
and series NMOS transistors.
 Instantiates the NAND gate module and defines a testbench with registers a and b, and
wire c.
 Simulates the NAND gate behavior by sequentially toggling inputs a and b through
different combinations with a 5-unit delay.
 Observes the NAND gate's response to input changes during simulation.
 Stops the simulation after the last input combination with #5;

Task Results:

Design Code:
`timescale 1ns / 1ps
module LAB6T2_NANDgate_42(a,b,y);
input a,b;
output y;
supply1 vdd;
supply0 vss;
wire temp;
pmos p1(y,vdd,a);
pmos p2(y,vdd,b);
nmos n1(y,temp,a);
nmos n2(temp,vss,b);
endmodule

Test Bench:
`timescale 1ns / 1ps

module LAB6T2_nand_42_tb( );

reg a,b;

wire c;

LAB6T2_NANDgate_42 uut (a,b,c);

initial

begin

a=1'b0; b=1'b0;

#5;

a=1'b0; b=1'b1;

#5;

a=1'b1; b=1'b0;

#5;

a=1'b1; b=1'b1;
#5; $stop;

end

endmodule

Output Waveform:
 Design of NOT Gate
Procedure:
 Defines a NOT gate with input a, output z, and utilizes the not primitive.
 Instantiates the NOT gate module and defines a testbench with a register a and wire
 Simulates the NOT gate by toggling input a between 0 and 1 with a 10-unit delay.
 Displays a header "NOT_Gate" at the simulation start.
 Monitors and displays the simulation time, input a, and output z at each simulation step.
 Then observing the display of time, input, and output in the waveform viewer.

Task Results:

Design Code:
`timescale 1ns / 1ps

module LAB6T3_NOTgate42(a,z);

input a;

output z;

not(z,a);

endmodule
Test Bench:
`timescale 1ns / 1ps

module LAB6T3_NOTgate_42_tb( );

reg a;

wire z;

LAB6T3_NOTgate42 uut(a,z);

initial

begin

a=1'b0;

#10 a=1'b1;

#10 a=1'b0;

end

initial

begin

$display ("NOT_Gate");

$monitor ("time=%0d a=%b z=%b", $time, a,z);

end

endmodule
Output Waveform:
 Task No 2

Implementation of OAI and AOI Logic Gates

AOI Logic Diagram

 Task No 3
2:1 MUX using TRANSMISSION GATE
Procedure:
 Implements a 2-to-1 multiplexer using NMOS transistors based on the select line c.
 Instantiates the multiplexer module and defines testbench signals (a, b, c, and y).
 Simulates the multiplexer behavior by changing inputs a and b and select line c at intervals of 10
time units.
 Validates the output y against the expected multiplexer behavior for various input
combinations. Finishes the simulation after testing all input combinations.

Task Results:

Design Code:
`timescale 1ns / 1ps

module LAB6_3_MUX_TG_42(a,b,y,c);

input a,b,c; //c is the select line

output y;

supply0 gnd;

nmos n1(y,a,c);
nmos n2(y,b,~c);

endmodule

Test Bench:
`timescale 1ns / 1ps

module MUX_tb_42( );

reg a, b, c;

wire y;

LAB6_3_MUX_TG_42 mux (a,b,y,c);

initial

begin

a = 0; b = 0; c = 0; #10; // Should output '0' (a selected)

a = 0; b = 0; c = 1; #10; // Still output '0' (a selected)

a = 0; b = 1; c = 0; #10; // Should output '0' (a selected)

a = 0; b = 1; c = 1; #10; // Should output '1' (b selected)

a = 1; b = 0; c = 0; #10; // Should output '1' (a selected)

a = 1; b = 0; c = 1; #10; // Still output '1' (a selected)

a = 1; b = 1; c = 0; #10; // Should output '1' (a selected)

a = 1; b = 1; c = 1; #10; // Should output '1' (b selected)

$finish; // Finish simulation

end
endmodule

Output Waveform:

Conclusion:
In conclusion, the report successfully achieved the design of fundamental CMOS
logic gates, including NOT, NAND, and NOR gates. Furthermore, OAI and AOI logic gates
were successfully implemented to represent complex Boolean functions, with AOI realizing F =
[ab + ac + bd]' and OAI realizing F = (a + b)(a + c)(b + d)'. The design and simulation of a 2:1
MUX using transmission gates were also accomplished. Overall, the report contributes to a
comprehensive understanding of CMOS logic gate design and its application in constructing
complex logic functions and multiplexing circuits.