A computer uses a memory unit with 256K words of 32 bits each.

A binary
instruction code is stored in one word of memory. The instruction has four
parts: an indirect bit, an operation code, a register code part to specify one
of 64 registers, and an address part. a) How many bits are there in the
operation code, the register code part, and the address part? b) Draw the
instruction word format and indicate the number of bits in each part. c) How
many bits are there in the data and address inputs of the memory?

An instruction size is given as 32-bits.

Now, the instruction is divided into four parts :
An indirect bit
Register code part : Since number of registers given as 64(26) so to identify each
register uniquely 6-bits are needed.
Address part : 256K(218) word memory is mentioned so to identify each word
uniquely 18-bits are needed.
Operation code:
Size of Operation code = Complete instruction size - (size of indirect bit + size of
register code + size of address part)
Size of Operation code = 7-bits

Problem 5: Consider a processor that uses a 32-bit virtual memory address. The
memory consists of 32-bit words and is byte addressable. Determine,

a. How many bytes the virtual memory can have?

b. If the page size is 32KB, then how many records should the page table hold?

c. How much data space should physical memory have to hold 32K pages? d. How
many bits of storage will be needed in a record of TLB? Answer:

a. The virtual memory can have 232 = 4GB.

b. Number of records in page table = Number of virtual pages =

4GB/32KB = 128K. c. Physical memory size = 32KB ✕ 32K = 1GB.

d. A TLB record contains 1 valid bit, 1 dirty bit, 1 reference bit, page table index
requiring log2(128K), or 17 bits, and physical page number requiring log2(32K), or 15
bits. Therefore, a TLB record should hold 1 + 1 + 1 + 17 + 15 = 35 bits.

Consider a memory hierarchy with a write back cache. The cache has an access
time of 20nS. Ninety (90%) of all the memory access are found in the cache
itself. The main memory access time is 300nS. The 20% of the cache blocks
 are dirty. The cache block size is 4 bytes. Calculate the average memory
access time.
https://gateoverflow.in/14480/formula-write-back-write-through-access-time-
parallel-serial?show=14502#a14502

https://stackoverflow.com/questions/48277970/write-back-cache-formula-
with-write-allocate-policy

If we consider an hierarchical single level write back cache with write allocate policy,
then the formula for average access time during write operation is given by :-
Twrite = (H)(Tc) + (1-H)(Tc + Tm + (x*Tm)).
Twrite = (Tc * H) + (1-H)(Tc + (x * Tm))

Where,
H= hit ratio of cache.
Tc=access time of cache.
Tm= access time of memory.
x= fraction of cache blocks which are dirty

Classify the various instructions formarts to solve the arithmetic expressions in

different addressing modes

To solve arithmetic expressions in different addressing modes, various instruction

formats are utilized based on the architecture of the processor. Here are some
common instruction formats classified based on the addressing modes they
support:

1. **Immediate Addressing Mode:**

- In this mode, the operand is specified directly in the instruction.

- Example Instruction Format: `OP R1, #value` (where `OP` is the arithmetic
operation, and `value` is the immediate operand)

- Example: `ADD R1, #10` (Add the immediate value 10 to the content of register
R1)

2. **Register Addressing Mode:**

- In this mode, the operand is specified using registers.

- Example Instruction Format: `OP R1, R2` (where `OP` is the arithmetic operation,
and R1 and R2 are registers)
 - Example: `ADD R1, R2` (Add the content of register R2 to the content of register
R1)

3. **Direct Addressing Mode:**

- In this mode, the operand is specified by its memory address.

- Example Instruction Format: `OP R1, memory_address` (where `OP` is the

arithmetic operation, and `memory_address` is the memory address of the operand)

- Example: `ADD R1, 500` (Add the content of memory location 500 to the content
of register R1)

4. **Indexed Addressing Mode:**

- In this mode, the operand is specified by adding an index value to a base address.

- Example Instruction Format: `OP R1, base_register + index` (where `OP` is the
arithmetic operation, `base_register` is a register holding the base address, and
`index` is an offset)

- Example: `ADD R1, R2 + 10` (Add the content of memory location stored at the
address obtained by adding 10 to the content of register R2 to the content of register
R1)

5. **Indirect Addressing Mode:**

- In this mode, the operand is specified indirectly through a memory address stored
in a register or memory location.

- Example Instruction Format: `OP R1, (R2)` (where `OP` is the arithmetic operation,
and `R2` contains the memory address of the operand)

- Example: `ADD R1, (R2)` (Add the content of memory location pointed to by the
content of register R2 to the content of register R1)

These instruction formats allow processors to perform arithmetic operations on

operands stored in different addressing modes, providing flexibility and efficiency in
executing arithmetic expressions.
https://www.cecs.uci.edu/~gajski/eecs31/homeworks/hw8_solutions.html

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document-viewer-cta

Write a program to evaluate the arithmetic statement: X = A - B + C * (D * E - F) * G + H * K.

Using a general register computer with three-address instructions.

b. Using a general register computer with two-address instructions.

c. Using an accumulator type computer with one-address instructions.

d. Using a stack-organized computer with zero-address operation instructions.

Write a program to evaluate the arithmetic statement: X = A -

B + C * (D * E - F) * G + H * K. Using a general register
computer with three-address instructions. b. Using a general
register computer with two-address instructions. c. Using an
accumulator type computer with one-address instructions. d.
Using a stack-organized computer with zero-address
operation instructions.
Write a program to evaluate the arithmetic statement: X = A - B + C * (D * E - F) * G + H * K.

Using a general register computer with three-address instructions.

b. Using a general register computer with two-address instructions.

c. Using an accumulator type computer with one-address instructions.

d. Using a stack-organized computer with zero-address operation instructions.

Three-address instructions: ``` LOAD R1, A LOAD R2, B SUB R1, R1, R2 LOAD R3,
C LOAD R4, D LOAD R5, E MUL R4, R4, R5 LOAD R6, F SUB R4, R4, R6 MUL R3,
R3, R4 ADD R1, R1, R3 LOAD R7, H LOAD R8, K MUL R7, R7, R8 ADD R1, R1, R7
STORE X, R1

Write a program to evaluate the arithmetic statement: Y = (3 + 2) * (5-4)

(i) Using a general register computer with three address instruction.

# Three-address instruction format:

# OP R1, R2, R3 => R1 = R2 OP R3

# Initialize values

LOAD R2, 3 # Load 3 into R2

LOAD R3, 2 # Load 2 into R3

ADD R4, R2, R3 # R4 = R2 + R3 (3 + 2)

LOAD R5, 5 # Load 5 into R5

LOAD R6, 4 # Load 4 into R6

SUB R7, R5, R6 # R7 = R5 - R6 (5 - 4)

MUL R1, R4, R7 # R1 = R4 * R7 ((3 + 2) * (5 - 4))

(ii) Using a general register with two address instruction

# Two-address instruction format:

# OP R1, R2 => R1 = R1 OP R2

# Initialize values

LOAD R1, 3 # Load 3 into R1

ADD R1, 2 # R1 = R1 + 2 (3 + 2)

LOAD R2, 5 # Load 5 into R2

SUB R2, 4 # R2 = R2 - 4 (5 - 4)

MUL R1, R2 # R1 = R1 * R2 ((3 + 2) * (5 - 4))

 Hit: A hit occurs when the data or instruction requested by the CPU is found in
the cache memory. It indicates that the processor can retrieve the required
information without accessing the slower main memory.

Miss: A miss happens when the data or instruction requested by the CPU is not
found in the cache memory. As a result, the processor must fetch the required
information from the slower main memory.

Hit Ratio: The hit ratio is the ratio of cache hits to the total number of memory
access attempts. It is typically expressed as a percentage and gives an
indication of how effectively the cache is being utilized. A higher hit ratio
indicates that a larger portion of memory accesses are being served from the
cache rather than main memory.

Hit Ratio = (Number of Hits) / (Number of Hits + Number of Misses)

Miss Penalty: The miss penalty is the time it takes to retrieve data from the
slower main memory in the event of a cache miss. It includes the time to
access main memory, transfer the data to the cache, and possibly update
cache metadata. Reducing miss penalties is a critical aspect of optimizing
cache performance.

Instruction Cycle: An instruction cycle, also known as a machine cycle, is the

time required to complete the execution of one instruction by the CPU. It
typically consists of multiple sub-cycles, including fetching the instruction,
decoding it, executing it, and potentially writing back the result. Cache hits
and misses can affect the instruction cycle time by influencing memory
access times and overall CPU performance.

Cache coherence refers to the consistency of data stored in multiple caches that are
connected to a shared memory system. In a multiprocessor or multicore system
where each processor or core has its own cache memory, cache coherence ensures
that all caches have a consistent view of memory.

When multiple processors or cores share access to the same memory locations,
cache coherence ensures that any updates made by one processor or core are
visible to all other processors or cores. This prevents data inconsistency issues that
could arise if one processor reads stale data from its cache while another processor
has updated the same data in its cache.

Addressing modes in computer architecture define how operands are specified in

machine instructions. Here are some common addressing modes along with
examples:

Immediate Addressing Mode:

 ● In immediate addressing mode, the operand itself is specified in the
instruction.
● Example: MOV R1, #10 (Move the immediate value 10 into register R1)
● ADD 10 will increment the value stored in the accumulator by 10
Direct Addressing Mode:
● In direct addressing mode, the memory address of the operand is
specified in the instruction.
● Only one reference to memory is required to fetch the operand.
● Example: LOAD R2, 500 (Load the value from memory address 500
into register R2)

Register Addressing Mode:

● In register addressing mode, the operand is specified by a register.
● Example: ADD R3, R1, R2 (Add the values in registers R1 and R2, and
store the result in register R3)
Indirect Addressing Mode:

● In indirect addressing mode, the operand is specified indirectly through

a memory address stored in a register or memory location. Two
references to memory are required to fetch the operand.
● Example: LOAD R4, (R3) (Load the value from the memory address
stored in register R3 into register R4)

Indexed Addressing Mode:

● In indexed addressing mode, the operand is specified by adding an
index value to a base address.
● Example: LOAD R5, (R6 + 10) (Load the value from the memory
address obtained by adding 10 to the value in register R6 into register
R5)
Relative Addressing Mode:
 ● In relative addressing mode, the operand is specified relative to the
current instruction's address.
● Example: JUMP 20 (Jump to the instruction located 20 memory
locations away from the current instruction)
Base-Displacement Addressing Mode:
● In base-displacement addressing mode, the operand is specified by
adding a displacement value to a base address.
● Example: LOAD R7, 100(R6) (Load the value from the memory address
obtained by adding 100 to the value in register R6 into register R7)

These are some of the common addressing modes used in computer architectures.
Each addressing mode offers different ways to specify operands in machine
instructions, providing flexibility and efficiency in programming and execution.

https://www.gatevidyalay.com/addressing-modes/

Cache coherence problems occur when there are discrepancies or inconsistencies in

the data stored across multiple caches. These problems can lead to issues such as:

Read-After-Write (RAW) Hazard: This occurs when one processor writes to a

memory location, but another processor reads from that location before the
write operation is complete. If the reading processor accesses stale data
from its cache, it may produce incorrect results.
Write-After-Read (WAR) Hazard: This happens when one processor reads from a
memory location, and another processor writes to the same location before
the read operation is complete. If the writing processor's cache is not updated
immediately, the data read by the reading processor may become stale.
Write-After-Write (WAW) Hazard: This occurs when multiple processors write to
the same memory location in quick succession. If the caches are not updated
in a coordinated manner, the later write operations may overwrite the data
written by earlier operations, leading to data loss or inconsistency.

CPU registers are small, high-speed storage locations within the CPU (Central
Processing Unit) that hold data temporarily during processing. Each register serves a
specific purpose in the execution of instructions and the management of data within
the CPU. Here are some common CPU registers and their functions:

Name CPU registers and explain their functions

1. **Program Counter (PC):**

- The Program Counter holds the memory address of the next instruction to be fetched and
executed.

- It increments automatically after fetching each instruction, pointing to the next instruction
in memory.
2. **Instruction Register (IR):**

- The Instruction Register temporarily holds the currently fetched instruction.

- It is used to decode the instruction and determine the operation to be performed.

3. **Memory Address Register (MAR):**

- The Memory Address Register holds the memory address of data to be accessed or
modified in main memory.

- It is used during memory read and write operations.

4. **Memory Data Register (MDR):**

- The Memory Data Register holds the data read from or to be written into main memory.

- It acts as an interface between the CPU and main memory, facilitating data transfer.

5. **Accumulator (ACC):**

- The Accumulator is a general-purpose register used for arithmetic and logic operations.

- It stores intermediate results and final results of arithmetic and logic operations.

6. **Index Register (IX) and Index Register (IY):**

- Index Registers are used for indexed addressing operations.

- They hold an offset value that is added to a base address to calculate the effective
memory address for data access.

7. **Status Register (Flag Register):**

- The Status Register holds condition flags that reflect the outcome of arithmetic and logic
operations.

- Common flags include zero flag (Z), carry flag (C), overflow flag (V), and sign flag (S),
among others.
8. **Stack Pointer (SP):**

- The Stack Pointer holds the memory address of the top of the stack in memory.

- It is used for managing the stack data structure, especially during subroutine calls and
returns.

9. **Program Status Word (PSW):**

- The Program Status Word is a special register that contains various control and status
bits.

- It includes bits for interrupt enable/disable, privilege levels, and processor mode.

These are some of the common CPU registers found in most computer architectures. They
play crucial roles in instruction execution, data manipulation, and control flow within the
CPU.
Explain thr following: Main memory, Secondary memory and cache memory

1. **Main Memory (Primary Memory or RAM - Random Access Memory):**

- Main memory refers to the primary storage space directly accessible by the CPU.

- It is volatile, meaning it loses its contents when the power is turned off.

- Main memory is used to store data and instructions that are actively being used by the
CPU during program execution.

- It provides fast access to data but has limited capacity compared to secondary memory.

- Common types of main memory include DRAM (Dynamic RAM) and SRAM (Static RAM).

2. **Secondary Memory (Auxiliary Memory or Storage):**

- Secondary memory refers to storage devices that hold data and programs for long-term
storage.

- Examples include hard disk drives (HDDs), solid-state drives (SSDs), optical disks (CDs,
DVDs), and magnetic tapes.

- Secondary memory is non-volatile, meaning it retains its contents even when the power
is turned off.

- It has larger capacity and slower access times compared to main memory.

- Secondary memory is used for storing data and programs that are not actively being
used by the CPU, such as files and applications.

3. **Cache Memory:**

- Cache memory is a small, high-speed memory located between the CPU and main
memory.

- Its purpose is to store frequently accessed data and instructions to reduce the average
time taken to access memory.

- Cache memory is faster than main memory but smaller in size.

- It exploits the principle of locality, where recently accessed data is likely to be accessed
again in the near future.

- There are different levels of cache (L1, L2, L3) with varying sizes and speeds, with L1
cache being the closest to the CPU and typically the fastest.
 - Cache memory is managed by hardware and often uses cache coherence protocols to
ensure data consistency in multi-core or multi-processor systems.

In summary, main memory is the primary storage space used by the CPU during program
execution, secondary memory provides long-term storage for data and programs, and cache
memory is a small, high-speed memory used to reduce memory access times by storing
frequently accessed data and instructions. Each type of memory serves a specific purpose in
computer systems, balancing speed, capacity, and cost.

With regard to process synchronisation describe what is meant by race conditions?

https://tutorialspoint.com/race-condition-critical-section-and-semaphore

Mutual Exclusion
Mutual exclusion implies that only one process can be inside the critical
section at any time. If any other processes require the critical section,
they must wait until it is free.
Progresss
Progress means that if a process is not using the critical section, then it
should not stop any other process from accessing it. In other words,
any process can enter a critical section if it is free.
Bounded Waitings
Bounded waiting means that each process must have a limited waiting
time. Itt should not wait endlessly to access the critical section.

A semaphore uses two atomic operations, wait and signal for process
synchronization.

The wait operation decrements the value of its argument S, if it is positive. If

S is negative or zero, then no operation is performed.

wait(S){

while (S<=0);

S--;

}
The signal operation increments the value of its argument S.

signal(S){

S++;

Describe two methods that allow mutual exclusion with busy

waiting to be implemented.

Ensure you state any problems with the methods you describe.
https://www.cs.fsu.edu/~hawkes/cda3101lects/index.html
Locality of reference: the tendency of programs to access a relatively small portion of the
available memory at any given time.

temporal locality, states that individual memory locations once referenced are likely to be
referenced again. recently accessed data is likely to be accessed again soon. reuse
previously accessed data, reducing the need to fetch it from main memory. It is also known
as locality in time. Each time same useful data comes into execution.

spatial locality, states that if a location is referenced, then it is likely that nearby locations
will be referenced as well. Data tends to be accessed in contiguous or nearby memory
locations. subsequent memory accesses are likely to be within the same cache line,
resulting in cache hits and faster access times.It is also known as locality in space.Each
time new data comes into execution.

● Temporal Locality - if an item is referenced, then it will tend to be referenced again

soon
○ Instructions in loops are repeatedly referenced.
○ Instructions in recursive or utility functions tend to be repeatedly referenced.
○ Data inside loops (e.g. loop counter variables) are repeatedly referenced.
● Spatial Locality - if an item is referenced, then items whose addresses are close by
will tend to be referenced soon
○ Instructions are accessed sequentially (unless there is a transfer of control).
○ Data elements of an array tend to be accessed sequentially.

https://www.geeksforgeeks.org/difference-between-spatial-locality-and-temporal-locality/

Techniques for reducing the miss rate.

http://ece-research.unm.edu/jimp/611/slides/chap5_3.html

○ increase the associativity (helps exploit temporal locality)

○ increase the block size (helps exploit spatial locality)
○ Expand RAM, increase cache size, can hold more data
○ Larger Cache Size: Increasing the size of the cache allows it to store more
data, reducing the likelihood of cache misses. However, this may come with
increased costs and complexities.
○ Multilevel Caches: Implementing multiple cache levels (e.g., L1, L2, L3
caches) can help reduce miss rates. Smaller, faster caches (e.g., L1 cache)
can store frequently accessed data, while larger caches (e.g., L3 cache) can
hold more data with longer access times.
 ○ Cache Associativity: Associativity refers to the number of cache lines a given
cache location can map to. Higher associativity allows for more flexible
placement of data and reduces conflict misses. However, higher associativity
also increases hardware complexity.
○ Prefetching: Prefetching involves predicting future memory accesses and
bringing data into the cache before it is actually needed. This can reduce
miss rates by ensuring that the required data is already in the cache when
requested.
○ Cache Replacement Policies: Choosing an effective cache replacement policy
(e.g., Least Recently Used - LRU, First-In-First-Out - FIFO) can impact miss
rates. These policies determine which cache line to evict when the cache is
full and a new line needs to be brought in.
○ Compiler Optimizations: Compiler optimizations such as loop unrolling,
software pipelining, and code restructuring can improve spatial and temporal
locality, thereby reducing cache misses.
○ Hardware Prefetching: Some modern processors have hardware support for
prefetching, where the processor automatically predicts and fetches data into
the cache based on access patterns observed.
○ Cache Blocking: Cache blocking (also known as loop blocking or tiling)
involves partitioning data into smaller blocks that fit entirely within the cache.
This can improve cache utilization and reduce miss rates by maximizing
spatial locality.
○
● Techniques for reducing the miss penalty
○ using wrap-around-fill (early restart and critical word first)
○ using secondary caches
○ Cache Hierarchy: Implementing multiple levels of cache (e.g., L1, L2, L3
caches) can help reduce miss penalties. Smaller, faster caches closer
to the CPU can provide lower latency access to frequently used data,
while larger caches further from the CPU can hold more data to reduce
miss rates at the expense of slightly higher latency.
○ Multithreading: Utilizing multithreading techniques such as
simultaneous multithreading (SMT) or multithreaded processors can
help hide memory access latencies. While one thread is waiting for a
cache miss to be serviced, another thread can continue executing,
effectively overlapping computation with memory access.
○ Non-blocking Caches: Non-blocking or asynchronous caches allow
multiple cache misses to be processed concurrently, reducing the
impact of individual misses on overall memory access latency. This
technique is particularly effective in reducing the miss penalty for high-
performance processors.
○ Prefetching: Prefetching involves predicting future memory accesses
and fetching the anticipated data into the cache before it's actually
needed. Hardware prefetching mechanisms or software prefetching
hints can help reduce the latency of cache misses by overlapping
memory access with computation.
○ Write Buffers and Write Combining: Write buffers temporarily store
write operations before they are written back to memory. Write
 combining techniques batch multiple write operations together to
reduce the impact of write-related cache misses. These techniques
help reduce the latency of write operations, thereby mitigating write
miss penalties.
○ Cache Bypassing: Some processors support cache bypassing
mechanisms that allow certain memory accesses to skip the cache
entirely and access main memory directly. This can be beneficial for
latency-sensitive operations where cache misses would incur
significant penalties.
○ Memory-Level Parallelism (MLP): MLP exploits the parallelism inherent
in memory subsystems to overlap the processing of multiple memory
requests. Techniques such as memory banks, interleaving, and out-of-
order memory execution help increase the effective memory bandwidth
and reduce the impact of individual cache misses.
○ Compiler Optimizations: Compiler optimizations such as loop unrolling,
loop fusion, and software prefetching can help improve memory
access patterns and reduce cache miss penalties by enhancing spatial
and temporal locality.
○ Software-Level Techniques: Algorithms and data structures can be
designed or optimized to minimize cache misses and improve memory
access patterns, thus reducing miss penalties. Techniques such as
data layout optimizations and cache-conscious algorithms can be
effective in this regard.
○
Types of Signals

● clock - signal to indicate when an action is to be performed

● control - signal to indicate whether an action is to be performed
○ asserted means logically true
○ deasserted means logically false
● data - signal containing the actual data to be stored or manipulated

MIPS instruction set for two different types of implementations.

● single cycle implementation

● multicycle implementation
memory reference instructions

○ lw
○ sw
● arithmetic-logical instructions
○ add
○ sub
○ and
○ or
○ slt
● control instructions
○ beq
○ j

Implementing an Instruction Set

● A processor consists of
○ datapath - processes the data signals (read, manipulate, store)
○ control - commands the data path by using control signals
● Types of Implementations
○ single cycle
○ multiple cycle
○ pipelined

Advantages of a Multicycle Implementation

● The clock cycle can be much shorter.

● Can require less hardware.
○ Could use a single memory for instructions and data.
○ Can eliminate two adders.
● Allows different instructions to be executed in different number of cycles.

Multicycle Implementation Steps of Execution

● Instruction Fetch Step

● Instruction Decode and Register Fetch Step
● Execution, Memory Address Computation, or Branch Completion Step
● Memory Access or R-Type Instruction Completion Step
● Memory Read Completion Step

● Pipelining is a technique that exploits parallelism among the instructions in a

sequential stream.
● The pipeline is broken into stages, where each stage will take a single clock cycle.
 ● The stages described in the text are:
○ IF - Instruction Fetch
○ ID - Instruction Decode and register file read
○ EX - EXecution or address calculation
○ MEM - data MEMory access
○ WB - Write Back
● Pipelining is similar to the multicycle implementation, but instead of starting the next
instruction after the last step of the current instruction, we overlap the steps.

2022 May

Why Upgrade PC
HDD to SSD: faster data access speeds, reduced boot times, improved overall system
responsiveness, better durability, lower power consumption, and quieter operation.
RAM: smoother multitasking simultaneously without slowing down, quicker application
launch times, and improved overall system responsiveness. Run memory-intensive
applications and games more efficiently
Processor: for faster computing speeds, improved multitasking capabilities, and enhanced
performance in resource-intensive tasks like gaming, video editing, and 3D rendering.
upgrading the Graphics card: for better gaming or graphic design capabilities
improving cooling with better fans or a liquid cooling system.

Reasons why an embedded system may be stored in RAM

Non-volatile Memory: ROM retains its data even when power is turned off, making it
suitable for storing critical firmware or software that needs to be retained across
power cycles.

Security: ROM can be used to store sensitive code or data that needs to be protected
from unauthorized access or modification since it cannot be easily altered once
programmed.

Reliability: ROM is typically more reliable compared to other types of memory like RAM
(Random Access Memory) because it is not susceptible to data corruption or loss
due to power failure or electrical disturbances.

Cost: ROM tends to be cheaper than other non-volatile memory alternatives such as
Flash memory. For mass-produced embedded systems, cost considerations often
drive the choice of memory technology.

Name and describe functions of busses

● Address bus - is undirectional, carries memory addresses of data from the

processor to other components such as primary storage and input/output devices
for read or write operations.
● Data bus - is bidirectional, carries the actual data between the processor ,memory
and I/O devices.
 ● Control bus - carries control signals from the processor to other components, for
coordinating the overall system's operation. It includes signals such as read, write,
clock, interrupt, and reset signals
explain why special registers are needed in additon to primary memory

Speed: Registers are the fastest storage locations in a computer system, residing
directly within the CPU. Accessing data from registers is much quicker than
accessing data from primary memory (RAM). Since the CPU frequently requires
immediate access to operands and intermediate results during instruction execution,
using registers minimizes the latency associated with fetching data from slower
memory.

Operand Storage: Registers store operands for arithmetic and logical operations
performed by the CPU. When executing instructions, the CPU fetches data from
registers, performs computations, and stores results back into registers. Having
registers dedicated to storing operands allows for efficient manipulation of data
without repeatedly accessing primary memory.

Address Calculation: Special-purpose registers such as the instruction pointer (IP) or

program counter (PC) are used to store memory addresses of instructions or data.
These registers are crucial for determining the location of the next instruction to be
executed, facilitating sequential instruction execution and program flow control.

Control Signals: Registers store control signals and status information that govern the
behavior of the CPU and other components. For example, the status register may
contain flags indicating the outcome of arithmetic operations (e.g., zero, carry,
overflow), while control registers may hold configuration settings for system
operation (e.g., mode settings, interrupt enable/disable).

Context Switching: Registers play a vital role in context switching, where the CPU
switches between executing multiple processes or threads. During context switches,
the CPU saves the current state of registers for the current process/thread and
restores the state of registers for the next process/thread. This enables seamless
multitasking and efficient utilization of system resources.

I/O Operations: Registers are used to interface with input/output (I/O) devices. Special-
purpose registers, such as data and control registers, are employed to transfer data
between the CPU and I/O devices, initiate I/O operations, and monitor device status.

CPU Internal Operations: Registers are utilized for various internal operations within the
CPU, including instruction decoding, address generation, and temporary storage of
data and instructions during execution. Having dedicated registers for these
purposes enhances the efficiency and performance of the CPU.

State one item that needs to be stored in ROM and give a reason why ROM is used

BIOS (1) as ROM is non-volatile and the BIOS is needed just after the power supply is
turned on (when RAM would be empty)

State one item that needs to be stored in RAM and give a reason why RAM is used

currently running programs (1) because RAM has quick access speeds (1) / RAM is read &
write (1)
Registers

high-speed temporary storage area built directly into the processor or CPU , stores data,
addresses and instructions for quick processing.help process data efficiently.

is composed of multiple flip-flops

They are used to store operands, intermediate results, memory addresses, control flags, and
other essential data needed for processing instructions.

Role in Instruction Execution:

● Fetch: The CPU fetches instructions from memory into registers (e.g., IR).
● Decode: Instructions are decoded, and operands are fetched from memory into data
registers.
● Execute: The CPU performs arithmetic, logical, or control operations using the data
stored in registers.
● Write-back: Results are stored back into registers or memory.

Types of Registers:

● Data Registers:
● Accumulator (ACC): Often used as a primary data register for arithmetic and logical
operations. The result of most arithmetic operations is stored here.
● General-Purpose Registers (GPRs): Versatile registers that can hold data operands
or memory addresses. They are used for temporary data storage and manipulation.
● Floating-Point Registers (FPRs): Dedicated registers for performing floating-point
arithmetic operations, commonly used in scientific and engineering applications.

● Address Registers: Store memory addresses or pointers used for accessing data in
memory.
● Memory Address Register (MAR): Holds the memory address of data to be read
from or written to in the main memory.
● Memory Data Register (MDR): Holds the data being transferred between the CPU
and memory. It stores the data temporarily during read or write operations.

● Control Registers: Manage control signals, status flags, and mode settings that
govern the behavior of the CPU.
● Program Counter (PC): Holds the memory address of the next instruction to be
fetched and executed.
● Instruction Register (IR): Stores the current instruction fetched from memory,
awaiting decoding and execution.
● Status Register (SR): Contains flags indicating the outcome of arithmetic operations
(e.g., zero, carry, overflow) and system status (e.g., interrupt enable/disable)
● Special-Purpose Registers:
● Instruction Pointer (IP): Similar to the PC, it holds the address of the next instruction
to be executed, commonly used in some CPU architectures.
● Control and Status Register (CSR): Contains control bits and status flags for
configuring CPU operation and monitoring system status.

Key Functions and Operations:

● Operand Storage: Registers hold operands for arithmetic, logical, and data
manipulation operations performed by the CPU.
● Temporary Storage: Intermediate results of calculations are stored in registers during
instruction execution.
● Address Calculation: Registers hold memory addresses or pointers for accessing
data in main memory or other storage devices.
● Control Signals: Control registers store flags and control signals that influence the
behavior of the CPU, such as the carry flag, zero flag, and interrupt enable/disable
flags.
● Instruction Execution: Registers facilitate the decoding, fetching, and execution of
instructions by holding the current instruction (IR) and the address of the next
instruction to be executed (PC).
● Context Switching: Registers are used to save and restore the state of the CPU
during context switches between different processes or threads.
● Input/Output Operations: Registers interface with I/O devices, transferring data
between the CPU and peripheral devices.