Pipeline
Pipeline
Assume that each instruction requires different stage delays (in terms of number
of clock cycles) as shown in the table:
IF ID EX WB
Instruction 1 1 3 2 1
Instruction 2 2 2 3 1
Instruction 3 1 1 1 1
Instruction 4 2 1 1 2
a. How many clock cycles will be required to complete these 4 instructions in the given pipelining system?
b. Calculate the speedup.
1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 19 20 21 22 2 24 25 26 27 28 29 30 31 32
0 1 2 3 4 5 6 7 8 3
I I I d d d E d d W
1 F D * * * X * * B
I I d d I d d E d d d* W d*
2 F * * D * * X * * B
I I d ID d* EX d* WB d*
3 F *
I IF d* d* ID d* EX d* W d* d*
4 B
I1 IF ID ID ID E EX W
X B
I2 IF IF ID ID EX EX EX W
B
I3 IF ID EX WB
I4 IF IF ID EX W
B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
I1 IF IF ID ID ID ID EX EX EX WB WB
I2 IF IF IF ID ID ID EX EX EX EX WB WB
I3 IF IF ID ID EX EX WB WB
I4 IF IF IF ID ID EX EX WB WB WB
e. Calculate the speedup.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
I1 IF ID EX WB
I2 IF ID EX WB
I3 IF ID EX WB
I4 IF ID EX WB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
I1 IF ID EX WB
I2 IF ID EX WB
I3 IF ID EX WB
I4 IF ID EX WB