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Computer Organization-Input & Output
Organization 1|Page

MODULE-II

INPUT OUTPUT ORGANIZATION

Objectives
1. Accessing I/O Devices
2. Interrupts
2.1 Interrupt Hardware
2.2 Enabling & Disabling Interrupts
2.3 Handling Multiple Devices
2.4 Controlling Device Requests
2.5 Exceptions
3. Direct Memory Access
4. Buses
1. Accessing I/O Devices:
A simple arrangement to connect I/O devices to a computer is to use a single bus arrangement.

1) The bus enables all the devices connected to it to exchange information.

2) Bus consists of three sets of lines used to carry, data, and control lines.
3) Each I/O device is assigned a unique set of addresses.
4) When the processor places a particular address on the address line, the device that
recognizes this address responds to the commands issued on the control lines.
5) The processor requests either a read or a write operation, and the requested data are
transferred over the data lines.

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1.1 I/O interface for an input device:

The hardware arrangement of connecting Input device to the system bus is called as “Device
Interface Or I/O Interface”.
I/O interface has three modules:
i)Address Decoder
ii) Control circuits
iii) Data & Status registers

i) Address Decoder:
 Address decoder is connected to the address lines of the bus as shown in the fig:
 The function of address decoder is: Address decoder enables the device to recognize its
address when this address appears on the address bus.
ii) Data and Status registers:
• Data register holds the data being transferred to or from the processor.
• Status register holds information necessary for the operation of the I/O device.
• Data and status registers are connected to the data lines, and have unique addresses.
iii) Control Circuits:
 The control bus of system bus is connected to control circuit as shown in the fig.
 It controls the read write operations with respect to I/O device.
 I/O interface circuit coordinates I/O transfers.

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1.3 i)Memory-mapped I/O:

 In this technique both memory and I/O devices can share the common memory to store
the instruction as well as the operands.
 Memory related instructions are used for data transfer between I/O and processor.
 In case of memory mapped I/O input operation can be implemented as,
MOVE DATAIN, Ro
 Similarly output can be implemented as,
MOVE Ro,DATAOUT
ii) I/O mapped I/O:
 In this technique address spaces are different for I/O devices and memory.
Processor has special IN and OUT instructions to perform I/O transfers.
IN DATAIN, R0
 This instruction reads the data from the DATAIN and stores it into the register R0; DATAIN
is the address of the buffer associated with the input device..
OUT R0, DATAOUT
 This instruction sends the contents of the register R0 to location DATAOUT; DATAOUT is
the address of the buffer associated with the output device.

Memory Mapped I/O I/O Mapped I/O

1 .In this technique both I/O devices 1. In this technique address spaces are
and memory share the same address different for I/O devices and memory.
space.

2. Any machine instruction that can 2. In this technique processor has

access memory can be used to transfer special IN and Out instructions to
data to or from an I/O device. perform I/O transfers.

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iii)Program-controlled I/O:
 In program-controlled I/O scheme the processor repeatedly checks a status flag of the I/O
devices to achieve the required synchronization between the processor and an input or
output device.
Disadvantage:
 Processor checks the status flag of I/O device, if I/O device not ready for data transfer,
processor enters to wait loop.
 During this period, the processor is not performing any useful computation.
 There are many situations where other tasks can be performed while waiting for an I/O
device to become ready.

2. Interrupts:
Definition: Interrupt is an event which suspends the execution of one program and begins the
execution of another program.
Interrupt signals and its function:
i) INT(Interrupt):
Interrupt is a hardware signal sent by I/O device when it is become ready to alert the processor.
ii) INTR(Interrupt Request):
At least one of the control lines called interrupt request line is usually dedicated for this purpose.
iii) INTA(Interrupt Acknowledgement):
Interrupt-Acknowledge signal is a special signal issued by the processor to the device that its
request has been recognized so that it may remove its interrupt request signal.
iv) ISR( interrupt-service routine):
The routine executed in response to an interrupt request is called the interrupt-service
routine(interrupt program).

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Working procedure of Interrupts

Assume that an interrupt request arrives during execution of instruction i.

1) The processor first completes execution of instruction i.

2) Processor is executing the instruction located at address i when an interrupt occurs.
3) Interrupt program executed in response to an interrupt request is called the interrupt-
service routine.
4) When an interrupt occurs, control must be transferred to the interrupt service routine.
5) But before transferring control, the current contents of the PC (i+1), must be saved in a
known location.
6) This will enable the return-from-interrupt instruction to resume execution at i+1.
7) Return address, or the contents of the PC are usually stored on the processor stack.

8) Treatment of an interrupt-service routine is very similar to that of a subroutine.

9) the differences between subroutine and interrupts:
a. A subroutine performs a task that is required by the calling program.

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b. Interrupt-service routine may not have anything in common with the program it
interrupts.
c. Interrupt-service routine and the program that it interrupts may belong to different
users.
d. As a result, before branching to the interrupt-service routine, not only the PC, but
other information such as condition code flags, and processor registers used by both
the interrupted program and the interrupt service routine must be stored.
e. This will enable the interrupted program to resume execution upon return from
interrupt service routine.
10) Saving and restoring information can be done automatically by the processor or explicitly
by program instructions.
11) Saving and restoring registers involves memory transfers:
a. Increases the total execution time.
b. Increases the delay between the time an interrupt request is received, and the
start of execution of the interrupt-service routine.
This delay is called interrupt latency.
12) In order to reduce the interrupt latency, most processors save only the minimal amount of
information:
a. This minimal amount of information includes Program Counter and processor
status registers.
13) Any additional information that must be saved , must be saved explicitly by the program
instructions at the beginning of the interrupt service routine.
14) When a processor receives an interrupt-request, it must branch to the interrupt service
routine.
15) It must also inform the device that it has recognized the interrupt request.
This can be accomplished in two ways:
i) Some processors have an explicit interrupt-acknowledge control signal for this purpose.
ii) In other cases, the data transfer that takes place between the device and the processor can
be used to inform the device.

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2.1 Interrupt hardware:-

1) The external device (I/O device) request the processor by activating one bus line and this
bus line is called as interrupt request line.
2) The one end of this interrupt request line is connected to input power supply by means of
pull up register is as shown in the fig.

3) Another end of interrupt request line is connected to INTR (Interrupt request) signal of
processor as shown in the figure above.
4) The I/O device is connected to interrupt request line by means of switch as shown in the
fig.
5) INTR is a INTerrupt Request signal which is sent by I/O device to request interrupt, INTR
is active-low signal.
6) Depends on the interrupt switch on and off we can consider two stares:
i) In-Active State
ii) Active State
i)In-Active State:

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 When all the switches are open the voltage drop on interrupt request line is equal to the
VDD.
Therefore INTR=0
 This state is called as in-active state of the interrupt request line.

ii)Active State:
 The I/O device interrupts the processor by closing its switch.
7) When switch is closed the voltage drop on the interrupt request line is found to be zero.
Therefore INTR=1
8) The signal on the interrupt request line is logical OR of requests from the several I/O
devices.
Therefore, INTR=INTR1 + INTR2 + ……….+ INTRn
2.2. Enabling and Disabling Interrupts:-
Disadvantages of interrupt:
1) Interrupt-requests interrupt the execution of a program, and may alter the intended
sequence of events:
2) Sometimes such alterations may be undesirable, and must not be allowed.
Example: The processor may not want to be interrupted by the same device (either input or
output device) while executing its interrupt-service routine.
To overcome above disadvantages, Processors generally provide the ability to enable and disable
such interruptions as desired called Interrupt-Enable and Interrupt-Disable
There are 3 techniques to enable and disable the interrupts.
Method 1:
To avoid interruption by the same device during the execution of an interrupt service routine:
 First instruction of an interrupt service routine can be Interrupt-disable.
 Last instruction of an interrupt service routine can be Interrupt-enable.
Method 2: suitable for a simple processor with only one interrupt-request line:
1) The processor automatically disables interrupts before starting the execution of the
interrupt service routine.

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2) Uses the PS (Processor status) register,(1 bit in the PS register called interrupt-enable
indicates whether interrupts enabled),when this bit is 1 interrupt is accepted.
3) After saving the contents of the PC and the processor status register (PS) on the stack, the
processor clears the Interrupt-enable bit in its PS register, thus disabling further interrupts.
4) When return-from-interrupt is executed, the contents of the PS are restored from the stack,
setting the interrupt-enable bit to 1.
Method 3: Uses special INTR line:
1. The device raises an interrupt request.
2. The processor interrupts the program currently being executed.
3. Interrupts are disabled by changing the control bits in the Processor Status register
4. The device is informed that its request has been recognized, and in response, it deactivates the
interrupt-request signal.
5. The action requested by the interrupt is performed by the interrupt-service routine.
6. Interrupts are enabled and execution of the interrupted program is resumed.
2.3 HANDLING MULTIPLE DEVICES:-
1) The information needed to determine whether an input or output device is requesting an
interrupt is available in its status register.

2) When a device raises an interrupt request, it sets IRQ bit to 1, which is in its status register.
Example: Bits KIRQ and DIRQ are the interrupt request bits for the keyboard and the
display, respectively.
3) The simplest way to identify the interrupting device is to have the interrupt service routine
poll all the I/O devices connected to the bus.
4) The first device encountered with its IRQ bit set is the device that should be serviced.
5) An appropriate subroutine is called to provide the requested service.
2.3.1 Polling scheme:
1) Processor uses polling mechanism to poll the status registers of I/O devices to determine
which devices are polled.

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2) The first device with status bit is set to 1 is the device whose interrupt request is accepted.
3) The polling scheme is easy to implement.
4) Its main disadvantage in polling scheme is the time spent interrogating the IRQ bits of all
the devices that may not be requesting any service.

An alternative approach is to use vectored interrupts.

2.3.2 Vectored Interrupt:
1) To reduce the time involved in the polling process, using vector interrupts.
2) “A device requesting an interrupt indentifies itself by sending a special code to the processor
over the bus”.
3) This enables the processor to identify individual devices even if they share a single interrupt
request line.
4) Interrupt vector code:
a) The code supplied by the device may represent the starting address of the interrupt
service routine for that device.
b) The code length is typically in the range of 4 to 8 bits.
c) The location pointed to by the interrupting device is used to store the starting address
of the interrupt service routine.
d) The processor reads this address called as interrupt vector, and loads it into PC.
e) The interrupt vector may also include a new value for the processor status register.
f) In most computers, I/O Devices send the interrupt vector code over the data bus using
the bus control signals to ensure that the devices do not interface with each other.
g) When a device sends an interrupt request, the processor may not be ready to receive
the interrupt vector code immediately.
h) Then the processor can immediately transfer its service to interrupt service routine.
Such interrupts are known as vectored interrupts.
5) The remainder of the address is supplied by the processor based on the area in its memory where
the addresses for interrupt service routines are located.

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2.3.3 Interrupt Nesting: -

1) Processor accepts the interrupt request from high-priority device while it is servicing
another request from low-priority device.
2) Hence, branching from one interrupt –service to another interrupt-service is called
interrupt-nesting.
Priority level:
3) An interrupt request from a high-priority device should be accepted while the processor is
servicing another request from a lower-priority device.
4) To implement this scheme, assign a priority level to the processor that can be changed
under program control.
5) The priority level of the processor is the priority of the program that is currently being
executed.
6) The processor accepts interrupts only from devices that have priorities higher than its own.
7) The processor’s priority is usually encoded in a few bits of the processor status word.
Privileged instructions:
8) Processor’s priority can be changed by program instructions that write into the PS, These
are privileged instructions, which can be executed only while the processor is running in
the supervisor mode.
9) Processor works in different modes mainly supervisor mode and user mode
10) supervisor mode: The processor is in the supervisor mode only when executing operating
system routines
11) User mode: The processor is in the user mode only when executes user(including I/O
Interrupt programs) application program.

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12) The processor is in the supervisor mode only when executing operating system routines.
13) It switches from supervisor mode to the user mode before beginning to execute application
programs.
14) Thus, a user program cannot accidentally, or intentionally, change the priority of the
processor and disrupt the system’s operation.
15) An attempt to execute a privileged instruction while in the user mode leads to a special
type of interrupt called a privileged instruction.
b)Multiple-Priority Scheme:
1) A multiple-priority scheme can be implemented easily by using separate interrupt-request
and interrupt-acknowledge lines for each device, as shown in figure.

INTR 1 I N TR p

Processor Device 1 Device 2 Device p

INTA1 INTAp

Priority arbitration
Fig: Implementation of interrupt priority using individual interrupt-request and acknowledge lines.

2) Each device has a separate interrupt-request and interrupt-acknowledge line.

3) Each interrupt-request line is assigned a different priority level.
4) Interrupt requests received over these lines are sent to a priority arbitration circuit in the
processor.
5) If the interrupt request has a higher priority level than the priority of the processor, then
the request is accepted.
2.3.4 Simultaneous Requests:-
Consider the problem of simultaneous arrivals of interrupt requests from two or more devices.
Daisy chain scheme:
Devices are connected to form a daisy chain as shown in the below fig.

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Fig: Daisy chain scheme

1) The processor simply accepts the requests having the highest priority.
2) Devices share the interrupt-request line using common (single) bus line.
3) Interrupt-acknowledge line is connected to form a daisy chain fashion.
4) When devices raise an interrupt request, the interrupt-request line is activated.
5) The processor in response activates interrupt-acknowledge.
6) Received by device 1, if device 1 does not need service, it passes the signal to device 2.
7) Device that is electrically closest to the processor has the highest priority.
Arrangement of priority groups using daisy-chain fashion:
1) When I/O devices were organized into a priority structure, each device had its own
Interrupt-request and interrupt-acknowledge line.
2) When I/O devices were organized in a daisy chain fashion, the devices shared an interrupt-
request line, and the interrupt-acknowledge propagated through the devices.
3) A combination of priority structure and daisy chain scheme can also used.
I NT R 1

Device Device
INTA1
Processor
IN T R p

Device Device
INTA p
Priority arbitration
circuit

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Fig: Arrangement of priority groups

4) Devices are organized into groups.
5) Each group is assigned a different priority level.
6) All the devices within a single group share an interrupt-request line, and are connected to
form a daisy chain
2.3.5 Controlling Device Requests: -
1) It is important to ensure that interrupt requests are generated only by those I/O devices
which is used by a given program.
2) Idle devices must not be allowed to generate interrupt requests, even though they may be
ready to participate in I/O transfer operations.
3) The control needed is usually provided in the form of an interrupt-enable bit in the device’s
interface circuit.
4) The keyboard interrupt-enable, KEN, and display interrupt-enable, DEN, flags in register
CONTROL perform this function.
5) If either of these flags is set, the interface circuit generates an interrupt request whenever
the corresponding status flag in register STATUS is set.
6) At the same time, the interface circuit sets bit KIRQ or DIRQ to indicate that the keyboard
or display unit, respectively, is requesting an interrupt.
7) If an interrupt-enable bit in PS is equal to 0, the interface circuit will not generate an
interrupt request, regardless of the state of the status flag.
Summary:
There are two independent mechanisms for controlling interrupt requests:
1) At the device end, an interrupt-enable bit in a control register determines whether the
device is allowed to generate an interrupt request.
2) At the processor end, either an interrupt enable bit in the PS register or a priority structure
determines whether a given interrupt request will be accepted.
2.3.5 Exceptions:-
Interrupt: An interrupt is an event that causes the execution of one program to be suspended and
the execution of another program to begin.

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 The interrupt mechanism is used in a number of other situations.

 The term exception is used to refer to any event that causes an interruption.
 Hence, I/O interrupts are one example of an exception.

i)Recovery from Errors:-

 Computers use a variety of techniques to ensure that all hardware components are operating
properly.
Example:
 Many computers include an error-checking code in the main memory, which
allows detection of errors in the stored data.
 If errors occur, the control hardware detects it and informs the processor by
raising an interrupt.
 The processor may also interrupt a program if it detects an error or an unusual condition
while executing the instructions of this program.
Example:
 The OP-code field of an instruction may not correspond to any legal instruction,
or an arithmetic instruction may attempt a division by zero.
 When exception processing is initiated as a result of such errors, the processor proceeds in
exactly the same manner as in the case of an I/O interrupt request.
 It suspends the program being executed and starts an Exception-Service Routine (ESR).
 This routine takes appropriate action to recover from the error, if possible, or to inform the
user about it.
 Recall that in the case of an I/O interrupt, the processor completes execution of the
instruction in progress before accepting the interrupt.
 However, when an interrupt is caused by an error, execution of the interrupted instruction
cannot usually be completed, and the processor begins exception processing immediately.
ii)Debugging:-

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Another important type of exception is used as an aid in debugging programs.

 System software usually includes a program called a debugger, which helps the
programmer find errors in a program.
 The debugger uses exceptions to provide two important facilities called trace and
breakpoints.

Trace:
1) When a processor is operating in the trace mode, an exception occurs after
execution of every instruction, using the debugging program as the exception-
service routine.
2) The debugging program enables the user to examine the contents of registers,
memory locations, and so on.
3) On return from the debugging program, the next instruction in the program
being debugged is executed, and then the debugging program is activated again.
4) The trace exception is disabled during the execution of the debugging program.
Breakpoint:
1) Breakpoint provides a similar facility, except that the program being debugged is
interrupted only at specific points selected by the user.
2) An instruction called Trap or Software-interrupt is usually provided for this
purpose.
3) Execution of this instruction results in exactly the same actions as when a hardware
interrupt request is received.
Working of debugging program:
1) While debugging a program, the user may wish to interrupt program execution after
instruction i.
2) The debugging routine saves instruction i+1 and replaces it with a software interrupt
instruction.
3) When the program is executed and reaches that point, it is interrupted and the debugging
routine is activated.

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4) This gives the user a chance to examine memory and register contents.
5) When the user is ready to continue executing the program being debugged, the debugging
routine restores the saved instruction that was a location i+1 and executes a Return-from-
interrupt instruction.

iii)Privilege Exception:-
To protect the operating system of a computer from being corrupted by user programs, certain
instructions can be executed only while the processor is in supervisor mode. These are called
privileged instructions.
Example:
 when the processor is running in the user mode, it will not execute an instruction
that changes the priority level of the processor or that enables a user program to
access areas in the computer memory that have been allocated to other users.
 An attempt to execute such an instruction will produce privilege exceptions,
causing the processor to switch to the supervisor mode and begin executing an
appropriate routine in the operating system.
Direct Memory Access
Definition for DMA: “A special control unit used to provided to transfer a block of data with high
speed directly between an I/O device and the main memory, without continuous intervention by
the processor, this approach is called direct memory acces(DMA)”

Ex: Internal memory (RAM) data transfers and disk transfers uses DMA.
3.1)Direct Memory Access (DMA):
1) Control unit which performs DMA transfers is a part of the I/O device’s interface circuit.
This control unit is called as a DMA controller.
2) DMA controller performs functions that would be normally carried out by the processor:
 For each word, it provides the memory address and all the control signals.
 To transfer a block of data, it increments the memory addresses and keeps track of the
number of transfers.

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3) DMA controller can transfer a block of data from an external device to the processor,
without any intervention from the processor.
4) However, the operation of the DMA controller must be under the control of any program
executed by the processor. That is, the processor must initiate the DMA transfer.

5) To initiate the DMA transfer, the processor informs the DMA controller of:
 Starting address
 Number of words in the block.
 Direction of transfer (I/O device to the memory, or memory to the I/O device).
6) After initiating the DMA transfer, the processor suspends the program that initiated the
transfer, and continues with the execution of some other program.
The program whose execution is suspended is said to be in the blocked state.
7) On receiving this information, the DMA controller proceeds to perform the requested
operation.
8) Once the DMA controller completes the DMA transfer, it informs the processor by raising
an interrupt signal.
9) While a DMA transfer is taking place, the program that requested the transfer cannot
continue, and the processor can be used to execute another program.
10) After the DMA transfer is completed, the processor can return to the program that requested
the transfer.
DMA with OS:
11) I/O operations are always performed by the operating system of the computer in response
to a request from an application program.
12) The OS is also responsible for suspending the execution of one program and starting
another.
13) Thus, for an I/O operation involving DMA, the OS puts the program that requested the
1transfer in the Blocked state, initiates the DMA operation, and starts the execution of
another program.

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14) When the transfer is completed, the DMA controller informs the processor by sending an
interrupt request
15) In response, the OS puts the suspended program in the Runnable state so that it can be
selected by the scheduler to continue execution.

i) Registers of DMA:
1) Figure shows an example of the DMA controller three registers that are accessed by the
processor to initiate transfer operations.
2) Two registers are used for storing the Starting address and the word count.

3) The third register contains status and control flags.

a)Read/Write flag register:

The R/W bit determines the direction of the transfer as explained below:
Case 1: Read operatio
When R/W bit=1 by a program instruction,
The controller performs a Read operation,
That is, it transfers data from the memory to the I/O device.
Case 2: Write operation
When R/W bit=0 by a program instruction,
The controller performs a Write operation,

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That is, it transfers data from the I/O device to the memory.
b) DONE flag register:
 This information is informed to CPU by means of DONE bit.
 When done flag=1 then DMA controller is ready to receive another command
 When done flag=0 then DMA controller is not ready to receive another command

c) Interrupt enable(IE) flag register:

 The DMA controller enables the interrupt enable bit after the completion of DMA
operation
 Bit 30 is the Interrupt-enable flag,
when IE=1: The controller to raise an interrupt
when IE=0: The controller do not raise an interrupt
d). Interrupt request (IRQ) flag register:
 The DMA controller requests the CPU to transfer new block of data from source to
destination by activating this bit.
 Bit 30 is the the Interrupt request,
Controller sets the IRQ bit= 1 when it has requested an interrupt.
Controller sets the IRQ bit= 0 when it has not requested an interrupt.
ii)Use of DMA controllers in a computer system:
1) An example of a computer system is given in below figure, showing how DMA controllers
may be used.

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Main
Processor memory
System bus

Disk/DMA DMA Printer Keyboard

controller controller

Disk Disk Network

Interface

2) A DMA controller connects a high-speed network to the computer bus.

3) The disk controller, which controls two disks, also has DMA capability and provides two
DMA channels.
4) It can perform two independent DMA operations, as if each disk had its own DMA
controller.
5) The registers needed to store the memory address, the word count, and so on are
duplicated, so that one set can be used with each device.
Working of DMA Controller:
6) To start a DMA transfer of a block of data from the main memory to one of the disks, a
program writes the address and word count information into the registers of the
corresponding channel of the disk controller.
7) The DMA controller proceeds independently to implement the specified operation.
8) When the DMA transfer is completed,
This fact is recorded in the status and control register of the DMA channel by setting the
Done bit.
9) At the same time, if the IE bit is set that is IE=1, the controller sends an interrupt request
to the processor and sets the IRQ bit that is IRQ=1.
10) The status register can also be used to record other information, such as whether the transfer
took place correctly or errors occurred.
iii)DMA data transmission modes:
DMA transmits data using 2 modes:

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1) cycle stealing
2) Burst mode
1) Cycle stealing:
1) Memory accesses by the processor and the DMA controller are interwoven.
2) Requests by DMA devices for using the bus are always given higher priority than processor
requests.
3) Among different DMA devices, top priority is given to high-speed peripherals such as a
disk, a high-speed network interface, or a graphics display device.
4) Since the processor originates most memory access cycles, the DMA controller can be said
to “steal” memory cycles from the processor.
5) Hence, the interweaving technique is usually called cycle stealing.
2) Burst mode:
1) In this mode,the DMA controller may be given exclusive access to the main memory to
transfer a block of data without interruption. This is known as block or burst mode.
2) Most DMA controllers incorporate a data storage buffer. In the case of the network
interface
Example: the DMA controller reads a block of data from the main memory and stores it
into its input buffer. This transfer takes place using burst mode at a speed appropriate to
the memory and the computer bus.
3) Then, the data in the buffer are transmitted over the network at the speed of the network.
Conflicts in DMA:
 A conflict may arise if both the processor and a DMA controller or two DMA controllers
try to use the bus at the same time to access the main memory.
 To resolve these conflicts, an arbitration procedure is implemented on the bus to coordinate
the activities of all devices requesting memory transfers.
3.2 Bus Arbitration:-
 Processor and DMA controllers both need to initiate data transfers on the bus and access
main memory.
 The device that is allowed to initiate transfers on the bus at any given time is called the bus
master.

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Computer Organization-Input & Output
Organization 23 | P a g e

 When the current bus master relinquishes its status as the bus master, another device can
acquire this status.
Bus Arbitration: The process by which the next device to become the bus master is
selected and bus mastership is transferred to it is called bus arbitration.
Purpose of Bus Arbitration:
 Bus arbitration is required to resolve the conflict that arises when both the Processor and a
DMA controller or two DMA controllers try to use the bus at same time to access main
memory.
 Bus arbitration is required coordinate the activities of all devices requesting memory transfers.
There are two approaches to bus arbitration:
i) Centralized arbitration: a single bus arbiter performs the required arbitration.
ii) Distributed arbitration: all devices participate in the selection of the next bus master.
i)Centralized Arbitration:-
1) In centralized arbitration, the bus master may be the processor or a separate unit connected to
the bus.
2) Figure shows a basic arrangement in which processor contains the bus arbitration circuit.

BBSY
BR
Processor
DMA DMA
controller controller
BG1 1 BG2 2
3) In this case, the processor is normally the bus master unless it grants bus mastership to one of
the DMA controllers.
4) A DMA controller indicates that it needs to become the bus master by activating the BUS
request line, BR.
5) This signal is connected to all DMA controllers using a DAISY-CHAIN arrangement.
6) When the bus request line is activated, the processor activates the bus grant signal, BG1
indicating to the DMA controllers that they may use the bus when it becomes free.
7) This signal is connected to all DMA controllers using a DAISY-CHAIN arrangement.

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Organization 24 | P a g e

8) Thus, if DMA controller 1 is requesting the bus, it blocks the propagation of the grant signal
to the other devices; otherwise, it passes the grant signal to next device.
9) The current bus master indicates to all devices that it is using bus by activating another line
called BUS-BUSY (BBSY).
10) Hence, after receiving the BUS –grant signal, a DMA controller waits for BUS-BUSY to
become inactive, then it gets the BUS Mastership. at this time it activates BUS-BUSY.
11) The timing diagram in the figure shows the sequence of events for the devices.

DMA controller 2
Time
asserts the BR signal. Processor asserts
BR
the BG1 signal
BG1
BG1 signal propagates
BG2 to DMA#2.
BBSY
Bus
master Processor DMA controller 2 Processor

Processor relinquishes control

of the bus by setting BBSY to 1.

Distributed Arbitration:
1) In distributed arbitration all devices participate in the selection of next bus master.

2) A simple method for distributed arbitration is shown in the figure 4.22.

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Computer Organization-Input & Output
Organization 25 | P a g e

3) Each device on the bus is assigned a 4-bit identification number.

4) When one or more devices request the bus, they assert the start arbitration signal and place
their 4-bit identification numbers on four lines, ARB0 through ARb3.

5) A winner is selected as a result of the interaction among the signals transmitted over these lines
by all contenders.

6) If one device puts 1 on the bus and another device puts 0 on the same bus line, the bus line
status will be 0.
Example:
1) Consider that two devices A and B having ID numbers 5 and 6 respectively are requesting the
use of bus.
2) Device A transmits the pattern 0101, and device B transmits the pattern 0110.
3) The code seen by both devices is 0111.
4) If it detects a difference at any bit position, it disables its drivers at that bit position and for all
lower-order bits. It does so by placing 0 at the input of these drivers.
5) In our example device A detects the difference on the line ARB1; hence it disables its drivers
on lines ARB1 and ARB0. This causes the pattern on the arbitration lines to change to 0110,
which means that device B has won the contention.

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1

MODULE-II
I/O Operations(part2)
4.1 Interface Circuits

An I/O interface consists of the circuitry required to connect an I/O device to a computer bus.
On one side of the interface, we have bus signals. On the other side, we have a data path with its
associated controls to transfer data between the interface and the I/O device – port. We have two
types:

Serial port and

Parallel port

A parallel port transfers data in the form of a number of bits (8 or 16) simultaneously to or
from the device. A serial port transmits and receives data one bit at a time. Communication with
the bus is the same for both formats. The conversion from the parallel to the serial format, and
vice versa, takes place inside the interface circuit. In parallel port, the connection between the
device and the computer uses a multiple-pin connector and a cable with as many wires. This
arrangement is suitable for devices that are physically close to the computer. In serial port, it is
much more convenient and cost-effective where longer cables are needed.

Typically, the functions of an I/O interface are:

• Provides a storage buffer for at least one word of data

• Contains status flags that can be accessed by the processor to determine whether the
buffer is full or empty
• Contains address-decoding circuitry to determine when it is being addressed by the
processor
• Generates the appropriate timing signals required by the bus control scheme
• Performs any format conversion that may be necessary to transfer data between the bus
and the I/O device, such as parallel-serial conversion in the case of a serial port

i)Parallel Port

The hardware components needed for connecting a keyboard to a processor Consider the
circuit of input interface which encompasses (as shown in below figure):
– Status flag, SIN
– R/~W
– Master-ready
– Address decoder

A detailed figure showing the input interface circuit is presented in figure 4.29. Now, consider
the circuit for the status flag (figure 4.30). An edge-triggered D flip-flop is used along with read-
data and master-ready signals.
2

Keyboard to processor connection

Printer to processor connection

The hardware components needed for connecting a printer to a processor are: the circuit
of output interface, and
– Slave-ready
– R/~W
– Master-ready
– Address decoder
– Handshake control

The input and output interfaces can be combined into a single interface. The general purpose
parallel interface circuit that can be configured in a variety of ways. For increased flexibility, the
circuit makes it possible for some lines to serve as inputs and some lines to serve as outputs,
under program control.

ii)Serial port

A serial interface circuit involves – Chip and register select, Status and control, Output
shift register, DATAOUT, DATAIN, Input shift register and Serial input/output – as shown in
figure 4.37.
3

4.2 Standard I/O interfaces

Consider a computer system using different interface standards. Let us look in to Processor bus
and Peripheral Component Interconnect (PCI) bus. These two buses are interconnected by a
circuit called bridge. It is a bridge between processor bus and PCI bus. An example of a
computer system using different interface standards is shown in figure 4.38. The three major
standard I/O interfaces discussed here are:

– PCI (Peripheral Component Interconnect)

– SCSI (Small Computer System Interface)
– USB (Universal Serial Bus)

4.2.1 PCI (Peripheral Component Interconnect):

The topics discussed under PCI are: Data Transfer, Use of a PCI bus in a computer system, A
read operation on the PCI bus, Device configuration and Other electrical characteristics. Use of a
PCI bus in a computer system is shown in figure 4.39 as a representation.

Host, main memory and PCI bridge are connected to disk, printer and Ethernet interface
through PCI bus. At any given time, one device is the bus master. It has the right to initiate data
transfers by issuing read and write commands. A master is called an initiator in PCI terminology.
This is either processor or DMA controller. The addressed device that responds to read and write
commands is called a target. A complete transfer operation on the bus, involving an address and
a burst of data, is called a transaction. Device configuration is also discussed.

4.2.2 SCSI Bus:

It is a standard bus defined by the American National Standards Institute (ANSI). A

controller connected to a SCSI bus is an initiator or a target. The processor sends a command to
the SCSI controller, which causes the following sequence of events to take place:

• The SCSI controller contends for control of the bus (initiator).

• When the initiator wins the arbitration process, it selects the target controller and hands
over control of the bus to it.
• The target starts an output operation. The initiator sends a command specifying the
required read operation.
The target sends a message to the initiator indicating that it will temporarily suspends the
connection between them. Then it releases the bus.

• The target controller sends a command to the disk drive to move the read head to the first
sector involved in the requested read operation.
• The target transfers the contents of the data buffer to the initiator and then suspends the
connection again.
4

• The target controller sends a command to the disk drive to perform another seek
operation.
• As the initiator controller receives the data, it stores them into the main memory using the
DMA approach.
• The SCSI controller sends an interrupt to the processor to inform it that the requested
operation has been completed.
The bus signals, arbitration, selection, information transfer and reselection are the topics
discussed in addition to the above.

4.2.3Universal Serial Bus (USB):

The USB has been designed to meet several key objectives such as:
• Provide a simple, low-cost and easy to use interconnection system that overcomes the
difficulties due to the limited number of I/O ports available on a computer

• Accommodate a wide range of data transfer characteristics for I/O devices, including
telephone and Internet connections
• Enhance user convenience through a “plug-and-play” mode of operation
a)Port Limitation:
Here to add new ports, a user must open the computer box to gain access to the internal
expansion bus and install a new interface card. The user may also need to know how to configure
the device and the software. And also it is to make it possible to add many devices to a computer
system at any time, without opening the computer box.
b)Device Characteristics:
The kinds of devices that may be connected to a computer cover a wide range of functionality -
speed, volume and timing constraints. A variety of simple devices attached to a computer
generate data in different asynchronous mode. A signal must be sampled quickly enough to track
its highest-frequency components.
c)Plug-and-play:
Whenever a device is introduced, do not turn the computer off/restart to connect/disconnect a
device. The system should detect the existence of this new device automatically, identify the
appropriate device-driver software and any other facilities needed to service that device, and
establish the appropriate addresses and logical connections to enable them to communicate.
ii)USB architecture

To accommodate a large number of devices that can be added or removed at any time, the
USB has the tree structure. Each node has a device called a hub. Root hub, functions, split bus
operations – high speed (HS) and Full/Low speed (F/LS).
4.8 Concluding remarks

The three basic approaches of I/O transfers are discussed. The simplest technique is
programmed I/O, in which the processor performs all the necessary control functions under
direct control of program instructions. The second approach is based on the use of interrupts. The
third I/O scheme involves DMA, the DMA controller transfers data between an I/O device and
the main memory without continuous processor intervention. Access to memory is shared
between the DMAQ controller and the processor.
5

Three popular interconnection standards – PCI, SCSI, USB are discussed. They represent
different approaches that meet the needs of various devices and reflect the increasing importance
of plug-and-ply features that increase user convenience.
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Computer Organization-Memory Unit 1|Page

Non-volatile memory
Both S-RAM and D-RAM are volatile so ROMs are used to store the information
permanently.
Different Type of ROMs are: ROM, PROM, EPROM and EEPROM.

Read-only memory (ROM) is an integrated circuit programmed with specific data when
it is manufactured.

Word line

P Connected to store a 0

Not connected to store a 1

Bit line

Fig: ROM Cell

ROM is made up of transistor and a switch P. If P is connected to GND it stores binary 0
and if it is not connected it stores binary 1. Bit lines are connected to power supply using
resistors. To read the information the word line is activated and transistors is closed & it
will read binary 0 or 1 based on P connected to GND or not.

Programmable Read-only memory (PROM)

Fig: PROM Cell

Programmable Read-only memory (PROM) is an integrated non-volatile memory circuit

that is manufactured to be empty.
It can be later programmed with specific data. The programming can be done only once.

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Computer Organization-Memory Unit 2|Page

After programming this data is always stored to this IC.

PROM chips contain a fuse at the switch P so all bits contain binary 0. While writing user
will pass current to burn out the fuse where ever required to store binary 1. This process
is known as burning the PROM.

Erasable programmable read-only memory (EPROM)

Fig: EPROM Cell

Erasable programmable read-only memory (EPROM) chips work as PROM chips, but
they can be rewritten many times.
In an EPROM, the cell at each intersection has two transistors. The two transistors are
separated from each other by a thin oxide layer.
One of the transistors is known as the floating gate and the other as the control gate. The
floating gate is connected to the row (word line) through the control gate.
When floating gate and control gate is connected the cell has a value of 1. To change the
value to 0 requires altering the placement of electrons in the floating gate.
An electrical charge, usually 10 to 13 volts, is applied to the floating gate to charge the
floating gate and thus turn bit to 0.
Erasing an EPROM is done by exposing it to ultraviolet (UV) light (253.7 nm wavelength)
it will erase the entire EPROM.

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Computer Organization-Memory Unit 3|Page

Electrically erasable programmable read-only memory (EEPROM

Fig: EEPROM Cell

EEPROM chips that can be electrically programmed and erased.

EEPROMs are organized as arrays of floating-gate transistors. EEPROMs can be
programmed and erased in-circuit, by applying special programming signals.
Originally, EEPROMs were limited to single byte operations which made them slower,
but modern EEPROMs allow multi-byte page operations.

Flash memory

Flash memory is a type of EEPROM it has in-built circuit to erase by applying an electrical
field to the entire chip or blocks.
Flash memory works much faster than traditional EEPROMs because it writes data in
chunks, usually 512 bytes in size, instead of 1 byte at a time.
Flash memories are implemented as Flash cards, removable solid-state storage devices
(SSD) and flash drives.

Memory Hierarchy/Speed, Size and Cost

All different memory/storage devices used in computer is organized in hierarchy. The

processor contain limited number of registers to store operands and intermediate results
and L1 cache to store frequently used information. Register and cache are the D-RAM
cells on processor chip which are high speed but limited in number/size.
On the mother board we have secondary L2 cache which is slow but larger compared to
L1 cache & registers.
In the next level of hierarchy there will be main memory made up of D-RAM cells slow
but larger L1 cache & registers which stores the program and data while execution by
processor.

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Computer Organization-Memory Unit 4|Page

Fig: Memory Hierarchy

The large secondary storage devices either magnetic or optical devices form the next level
of hierarchy which are slower and quite larger than main memory.
Comparison:
The speed & cost increases as we go up in the hierarchy and size increases as we go down
in the hierarchy.

Virtual Memory
 The main memory of a computer ranges from 100MB to 8GB, if some program of
larger size than the size of main memory need to be executed then entire program
is stored in secondary storage devices (HDD) and only those part/block of the
program which is currently needed for execution by the processor is placed in the
main memory.
 When a new block or next part of the program is needed by the processor the
existing block is moved back to HDD and the new block is brought into main
memory.
 Operating system is responsible for moving the program blocks between main
memory and HDD this technique is called as Virtual Memory.
 The binary address given by the processor is called virtual address.
 The MMU (Memory Management Unit) translates virtual address to physical
address and search the data in cache memory /main memory if present will be
accessed, if not found then data transfer is done from HDD through DMA (Direct
Memory Access).

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Computer Organization-Memory Unit 5|Page

Processor

MMU

Cache

Main Memory

Disk Storage
Address Translation

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Computer Organization-Memory Unit 6|Page

 All programs & data in the disk storage is divided into fixed length units called
page, page size range from 2KB to 16KB.
 The processor generates the virtual address requesting for instructions or data.
 Virtual address consists of virtual page number (higher order bits) followed by
offset (lower order bits) offset specify the location of the word in each page.
 The allocated memory for a process is divided number of blocks (page frames)
such that page size =page frame size.
 Information about which page is residing in which page frame is kept in page
table.
 The starting address of the page table is kept in a page table register.
 Virtual page number + page table base register=page frame address
 The page table is frequently accessed by MMU so ideally it should be stored in
MMU as the size of page table is large it is kept in main memory so as to reduce
the time for accessing a small portion of the page table is placed on the buffer on
MMU called as Translation Look-ahead Buffer( TLB).
Address Translation proceeds as follows:
 Processor gives virtual address- MMU looks in TLB if entry is found returns the
physical address of the page. If the page entry is not found in TLB then the page
table on main memory is searched and the physical address of the page is returned
if found.
 If the requested page is not in main memory it is a page fault then MMU requests
OS to bring the required page from HDD.
 OS will suspend the execution of the current process until the desired page is
brought.
 If the desired page is brought from HDD and main memory is full then an existing
page has to be replaced, so least recently used pages is chosen for replacement

Hard disk Drive organization

 The HDD is the stack of rotating platters that coated with magnetic coating. There
are read/write heads on the top and bottom of each platter, so information can be
recorded on both surfaces. All heads move together across the platters. The
platters rotate at constant speed usually 3600 rpm.
 The disk drive electronics are located on a printed circuit board attached to the
disk drive.
 Data is organized on the disk platters by tracks and sectors.

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Computer Organization-Memory Unit 7|Page

 The number of bytes per sector is fixed for a given disk drive, varying in size from
512 bytes to 2KB. All tracks with the same number, but as different surfaces, form
a cylinder.
 The information is recorded on the disk surface 1 bit at a time by magnetizing a
small area on the track with the write head. That bit is detected by sending the
direction of that magnetization as the magnetized area passes under the read head.
 The 12 bytes of ECC (Error Correcting Code) information are used to detect and
correct errors in the 512 byte data field.
 The operating system specifies the track, sector and surface of the desired block.
The disk controller translates that requests to a series of low level disk operations.
 Seek time: - Is the average time required to move the read/write head to the
desired track.
 Access time: - Is the time required to move the head from one track to adjoining
one.
 Rotational latency: - Is the average time required for the needed sector to pass
under head once and head has been positioned once at the correct track.
 Average Access time: - Is equal to seek time plus rotational latency.
 Burst rate: - Is the maximum rate at which the drive produces or accepts data once
the head reaches the desired sector,
Optical Disks
Compact Disk (CD) Technology:- CD system is based on laser light source. A laser beam
is directed onto the surface of the spinning disk. Physical indentations in the surface are
arranged along the tracks of the disk. They reflect the focused beam towards a photo
detector, which detects the stored binary patterns.

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Computer Organization-Memory Unit 8|Page

 A cross section of CD shows the bottom payer is Polycarbonate plastic, which

functions as a clear glass base. The surface of this plastic is Programmed to store
data by indenting it with pits. The un-indented parts are called lands. A thin layer
of reflecting aluminum material is placed on top of a programmed disk. The
aluminum is then covered by a protective acrylic. Finally the topmost layer is
deposited and stamped with a label.
 The laser source and the Photo detector are positioned below the polycarbonate
plastic. The emitted bean travels through this plastic, reflects off the aluminum
layer and travels back toward photo detector
 Some important optical disks are listed below
1. CD-ROM
2. CD-RWs (CD-re writable)
3. DVD technology (Digital Versatile disk)

Cache Replacement Algorithm

In direct mapping the position of mapping each block of main memory to cache memory
is fixed but in associative and set associative mapping if cache blocks are full the cache
controller should decide which of the blocks on the cache to replace for bringing in the
new block.
The objective of the replacement is to restore the block which are frequently used and
replace the least frequently used blocks.
To track least frequently used blocks cache controller uses a counter:
When new block is brought into cache the counter is made equal to 0 and all other block’s
counter is incremented by 1. When an existing bock is referred again then the counter is
set to 0 and all other block’s counter is incremented by 1.
So the frequently used blocks will have least counter value than the others and the block
with high counter value is chosen for replacement.

Write Buffer with cache

If write through protocol is used the cache block which are written has to be updated
immediately to main memory, which consumes lot of write operations and processor
should wait.
So as to improve the performance “Write Buffer” is used, the processor places all the
write requests to the write buffer and continues with next instruction, these write
requests in the write buffer are updated to main memory whenever the read request is
not answered.
During read request the contents is first checked in the write buffer as it is the updated
value.
When write back protocol is used if processor requests a new block and cache is full then
the dirty data of the block chosen for replacement has to be updated to main memory
during which processor has to wait. Now the dirty contents are moved to the write buffer
and the new block is brought immediately to the cache and the contents of the write
buffer is updated later.

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Computer Organization-Memory Unit 9|Page

Pre-fetching with cache

When a read miss occurs the requested data has to be brought from main memory during
which the processor has to wait (miss penalty).
So to avoid this pre-fetching of the data before the request is done by using special
instructions, the pre-fetch instructions are placed into the program by compiler.
The drawback is unnecessary data may be pre-fetched and if cache is full the pre-fetched
block may be replaced before it is used.

Lock up free cache

When read miss occurs cache gets locked until the requested data is brought from the
main memory.
So Lockup free cache is used which allows processor to access cache during miss. This
supports multiple outstanding misses.

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Computer Organization-Embedded
System 1|Page
Computer systems are used in a numerous of applications; therefore, they come in a
variety of organizations, sizes, and capabilities. The important factors considered for
any application is performance, reliability, and cost.
Microprocessors are now commonly used in cameras, cell phones, kitchen
appliances, cars, and many toys. Low cost and high reliability, small size and low
power consumption are key importance in such applications.
Microprocessor chips that include I/O interfaces and some memory are called as
micro controllers.
A physical system that employs computer control for a specific purpose,
rather than for general-purpose computation, is referred to as an embedded system.
EXAMPLES OF EMBEDDED SYSTEMS
I. Microwave Oven
Microwave oven is based on a magnetron power unit that generates microwaves used
to heat food.
When turned on, the magnetron generates its maximum power output. The
power level and the total heating time can be controlled based on user’s cooking
options.
The specification for a microwave oven
1. Cooking options
a) Manual selection of the power level and cooking time
b) Manually selected sequence of cooking steps
c) Automatic selection cooking steps, power level & time based on user specified
type of food and the weight of the food.
d) Automatic defrosting of meat by specifying weight
2. Output display of Oven:
a) Time of day clock
b) Decrementing clock timer while cooking
c) Information messages to fee user
3. An audio alert signal beep tone to indicate fee end of a cooking
4. An exhaust fan and oven light
5. A door interlock -magnetron off if the Oven door is open
6. The input/output capability
a) Input keys that comprise the number pad 0 to 9 and function keys such as Reset,
Start, Stop, Power Level, Auto Defrost, Auto Cooking, Clock Set, and Fan
Control.
b) Visual output in the form of a LCD.
c) A small speaker feat produces fee beep tone.

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Computer Organization-Embedded
System 2|Page

Implementation:
The controller for a microwave oven can be implemented by a small microprocessor
based computer unit.
The computational tasks include:
 Maintain time of day clock
 Determining the actions needed in the various cooking options
 Control signals generation to turn on or off magnetron and fan
 Displaying information.
The program for controlling oven must be stored in a ROM
Oven also need RAM to store user specified data & computation
A simple processor with small ROM and RAM units and parallel I/O on a single VLSI
chip is sufficient to implement the controller of oven in a cost effective way.

II. DIGITAL CAMERA

Digital camera, contains array of optical sensors for capturing images. These sensors
are based on photodiodes which convert light into electrical charge.
Two different types of sensors are used:
 Charge-Coupled Devices (CCDs)
 Sensors based on CMOS technology

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Computer Organization-Embedded
System 3|Page

Each sensor generates a charge that corresponds to one pixel, number of pixels
determines the quality of picture.
The charge is an analog which is converted into a digital using A/D conversion
circuits.
In digital image the color and intensity of each pixel is represented by a number of
bits.
The camera controller contains a processor, memory (both RAM and EEPROM), and
set of interface circuits to connect to other parts of the system.
The processor obtain raw image from the A/D circuits and generate images in
standard formats such as TIFF, JPEG etc.
A captured image can be displayed on LCD screen in the camera and are stored in a
larger flash storages.
PCI or USB interfaces are used to transfer the images to a computer or a printer.
The camera controller generates signals to control the operation of the motor and the
flash unit.
A digital camera requires more powerful processor with less power consumption to
perform complex signal processing functions.

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PROCESSORS FOR EMBEDDED APPLICATONS
A chip that contains a processor, some memory, and I/O interface circuitry useful in
embedded applications is called as embedded processor. As they perform
important control functions are also known as microcontroller chips.

The main parts are:

 Processor core
 RAM to hold the data during computations
 ROM to hold the software of embedded system
 Storage are EEPROM and Flash memory
 I/O ports to provided for both parallel and serial interfaces
 Timer circuit to generate control signals
 AID and D/A conversion circuits
Some of the commercially available embedded processor chips:
CISC-type processor cores
 Motorola’s 68HC11, 683xx and MCF5xxx families, Intel’s 8051 and MCS-
96family
RISC-type processor
 ARM microcontrollers

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A SIMPLE MICROCONTROLLER

Figure 9.4 shows the block diagram of simple microcontroller which contains:
 Processor core
 on-chip memory
 processor bus connections on the chip to connect to external memory
 two 8-bit parallel interfaces, called A and B
 one serial interface
 32-bit counter/timer circuit to generate internal interrupts and serve as a
system stop
watch
PARALLEL I/O PORTS
A and B ports can be used as either inputs or outputs Figure 9.5 illustrates the
bidirectional control for one bit in Port A.
Port pin PAi is treated as an input if the data direction flip-flop contains 0. In this case
Read_port signal is placed on port and data onto the data line Di of the processor bus
and processor reads the data on the pins.
The port pin PAi serves as an output if the data direction flip-flop is set to 1. In this
case, the data is loaded into the data output flip-flop and Write Port signal, is placed
on the pin.

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Figure 9.6 shows the eight 8-bit registers used for data transfer operations on ports A
and B and addresses assigned to these registers.

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The status register, PSTAT, contains the status flags

The PASIN flag is set to 1 when there is new data on the pins of port A. 0 when the
processor accepts the data
The PASOUT flag is set to 1 when the data in register PAOUT are transferred to the
connected device and now processor can load new data into PAOUT. It is 0 when the
processor writes data into PAOUT.
The flags PBSIN and PBSOUT perform the same function for port B
The status register also contains four interrupt flags.
If IAIN= 1 then interrupt is enabled and the corresponding I/O action takes place. The
interrupt enable bits are held in PCONT.
A single interrupt request signal is used. The processor must examine the interrupt
flags to determine the actual source of the request.
Information in the status and control registers is used for controlling the data transfers
to and from the devices connected to ports A and B.
When the device places data on portA, CAIN is set to 1 it sets the PASIN to 1 after
processor reads data 0 PASIN.
For an output transfer, the processor writes the data into the PAOUT which makes
PASOUT bit to 0 and sends signal to CAOUT. When the device takes data, sets PASOUT
to 1.
SERIAL I/O INTERFACE
The serial interface provides the UART (Universal Asynchronous Receiver
Transmitter) to transfer data Figure 4.37. Double buffering is used in both transmit and
receive paths, Figure 9.7. Figure 9.8 shows the addressable registers of the serial
interface.
Input data are read from the 8-bit Receive buffer, and output data loaded into the 8-
bit Transmit buffer. The status register, SSTAT, provides status of receive and transmit
units.
SSTAT0 is set to 1 when there is data in the receive buffer.
SSTAT1 is set to 1 when the transmit buffer is empty and can be loaded with new data.
Interrupt flags:
 SSTAT2 is set to 1 if an error occurs during the receive process.
 SSTAT4 is set to 1 when the receive buffer is full.
 SSTAT5 is set to 1 when the transmit buffer is empty
SCONT, is used to hold the interrupt enable bits which can enable or disable
corresponding interrupts.
DIV 32-bit register divides the system clock signal to generate the serial transmission
clock.

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COOUNTER/TIMER
A 32-bit down-counter circuit is used as counter or a timer.
The circuit loads starting value into the counter, and then decrement the counter by
using internal system clock or an external clock signal then raise an interrupt when
the counter reach zero.
The counter registers:
 CNTM loaded with an initial value then transferred into the counter circuit.
 CTCON specify the operating mode of the counter/timer circuit.
 CTSTAT, reflects the state of the circuit.

Counter Mode
The counter mode is selected by setting CTCON7 to 0.The starting value is loaded into
the counter by writing it into register CNTM.
The counting process begins when bit CTCON0 is set to 1 by a program instruction
then the CTCON0 bit is cleared to 0.
The counter is decremented by pulses on the Counter_in line. Upon reaching 0, the
counter circuit sets the status flag CTSTAT0 to 1, and will raise an interrupt.
The counting process is stopped by setting CTCON1 to 1.
Timer Mode
The timer mode is selected by setting CTCON7 to 1. This mode is suitable for
generating a square-wave signal on the output line Timer_out.
The counting process begins when bit CTCON0 is set to 1 by a program instruction
then the CTCON0 bit is cleared to 0.
As the counter counts down, the value on the output line is held constant. Upon
reaching zero, the counter is reloaded automatically with the starting value, and the
output signal on the line is inverted.
INTERRUPT CONTROL MECHANISM
The microcontroller has two interrupt request lines, IRQ and XRQ. The IRQ for I/O
interfaces within the microcontroller and XRQ for interrupts raised by external
devices.
When IRQ line is active the processor polls to determine the sourceof the interrupt
request by examining PSTAT, SSTAT and CTSTAT.
PSR, has two bits for enabling interrupts. The IRQ interrupts are enabled if PSR6 = 1,
and the XRQ interrupts are enabled if PSR7 = 1.
A vectored interrupt scheme is used, with the vectors for IRQ and XRQ each vector
contains the address of the corresponding interrupt service routine.
During interrupt request in addition to saving the return address in LR, the contents of
the processor status register, PSR, are saved in a processor register IPSR.

Guruprasad S & Srivani P BMSIT&M

 Computer Organization
Module 1
1. Explain the basic functional units of computer
2. Explain the basic operational concept with a neat diagram and demonstrate with an
example how fetch and execute sequence occurs.
OR
Draw and explain the connection between memory and processor with the respective
registers.
3. Explain the methods to improve performance of computer.(Basic Performance
Equation, SPEC rating, clock rate, pipeline, CISC & RISC).
1. Explain clearly SPEC rating and its significance. Assuming that the reference
computer is ultra SPARCIO work station with 300 MHz ultra SPARC processor. A
company has to purchase 1000 new computers hence ordered testing of new computer
with SPEC 2000.Following observations were made

Programs Runtime on reference computer Runtime in new computer

1 50 Minutes 5 Minutes
2 75 Minutes 4 Minutes
3 60 Minutes 6 Minutes
4 30 Minutes 3 Minutes
1. Explain the following
a. Memory Location and addressing using Big endian and little endian
b. Overflow & Conditional codes
2. Explain the 3 ways of number representation for both signed and unsigned numbers in
detail with examples. Also show how addition and Subtraction is performed.
3. Perform the following operations on the 5-bit signed numbers using 2’s complement
representation system. Also indicate whether overflow has occurred
i) (-10) + (-13) ii) (10) - (+4) iii) (-3) + (-8) iv) (-10) - (+7)
4. Explain different addressing modes with examples.
5. Explain basic instruction types. Show how an operation C=A+B can be
implemented in a computer by using 1) three address instruction 2)two address
instruction 3) one address instruction Explain
6. Explain basic input and output opearations?differenciate between programmed
controlled I/O and memory mapped I/o
7. What is a stack frame and frame pointer? Explain commonly used layout information
in a stack subroutine frame.
8. Explain shift and rotate instructions with examples for a 16 bit number
9. Briefly explain about encoding machine instructions with examples
10. Define subroutine. explain subroutine linkage using link registers with sample
program as an example
Module 2
11. Define and explain the following
a. Interrupt and Interrupt service routine
b. Vectored interrupts
c. Interrupt nesting
d. Interrupt enabling and disabling
 12. Explain with a neat diagram the working of daisy chain with multiple priority levels
and multiple devices in each level
13. Discuss the different schemes available to disable and enable interrupts
14. Explain bus arbitration, explain in detail any one approach of bus arbitration
15. Define memory mapped I/O and I/O mapped I/O with examples explain how
interrupt request from several IO devices can be communicated to a processor through
a single INTR line
16. What are the different methods of DMA and DMA controllers? explain them in brief
17. With a block diagram explain how keyboard is connected to processor.
18. With a block diagram explain the printer interfaced to processor.
19. Explain the serial port and serial interface.
20. Explain PCI bus
21. List SCSI bus signal with their functionalities and controllers.
22. Explain the tree structure, protocols, addressing scheme and architecture of USB.

Module-3
1. Explain internal organization of 16 Megabit DRAM chip configured as 2M*8 cells
Also explain how it can be made to work fast in fast page mode.
2. Explain the working of 16-megabyteDRAM chip configured as 1M x 16 memory
chip.
3. Discuss the internal organization of a 1K x 1 memory chip
4. Explain the read and write operations of a static RAM cell and CMOS cell
5. Differentiate between SRAM and DRAM giving 5 key differences.(With a cell
diagram).
6. With a block diagram, explain the organization of 8M x 32 memory using 512 K x 8
memory chips
7. Explain synchronous DRAM with a neat diagram.
8. With figure analyse the memory hierarchy in terms of speed cost and size
9. What is cache? With block diagram explain Direct, Associative and set-associative
mapping between cache and main memory.
10. Briefly explain any four non-volatile memory concepts(ROM, PROM, EPROM,
EEPROM, Flash)
11. Discuss in detail any one feature of memory design that leads to improved
performance of computer. (memory Interleaving, Cache hit and miss)
12. Calculate the average access time experienced by a processor if cache hit rate is 0.88.
miss-penalty is 0.015 milliseconds and cache access time is 10 microseconds.
13. Write short notes on Hard disk/ Magnetic Disk, CD/DVD, Magnetic Tapes.
14. What is virtual memory? Explain simple method of translating virtual address into
physical address.
15. Define the following:
a. Memory Latency
b. Memory bandwidth
c. Hit rate
d. Miss-penalty
e. Memory access time
f. Memory cycle time
 g. Random access memory
h. Static memories
i. Seek time
j. Latency
k. Access time
Module- 4
1. Design 4 bit carry look ahead logic and explain how it is faster them 4 bit ripple
adder. Also explain addition/subtraction Logic unit.
2. Explain with figure the design and working of a 16-bit carry look ahead adder built
from 4-bit adder. ( FAST ADDERS)
3. Explain booths algorithm apply booths algorithm to multiply signed numbers +13 and
-6.
4. Write the circuit diagram and algorithms for restoring and non-restoring division
methods.
5. Perform division of 8 by 3 using non restoring division method.
6. Perform division of 16 by 4 using restoring division method
7. Explain and Multiply (+14) and ( -6) using Bit-Pair Recording Method
8. List out the rules for addition, subtraction, multiplication and division of floating
point numbers. Explain with circuit diagram
9. Explain IEEE standard for Floating point numbers.
OR
Explain normalization, excess - exponent and special values with respect to IEEE
floating point representation.

Module-5
1. Draw and explain the single bus organization of the data path inside a processor
2. Explain the control sequence for execution of
1) Add (R3) R1
2) Mul R1, (R2)
3) Add #6, r1
4) an unconditional branch instruction
3. Explain with block diagram the basic organization of a micro programmed control
unit to support conditional branching in the micro program.
4. Write the control sequence for the instruction Add R1, R2, R3 with a neat diagram
using Three bus organization (Multiple Bus Organization).
5. Explain with a neat diagram micro-programmed control method for design of control
unit using micro-instructions.
6. With a neat diagram explain hardwired control unit show the generation Zin and End
control signals
7. With a neat diagram explain complete processor.
8. Briefly explain the Diagram of camera and Microwave Oven. Define Embedded
System.
9. Explain the organization of a simple microcontroller and discuss some features that
may be used in practice.
10. Explain the structure of general purpose multiprocessor in detail.