North South University

Department of Electrical & Computer Engineering

LAB REPORT
Course Name: CSE231L
Experiment Number: 6

Experiment Name: Introduction to Multiplexers and Decoders

Experiment Date: 13/12/2020

Report Submission Date: 26/12/2020
Section: 3

Student Name: Zahid Hasan Score

Student ID: 1911509642

Remarks:
 LAB-06: Introduction to Multiplexers and Decoders

Objectives:
• To understand the concept of multiplexing in the context of digital logic circuits.
• To learn about the internal logic of digital multiplexers.
• To implement digital logic functions using multiplexers.
• To observe and analyze the operations of the 3 to 8 Line Decoder

Apparatus:

• Trainer board
• 1 x IC 7404 Hex Inverter (NOT gates)
• 2 x IC 7411 3-input AND gates
• 1 x IC 7432 2-input OR gates
• 1 x IC 74151 8:1 Multiplexer
• 1 x IC 74138 3x8 Decoder

Theory:
Multiplexer:
Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’
selection lines and single output line. One of these data inputs will be connected
to the output based on the values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros
and ones. So, each combination will select only one data input. Multiplexer is
also called as MUX. Example- 2:1 MUX, 4:1 MUX, 8:1 MUX, 16:1 MUX and so on.

Decoder:
A decoder is a combinational circuit that converts binary information from n
input lines to a maximum of 2n out puts lines. One of these outputs will be active
High based on the combination of inputs present, when the decoder is enabled.
That means decoder detects a particular code. The outputs of the decoder are
nothing but the min terms of ‘n’ input variables lines, when it is enabled.
Example- 2x4 Decoder, 3x8 Decoder, 4x16 Decoder and so on.
Circuit Diagram:
Experiment-1:

Figure 1: Constructing a 4:1 Multiplexer using basic logic gates.

Data Table:
Experiment-1:
Table 01: Truth table of the given circuit using universal gates.

A B C F (Theoretical) Data Inputs F (Practical)

0 0 0 1 1
I0 = 1
0 0 1 1 1

0 1 0 0 0
I1 = 0
0 1 1 0 0

1 0 0 0 0
I2 = C
1 0 1 1 1

1 1 0 0 0
I3 = C
1 1 1 1 1
 Table 02: Truth table for 8:1 MUX implementation for Function

F (A, B, C, D) = Σ (0, 1, 3, 5, 8, 9, 14, 15)

A B C D F (Theoretical) Data Inputs F (Practical)

0 0 0 0 1 1
I0 = 1
0 0 0 1 1 1

0 0 1 0 0 0
I1 = D
0 0 1 1 1 1

0 1 0 0 0 0
I2 = D
0 1 0 1 1 1

0 1 1 0 0 0
I3 = 0
0 1 1 1 0 0

1 0 0 0 1 1
I4 = 1
1 0 0 1 1 1

1 0 1 0 0 0
I5 = 0
1 0 1 1 0 0

1 1 0 0 0 0
I6 = 0
1 1 0 1 0 0

1 1 1 0 1 1
I7 =1
1 1 1 1 1 1
Table 03: Truth table for 8:1 MUX implementation of report section.

For function F (A, B, C, D) = Σ (1, 2, 4, 5, 10, 12, 13)

A B C D F (Theoretical) Data Inputs F (Practical)

0 0 0 0 0 0
I0 = D
0 0 0 1 1 1

0 0 1 0 1 1
I1 =D’
0 0 1 1 0 0

0 1 0 0 1 1
I2 = 1
0 1 0 1 1 1

0 1 1 0 0 0
I3 = 0
0 1 1 1 0 0

1 0 0 0 0 0
I4 = 0
1 0 0 1 0 0

1 0 1 0 1 1
I5 = D’
1 0 1 1 0 0

1 1 0 0 1 1
I6 = 1
1 1 0 1 1 1

1 1 1 0 0 0
I7 = 0
1 1 1 1 0 0
Table 04: Experimental Data of 3 to 8 Line Decoder.

Select Inputs Outputs

A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

Question and Answer:

Experiment-2:
Figure F2: IC Simulation diagram for the implementation of function F (A, B, C, D) = ∑ (1, 2, 4,
5, 10, 12, 13) using IC74151.
Experiment-3:

Ques: Difference between active-high and active-low device:

Ans: Active-High Device:

A signal ‘active-high’ means that signal will be performing when its logical
value is ‘1’. Active-high device works when the enable input is active high or
‘1’. If the circuit uses "active high" logic, 5 volts represents a digital "1" and 0
volts represents a digital "0".

Ans: Active-Low Device:

A signal ‘active-low’ means that signal will be performing when its logical value
is ‘0’. Active-low device works when the enable input is active low or ‘0’. If the
circuit uses "active low" logic, 5 volts represents a digital "0" and 0 volts
represents a digital "1".

Discussion:
The overall lab experiment was about the structures and implementations of
multiplexers and decoders.
At the beginning of the experiment, the task was to build a 4:1 MUX. So I designed it
using logic gates as well as IC diagram. I needed 4 2-input AND gates and 3 2-input OR
gates to design 4:1 MUX. I implemented a function, F(A, B, C) = Σ (0, 1, 5, 7) using 4:1
MUX and completed necessary truth table by drawing Karnaugh Map.
Then using 4:1 MUX and 2:1 MUX, I designed 8:1 MUX as well as IC diagram.
The 2nd experiment was to implement a Boolean function using 8:1 MUX and the
function was F(A, B, C, D) = Σ (0, 1, 3, 5, 8, 9, 14, 15). I used A, B, C as selector variables
and D as input variable. By drawing Karnaugh Map, I got the required 8 inputs. By
completing necessary truth table, I got the expected outputs. And the outputs received
from truth table and outputs received from designed circuit were same. Following this
same way, I implemented another function, F(A, B, C, D) = Σ (1, 2, 4, 5, 10, 12, 13).
Due to shortage of time, I did only 3x8 Decoder circuit diagram for the 3rd experiment.
During the experiment, Logisim worked perfectly. So I didn’t face any issue.
From the experiment, I learned about the internal structures and logical
implementations of different types of multiplexers and decoders.