Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates

DIGITAL SYSTEMS DEIGN LAB

M. Sc. NGUYỄN VÕ THẤT THUYẾT

ECE Program | Faculty of Engineering | Vietnamese-German University
[email protected]

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates

Revision
Version Modified date Modified by Description
v0r0 03/02/2023 Thuyet N. New creation

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
Contents
Revision .................................................................................................................................................. ii
Lab Introduction ..................................................................................................................................... 1
Description .......................................................................................................................................... 1
Hardware ............................................................................................................................................. 1
Software ...............................................................................................................................................2
Lab documents .................................................................................................................................... 5
Lab content .......................................................................................................................................... 5
Assessment .......................................................................................................................................... 6
LAB 1: Fundamentals of Logic Gates ....................................................................................................7
Goal ......................................................................................................................................................7
Prerequisite .......................................................................................................................................... 7
Required hardware and software .........................................................................................................7
Theory ..................................................................................................................................................8
Logic gates ....................................................................................................................................... 8
Even Parity Circuit (generator+checker) .........................................................................................9
Tasks ..................................................................................................................................................12
Planning .............................................................................................................................................13
Step-by-step instructions ...................................................................................................................14
Task 1: Logic gates ........................................................................................................................ 14
Create an empty project on Quartus .............................................................................................. 14
Write Verilog HDL code ............................................................................................................... 17
[Simulation] ................................................................................................................................... 19
[Emulation] ...................................................................................................................................... 8
Task 2: Even parity circuit .............................................................................................................17
Create an empty Quartus project (refer to task 1) ......................................................................... 18
Write Verilog HDL code ............................................................................................................... 18
[Simulation] ................................................................................................................................... 18
[Emulation] .................................................................................................................................... 21
Checklist ............................................................................................................................................ 24

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
Lab Introduction

Description

This lab is to design and implement the basic digital circuits (parity circuit, adders, counters etc.) on
an FPGA board by Verilog HDL (hardware description language).

Hardware

It is Terasic DE10-Nano with an Intel FPGA

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
Software
Quartus Lite Edition and ModelSim Starter Edition are tools used in this lab for FPGA
programming as well as simulation.

Download and installation

1) Create an account on Intel.com
2) Search for ‘Quartus download' and download Quartus Lite Edition + ModelSim-Intel
FPGA Edition (Starter Edition)
Please choose VERSION 20.1.1
3) Select files as below and download

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates

Files: Quartus lite + ModelSim-IntelFPGA setup files, Cyclone IV and Cyclone V device files
Note: Put all files in the same folder and then run Quartus set-up file.

Follow set-up instruction, and select installed components as below

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
Lab documents

LabDocs:Lab guidelines
Preparation:It has to be finished before each lab session
RefDocs:References
1) 00_fpgas_for_dummies_ebook.pdf: an book for beginners
2) 01_VGU_ECE_BasicsofFPGAandVerilog.pdf: basics of FPGA and Verilog HDL
3) 02_VGU_ECE_DigitalSystemsDesignLab_slides.pdf : introduction slides
4) 04_DE10-Nano_User_manual.pdf: hardware manual

Lab content

Lab 1 – Fundamentals of Logic Gates

Lab 2 - Adders
Lab 3 - Counters
Lab 4 – Simple Code

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
Assessment

The assessment criteria are followed the below table

Lab Estimated Item Points Note
Preparation 10 No preparation for first lab
Lab 1 Lab report 15
25 points Get -1 point per each delayed
Punctuality -1/min
minute
Preparation 10
Lab 2 Lab report 15
25 points Get -1 point per each delayed
Punctuality -1/min
minute
Preparation 10
Lab 3 Lab report 15
25 points Get -1 point per each delayed
Punctuality -1/min
minute
Preparation 10
Lab 4 Lab report 15
25 points Get -1 point per each delayed
Punctuality -1/min
minute
Total points 100

Important note:

AM session starting from 09:00

PM session starting from 13:00
PASS: If the total points >=75 AND
FAIL: If the total points <75 OR miss an attendance check

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
LAB 1: Fundamentals of Logic Gates
Goal

This lab exercise helps students be familiar with FPGA design flow on Quartus tool by
implementing simple logic gates (AND, OR, XOR, NOT etc.). Besides, students learn how to design
an even parity circuit (generator+checker) with exclusive-OR (XOR) gates.

Prerequisite

This is required knowledge of logic gates and parity checker.

Required hardware and software

1) Intel Quartus Lite 20.1.1

2) ModelSim IntelFPGA Starter 20.1.1
3) 01 x FPGA board, DE10-Nano
4) 01 x micro USB cable + 01 x AC to DC adapter (5 VDC, 2A output)

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
Theory

Logic gates

Logic gates Truth tables

x y
0 1
1 0

NOT gate

x y z
0 0 0
0 1 1
1 0 1
OR gate
1 1 1

x y z
0 0 0
0 1 0
AND gate 1 0 0
1 1 1

x y z
0 0 0
0 1 1
Ex-OR (XOR) gate 1 0 1
1 1 0

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
Even Parity Circuit (generator+checker)

XOR gate characteristic

The truth table of a 2-input XOR and a 3-input XOR gates:

Based on the above truth tables, it can be easily seen that the output of an XOR gate is equal to ‘1’
only if a number of bits ‘1’ at inputs are an odd number. In conclusion, with XOR gates, a
number of bits ‘1’ at inputs and outputs are always an even number.

What is a parity circuit?

A parity circuit is used to generate an even/odd parity bit at a transmitter as well as to check data
correctness at a receiver. In this lab, an even parity circuit is considered.

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From the generator side, the four-bit data is input to a 4-bit input XOR gate to generate an even
parity bit. The output value is calculated based on the below table.

Then, the four-bit data and parity bit are transferred to the receiver (parity checker).

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
From the checker side, it receives 4-bit data and 1-bit parity from transmitter (parity generator), then
it performs an even parity check among these 5 bits, a result bit (error bit) will be set to ‘1’ if an
error occurs, or ‘0’ if there is no error. It is explained that the total number of bits ‘1’ at inputs and
outputs of an XOR gate (see XOR gate characteristic) are always an even number. And the total bit
‘1’ from the transmitter (4-bit data and 1-bit parity) are also an even number (see parity generator
table), therefore, the error bit of the checker must be ‘0’ if the received data are correct.

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
Tasks

1) Task 1: Implementing logic gates

2) Task 2: Implementing an even parity circuit

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
Planning

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
Step-by-step instructions

Task 1: Logic gates

Create an empty project on Quartus

Run Quartus
File → New Project Wizards… → Next
This step is to choose the location for the project as well as to set the project and top module name.

And click Next t→ Next → Next to go to the step of selecting FPGA device of DE10-Nano board

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Device Information:

Device: Cyclone V SE Base

Name: 5CSEBA6U23I7

Click Next → Next → Finish

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates

An empty Quartus project has been created, next the implementation of the logic gates is introduced.
This process includes following steps:
1) Make design documents for the logic (see the theory)
2) Write Verilog HDL code
3) Compile the code
4) Run simulation
5) Board test
a. Do pin assignments
b. Generate bit stream file
c. Program bit stream file to FPGA
d. Run and test

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
Write Verilog HDL code

To write Verilog HDL code for logic gates, a ‘.v' file needs to be created by clicking File →
New→Verilog HDL File

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates

Type ‘module' then press Ctrl-S

Create the folder rtl, double click on rtl folder and then save ‘lab1.v' into it

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
[Simulation]

lab1.v
module lab1(
x,
y,

z
);

input x;
input y;

output z;

assign z = x&y;

endmodule

Compile the code and check syntax errors

Press the button or CTL-L or Processing → Start Compilation
If there are any syntax errors, then they must be fixed before moving next steps.

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Choose simulation tool: Assignments → Setting…
EDA Tool Settings → Simulation → Tool Name: ModelSim-Altera

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates

Specify path for simulation tool: Tools → Options…

General → EDA Tool Options → ModelSim-Altera: path to ModelSim-Altera installation folder
(example: C:\intelFPGA_lite\20.1\modelsim_ase\win32aloem)

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File → New → University Program VWF

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates

From Simulation Waveform Editor window, click Edit → Insert → Insert Node or Bus

Click Node Finder… to insert signals to waveform editor window.

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates

(If you cannot see any signals in Nodes Found, please run Compilation first)

List → [>>] → OK → OK to insert input and output signals to waveform window

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Use items in this toolbar to set values for input signals.

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates

Simulation → Run Functional Simulation

Fix errors if any
Example: If the following error occurs

Error (suppressible): (vsim-12110) The -novopt option has no effect on this product. -novopt option is
now deprecated and will be removed in future releases.
# Error loading design
Error loading design

Simulation → Simulation Settings

Delete option ‘-novopt’ and Save

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Simulation → Run Functional Simulation

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
[Emulation]

lab1.v
module lab1(
x,
y,

z
);

input x;
input y;

output z;

assign z = x&y;

endmodule

Compile the code and check syntax errors

Assign FPGA pins to counter pins (pin assignments)

Open DE10 user manual to find pin values of SW0, SW1 and LED0 to assign to the and gate pins

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
D10-Nano User Switches

D10-Nano User LEDs

Choose LED0 (PIN_W15, refer to DE10-nano User Manual) to assign to and gate ‘z' pin.
To do pin assignments for counter, click Assignments → Assignment Editor, and complete the
table as below:

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Generate a bit stream file for FPGA
After finishing pin assignments, click the button or CTL-L or Processing → Start
Compilation to compile the code and generate a bit stream file.

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Program a bit stream file to FPGA

Power on and connect the FPGA board to the PC/laptop.

DC Power

HDMI

USB Blaster (for FPGA

Click or Tools → Programmer

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Click Hardware Setup… at the left conner, selection DE-SoC[USB-1] for Currently selected
hardware and click Close.

Click Auto Detect and then OK

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Right click on line 5CSEBA6 → Change File, double click on ‘output_files' folder, select lab1.sof

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates

Check on Program/Configure column as below picture and the press Start button to
load bit file to FPGA

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates

When finishing uploading a bit stream file, the process bar will show 100% successful.

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
Run and test

LED[0] shows the output of AND gate

Switch SW0 and SW1 to change inputs of and

After finishing the implementation of AND gate, execute the same steps to implement NOT, OR
and XOR.

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
Task 2: Even parity circuit

Design

Block diagram

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
Create an empty Quartus project (refer to task 1)

Write Verilog HDL code

Create Verilog file(s) as below

[Simulation]

evenparity_gen.v
module evenparity_gen(
din,

pout

);

input [3:0] din;

output pout;

assign pout= din[3] ^ din[2] ^ din[1] ^ din[0] ;

endmodule

evenparity_checker.v
module evenparity_checker(
din,
pin,

p_err

);

input [3:0] din;

input pin;

output p_err; //0: no error; 1: error

assign p_err= din[3] ^ din[2] ^ din[1] ^ din[0] ^pin;

endmodule

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parity.v
module lab1(
din,

p_err,
p_out
);

//port declaration

input [3:0] din;

output p_err;// 0: no error; 1: error

output p_out;

//signal declaration

// logic implementation

evenparity_gen evenparity_gen_00(
.din(din),

.pout(p_out)

);

evenparity_checker evenparity_checker_00(
.din(din),
.pin(p_out),

.p_err(p_err)
);

endmodule

Compile to check the syntax errors

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[Emulation]

evenparity_gen.v
module evenparity_gen(
din,

pout

);

input [3:0] din;

output pout;

assign pout= din[3] ^ din[2] ^ din[1] ^ din[0] ;

endmodule

evenparity_checker.v
module evenparity_checker(
din,
pin,

p_err

);

input [3:0] din;

input pin;

output p_err; //0: no error; 1: error

assign p_err= din[3] ^ din[2] ^ din[1] ^ din[0] ^pin;

endmodule

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates

parity.v
module lab1(
din,

p_out
p_err
);

//port declaration

input [3:0] din;

output p_out;
output p_err;//0: no error; 1: error

//signal declaration

// logic implementation

evenparity_gen evenparity_gen_00(
.din(din),

.pout(pout)

);

evenparity_checker evenparity_checker_00(
.din(din),
.pin(p_out),

.p_err(p_err)
);

endmodule

Compile to check the syntax errors

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
Pin assignments

From To Assignment name Value Enabled

din[3] Location PIN_W20 Yes
din[2] Location PIN_W21 Yes
din[1] Location PIN_W24 Yes
din[0] Location PIN_Y24 Yes
p_err Location PIN_AA23 Yes
p_out Location PIN_W15 Yes

Compile again to generate the bit stream file

Load the bit stream file to FPGA

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Digital Systems Design Lab (DSDL) - Lab 1::Fundamentals of Logic Gates
Checklist

No Description Completed
1 Create an empty Quartus project for task 1
2 Implement task 1
3 Simulate task 1
4 Test logic of task 1 on FPGA board (board test)
5 Create an empty Quartus project for task 2
6 Implement task 2
7 Simulate task 2
8 Test logic of task 2 on FPGA board (board test)

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